JPH0156575B2 - - Google Patents

Info

Publication number
JPH0156575B2
JPH0156575B2 JP56176226A JP17622681A JPH0156575B2 JP H0156575 B2 JPH0156575 B2 JP H0156575B2 JP 56176226 A JP56176226 A JP 56176226A JP 17622681 A JP17622681 A JP 17622681A JP H0156575 B2 JPH0156575 B2 JP H0156575B2
Authority
JP
Japan
Prior art keywords
gain
level
circuit
average level
reference levels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56176226A
Other languages
Japanese (ja)
Other versions
JPS5877311A (en
Inventor
Hideo Suzuki
Shunsuke Yoda
Meiki Yahata
Takahiko Abe
Akira Nakano
Toshiro Nose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP17622681A priority Critical patent/JPS5877311A/en
Publication of JPS5877311A publication Critical patent/JPS5877311A/en
Publication of JPH0156575B2 publication Critical patent/JPH0156575B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices

Description

【発明の詳細な説明】 本発明は、データ伝送システム等において受信
信号レベルを一定振幅にするための自動利得制御
回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic gain control circuit for maintaining a received signal level at a constant amplitude in a data transmission system or the like.

音声帯域の電話回線を用いたデータ伝送等で
は、加入者線による信号の減衰が回線接続毎に変
化するため、データ受信装置の初段に受信信号レ
ベルを一定にするための自動利得制御(AGC)
回路を設ける必要がある。最近は、音声帯域の電
話回線用変復調装置(モデム)は、半導体技術の
進歩によりデイジタルLSI、マイクロプロセサ等
で構成される傾向にあり、AGC回路へもデイジ
タル信号処理技術が適用され始めている。しかし
ながら、デイジタル化されたAGC回路ではアナ
ログ形AGC回路と比べて、無調整で安定動作が
得られる反面、利得の設定がデイスクリートつま
りステツプ的になるため、単一の基準レベルで受
信信号レベルを判定し、それに基いて利得の制御
を行なうと、基準レベルを境として利得の最小ス
テツプで利得が振動して雑音を発生させる。この
ためデイジタル化AGC回路は、アナログAGC回
路に比べ性能が劣化するという欠点を有してい
た。
In data transmission using voice band telephone lines, the signal attenuation due to the subscriber line changes with each line connection, so automatic gain control (AGC) is used in the first stage of the data receiving device to keep the received signal level constant.
It is necessary to install a circuit. Recently, voice-band telephone line modems (modems) have tended to be constructed of digital LSIs, microprocessors, etc. due to advances in semiconductor technology, and digital signal processing technology has also begun to be applied to AGC circuits. However, compared to analog AGC circuits, digital AGC circuits provide stable operation without adjustment, but gain settings are discrete or step-like, so the received signal level can be determined using a single reference level. When the gain is determined and the gain is controlled based on the determination, the gain oscillates at the minimum step of the gain with respect to the reference level, generating noise. For this reason, digitized AGC circuits have had the disadvantage of lower performance than analog AGC circuits.

本発明は、このような従来の問題点に鑑みなさ
れたもので、利得の振動の生じない高性能のデイ
ジタル化されたAGC回路を提供する事を目的と
している。
The present invention has been devised in view of these conventional problems, and an object of the present invention is to provide a high-performance digitized AGC circuit in which gain oscillation does not occur.

本発明に係る自動利得制御回路は、入力アナロ
グ信号の振幅を変化させる利得可変回路の出力信
号をA/D変換回路によりデイジタル信号に変換
した後、その出力信号に含まれる直流成分を直流
除去フイルタで除去し、更にその出力信号の平均
レベルを少なくとも2つの基準レベルと比較して
判定し、この判定結果に基づいて、平均レベルが
少なくとも2つの基準レベルのうちの大きい方の
基準レベルより大きいときは利得を下げ、小さい
方の基準レベルより小さいときは利得を上げ、こ
れら2つの基準レベルの間にあるときは利得を一
定に保つように、利得可変回路の利得を制御する
ようにしたものである。
The automatic gain control circuit according to the present invention converts the output signal of a variable gain circuit that changes the amplitude of an input analog signal into a digital signal using an A/D conversion circuit, and then converts the DC component contained in the output signal into a digital signal using a DC removal filter. and further determine the average level of the output signal by comparing it with at least two reference levels, and based on the determination result, when the average level is greater than the larger of the at least two reference levels. The gain of the variable gain circuit is controlled so that the gain is lowered, the gain is increased when it is lower than the smaller reference level, and the gain is kept constant when it is between these two reference levels. be.

従つて、本発明によれば前記平均レベルが任意
の2つの基準レベルの間に収束した段階で利得が
一定となるので、利得の振動が生ずることはな
く、安定なAGC動作を達成することができる。
Therefore, according to the present invention, the gain becomes constant when the average level converges between two arbitrary reference levels, so that no gain fluctuation occurs and stable AGC operation can be achieved. can.

以下、図面を参照して本発明の一実施例を説明
する。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示したもので、入
力端子1には例えばデータ受信装置の受信信号の
ようなアナログ信号が入力される。この入力アナ
ログ信号は外部からの制御により利得が変化する
利得可変回路2で振幅制御された後、A/D変換
回路3でデイジタル信号に変換されてデイジタル
演算回路4に与えられる。すなわち、A/D変換
回路3の出力信号はデイジタルフイルタにより構
成された直流除去フイルタ5によつてA/D変換
回路3で生じた直流分を除去された後、AGC回
路の後段に配置された復調回路等のデイジタル信
号処理回路へ出力端子6を介して出力されるとと
もに、絶対値回路7とデイジタルフイルタにより
構成された低域通過フイルタ8とからなる平均レ
ベル検出手段により、その平均レベルが検出され
る。低域通過フイルタ8の出力は異なる基準レベ
ルl1,l2が与えられた2つのレベル比較回路91
2からなるレベル判定回路10でレベル判定さ
れ、その判定結果が利得制御手段である制御信号
発生回路11に与えられる。制御信号発生回路1
1は上記判定結果に基き、利得可変回路2の利得
をステツプ的に制御するための制御信号を発生す
る。
FIG. 1 shows an embodiment of the present invention, and an input terminal 1 receives an analog signal such as a received signal of a data receiving device. This input analog signal is subjected to amplitude control by a variable gain circuit 2 whose gain is changed by external control, and then converted to a digital signal by an A/D conversion circuit 3 and provided to a digital arithmetic circuit 4. That is, the output signal of the A/D conversion circuit 3 is removed from the DC component generated in the A/D conversion circuit 3 by the DC removal filter 5 constituted by a digital filter, and then the output signal is placed at the subsequent stage of the AGC circuit. The signal is output to a digital signal processing circuit such as a demodulation circuit via an output terminal 6, and the average level is detected by an average level detection means consisting of an absolute value circuit 7 and a low-pass filter 8 constituted by a digital filter. be done. The output of the low-pass filter 8 is passed through two level comparison circuits 9 1 , which are provided with different reference levels l 1 , l 2 .
The level is judged by a level judgment circuit 10 consisting of 92 , and the judgment result is given to a control signal generation circuit 11 which is a gain control means. Control signal generation circuit 1
1 generates a control signal for controlling the gain of the variable gain circuit 2 in a stepwise manner based on the above determination result.

このAGC回路の動作を第2図を用いて説明す
る。第2図aは基準レベルを1つしか持たない従
来のデイジタル化AGC回路の動作を示し、bは
2つの基準レベルl1,l2を有する本発明実施例の
AGC回路の動作を示している。
The operation of this AGC circuit will be explained using FIG. 2. FIG. 2a shows the operation of a conventional digitizing AGC circuit having only one reference level, and FIG. 2b shows the operation of a conventional digitizing AGC circuit having only one reference level, and FIG.
This shows the operation of the AGC circuit.

第2図aの場合、検出された平均レベル21は
時刻t0において基準レベルlより上にあるから、
利得可変回路の利得を下げる様な制御信号が出力
され、時刻t1で検出される平均レベルは時刻t0
のレベルよりも小さくなる。時刻t1での平均レベ
ルは基準レベルlよりもまだ上にあるため、さら
に時刻t2で平均レベルが下つて、基準レベルlよ
りも下のレベルとなる。したがつて、今度は利得
可変回路の利得を上げる制御信号が出力され、時
刻t3では、平均レベルが基準レベルより上のレベ
ルとなる。この様に基準レベルを1つしか持たな
い従来のデイジタル化AGC回路では、基準レベ
ルを中心として利得の最小制御ステツプで平均レ
ベルがステツプ的に振動する事になり、このレベ
ル変化がデイジタル化AGC回路で新たに発生し
た雑音となつて、出力される事になる。
In the case of FIG. 2a, since the detected average level 21 is above the reference level l at time t 0 ,
A control signal that lowers the gain of the variable gain circuit is output, and the average level detected at time t1 becomes smaller than the level at time t0 . Since the average level at time t 1 is still above the reference level l, the average level further decreases at time t 2 to become a level lower than the reference level l. Therefore, a control signal for increasing the gain of the variable gain circuit is output, and at time t3 , the average level becomes higher than the reference level. In the conventional digitized AGC circuit that has only one reference level, the average level oscillates stepwise at the minimum gain control step around the reference level, and this level change is reflected in the digitized AGC circuit. This will be output as newly generated noise.

これに対し、第1図のAGC回路の動作は、第
2図bに示すように平均レベル22は時刻t0、t1
では上の基準レベルl1と比較されて基準レベルl1
に近づき、時刻t2で基準レベルl1とl2との間に入
る。今、制御信号発生回路11による利得可変回
路2の利得制御を、平均レベル22が基準レベル
l1より上にあるとき利得を下げ、l2より下にある
とき利得を上げ、さらに、基準レベルl1とl2との
間にあるときは利得を変化させない様にすれば、
第2図bに示される如く、受信信号の平均信号レ
ベルは時刻t2以降、一定値となり、従来のデイジ
タル化AGC回路に見られるステツプ的な振動は
生じなくなる。
On the other hand, in the operation of the AGC circuit shown in FIG. 1, the average level 22 is set at times t 0 and t 1 as shown in FIG.
The reference level L 1 is compared with the reference level L 1 above.
approaches and enters between reference levels l 1 and l 2 at time t 2 . Now, the average level 22 is the reference level for the gain control of the variable gain circuit 2 by the control signal generation circuit 11.
If we reduce the gain when it is above l 1 , increase the gain when it is below l 2 , and keep the gain unchanged when it is between the reference levels l 1 and l 2 , we get
As shown in FIG. 2b, the average signal level of the received signal becomes a constant value after time t2 , and the step-like oscillations seen in the conventional digitized AGC circuit no longer occur.

本発明によれば、A/D変換後の出力信号に含
まれる直流成分を直流除去フイルタで除去した後
に、その平均レベルを検出してAGCを行なうの
で、A/D変換時における0レベルの誤差は上記
直流除去フイルタで全て除去され、最終的に正確
な0レベルを基準とした信号が得られる。しか
も、この発明によれば、A/D変換の際にデイジ
タル信号に発生する直流成分が直流除去フイルタ
により除去されるので、振幅値を反映した正確な
平均レベルの検出が可能であり、この結果、極め
て安定したAGCが可能になるという格別の効果
を奏する。
According to the present invention, after the DC component included in the output signal after A/D conversion is removed by the DC removal filter, the average level is detected and AGC is performed, so there is no error at the 0 level during A/D conversion. are all removed by the DC removal filter, and finally a signal based on an accurate 0 level is obtained. Moreover, according to the present invention, since the DC component generated in the digital signal during A/D conversion is removed by the DC removal filter, it is possible to accurately detect the average level that reflects the amplitude value. This has the extraordinary effect of making extremely stable AGC possible.

なお、第1図の実施例ではレベル判定回路を2
つのレベル比較回路で構成したが、必ずしも2つ
設置する必要はなく、複数の基準レベルと平均レ
ベルとの複数回の比較を1つのレベル比較回路で
時分割的に用いて行なつてよい。また、上記実施
例では基準レベルを2つとして説明したが、基準
レベルを更に増やすとともに、制御信号発生回路
による利得制御量(利得制御のステツプ幅)を、
レベル判定回路の判定結果に応じて、つまり平均
レベルが基準レベルで設定されたレベル領域のど
の位置にあるかに応じて異ならせることにより、
利得制御が安定する迄に要する時間を短縮化する
こともできる。
Note that in the embodiment shown in FIG.
Although the present invention is constructed with one level comparison circuit, it is not necessarily necessary to install two level comparison circuits, and multiple comparisons between a plurality of reference levels and an average level may be performed using one level comparison circuit in a time-sharing manner. In addition, although the above embodiment has been explained with two reference levels, the number of reference levels is further increased and the amount of gain control (step width of gain control) by the control signal generation circuit is increased.
By varying the average level according to the judgment result of the level judgment circuit, that is, depending on where the average level is in the level area set as the reference level,
It is also possible to shorten the time required until gain control becomes stable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例に係る利得制御回路
の回路図、第2図はその動作を説明するための波
形図である。 1……入力端子、2……利得可変回路、3……
A/D変換回路、4……デイジタル演算回路、5
……直流除去フイルタ、6……出力端子、7……
絶対値回路、8……低域通過フイルタ、91,92
……レベル比較回路、10……レベル判定回路、
11……制御信号発生回路。
FIG. 1 is a circuit diagram of a gain control circuit according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining its operation. 1...Input terminal, 2...Variable gain circuit, 3...
A/D conversion circuit, 4...Digital calculation circuit, 5
...DC removal filter, 6...Output terminal, 7...
Absolute value circuit, 8...Low pass filter, 9 1 , 9 2
... Level comparison circuit, 10 ... Level judgment circuit,
11...Control signal generation circuit.

Claims (1)

【特許請求の範囲】 1 利得が制御されることにより入力アナログ信
号の振幅を変化させる利得可変回路と、 この利得可変回路の出力信号をデイジタル信号
に変換するA/D変換回路と、 このA/D変換回路の出力信号に含まれる直流
成分を除去する直流除去フイルタと、 この直流除去フイルタの出力信号の平均レベル
を検出する平均レベル検出手段と、 この手段により検出された平均レベルを少なく
とも2つの基準レベルと比較して判定するレベル
判定手段と、 このレベル判定手段の判定結果に基づいて前記
利得可変回路の利得をステツプ的に制御する利得
制御手段とを備え、 前記利得制御手段は前記平均レベル検出手段に
より検出された平均レベルが前記少なくとも2つ
の基準レベルのうちの大きい方の基準レベルより
大きいときは前記利得を下げ、小さい方の基準レ
ベルより小さいときは前記利得を上げ、これら2
つの基準レベルの間にあるときは前記利得を一定
に保つことを特徴とする自動利得制御回路。 2 レベル判定手段は、平均レベル検出手段によ
り検出された平均レベルと少なくとも2つの基準
レベルとの比較を1つのレベル比較回路を時分割
的に用いて行なうものであることを特徴とする特
許請求の範囲第1項記載の自動利得制御回路。
[Claims] 1. A variable gain circuit that changes the amplitude of an input analog signal by controlling the gain; an A/D conversion circuit that converts the output signal of the variable gain circuit into a digital signal; a DC removal filter that removes a DC component included in the output signal of the D conversion circuit; an average level detection means that detects the average level of the output signal of the DC removal filter; and at least two Level determining means for determining the level by comparing it with a reference level; and gain controlling means for controlling the gain of the variable gain circuit in a stepwise manner based on the determination result of the level determining means, the gain controlling means determining the average level. When the average level detected by the detection means is larger than the larger one of the at least two reference levels, the gain is lowered, and when it is smaller than the smaller one of the at least two reference levels, the gain is increased;
An automatic gain control circuit characterized in that the gain is kept constant when the gain is between two reference levels. 2. The level determining means compares the average level detected by the average level detecting means with at least two reference levels using one level comparison circuit in a time-sharing manner. Automatic gain control circuit according to range 1.
JP17622681A 1981-11-02 1981-11-02 Automatic gain controlling circuit Granted JPS5877311A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17622681A JPS5877311A (en) 1981-11-02 1981-11-02 Automatic gain controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17622681A JPS5877311A (en) 1981-11-02 1981-11-02 Automatic gain controlling circuit

Publications (2)

Publication Number Publication Date
JPS5877311A JPS5877311A (en) 1983-05-10
JPH0156575B2 true JPH0156575B2 (en) 1989-11-30

Family

ID=16009828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17622681A Granted JPS5877311A (en) 1981-11-02 1981-11-02 Automatic gain controlling circuit

Country Status (1)

Country Link
JP (1) JPS5877311A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021054338A1 (en) 2019-09-17 2021-03-25 国立大学法人埼玉大学 Current interruption device and current interruption method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59224907A (en) * 1983-06-06 1984-12-17 Fujitsu Ltd Digital control type agc circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503759A (en) * 1973-05-15 1975-01-16

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503759A (en) * 1973-05-15 1975-01-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021054338A1 (en) 2019-09-17 2021-03-25 国立大学法人埼玉大学 Current interruption device and current interruption method

Also Published As

Publication number Publication date
JPS5877311A (en) 1983-05-10

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