JPH0151871B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electroluminescence (hereinafter referred to as
The present invention relates to a flat display device consisting of an EL (EL) element and a transistor for driving the light emission of the element.

Such displays are made by depositing fine particles onto a transparent glass substrate.
A large number of EL elements are arranged, and driving transistors are arranged in correspondence with each EL element, and when the driving transistors are turned on, the EL elements emit light to display figures, characters, etc. However, conventionally, binary compound semiconductors (CdSe,
Thin film transistors with a semiconductor layer made of a vapor-deposited film (CdS, etc.) are used as drive transistors, and a vapor deposition mask method is used to manufacture them.
The mask alignment accuracy is about 100 μm, the pattern width formed by the vapor deposition mask is about 30 μm, and the transistor element width is 230 μm or more, making it impossible to miniaturize the transistor.
When configuring a display device in combination with an EL element, there is a drawback that the pixel density cannot be increased to 1 line/mm or more.

In addition, thinning of the film causes compositional deviations, which deteriorates reliability and reproducibility. Binary compound semiconductors cannot be made into insulators through oxidation reactions, and they cannot be made into insulators by other elements such as SiO ₂ and AlO ₂ . Since the gate insulating film is obtained by forming the insulating film by sputter deposition, etc., the interface characteristics between the gate insulating film and the semiconductor layer deteriorate, resulting in a lack of reproducibility and uniformity, resulting in deviations in circuit characteristics. However, it has been difficult to realize flat displays with good characteristics.

The present invention aims to fundamentally eliminate these conventional drawbacks, and by combining a bidirectional high voltage polycrystalline Si thin film transistor and an EL element,
A planar display having high pixel density is realized and provided.

Hereinafter, details of the present invention will be explained with reference to figures showing examples.

FIG. 1 is a plan view showing the configuration of one pixel, where 1 is a thin film transistor as a signal switching element, 2 is a thin film transistor used for driving, 3 is a capacitor, 4 is an EL element, 5 is a scanning line, and 6 is a thin film transistor used as a signal switching element. 7 is a signal line, 7 is a power supply line, and 8 is a reference line as a common circuit, and the A-A' cross section and the B-B' cross section are as shown in FIGS. 2 and 3.

That is, in FIG. 2 showing the A-A' cross section,
9 is a transparent glass substrate, 10 is laser annealing,
A polycrystalline Si film made of polycrystalline Si whose grain size has been increased by electron beam annealing, thermal annealing, etc. and with offset gate regions formed on both sides; 11 is a gate insulating film; 12 is a gate made of polycrystalline Si; region, 13 is a source electrode or drain electrode, 14
1 is a gate electrode, 15 is a drain electrode or a source electrode, and these constitute the driving transistor 2.

In addition, 17 is a transparent electrode, 18 is an EL vapor deposition film in which a matrix such as ZnS is doped with Mn, etc., which becomes a luminescent center, and 1
9 is an insulating film, 20 is a power supply electrode, and these constitute the EL element 4.

On the other hand, in FIG. 3 showing the BB' cross section, 9
-15 are the same as those in FIG. 2, and these constitute the transistor 1 as a signal switching element, and 21 is the same as the transistor 1 and 2.
A polycrystalline Si film is formed as the electrode of the capacitor 3 formed in the same manner as the gate region 12, 22 is an insulating film, and 13 is an electrode for drawing out the capacitor 3.
is configured.

FIG. 4 is a cross-sectional view showing details of the transistors 1 and 2, in which 31 is an N-type (first conductivity type) channel region made of polycrystalline Si with increased grain size and having an appropriate resistivity value; 32 and 33 are impurity diffusion layers provided on each side of the channel region in which N-type impurities are diffused at a high concentration; 34 is an impurity diffusion layer formed on the surface of the channel region 31 by oxidizing polycrystalline Si with increased grain size A gate oxide film made of SiO ₂ formed; 35 an insulating film made of SiO ₂ formed on the surfaces of the gate region 12 and the gate oxide film 34;
36 and 37 are offset areas.

The rest of the structure is the same as in FIGS. 2 and 3, but the gate region 12 is formed in a predetermined central region of the gate oxide film 34, and is doped with P-type (second conductivity type) impurities at a high concentration. The electrodes 13 to 15 are made of diffused polycrystalline Si, and the electrodes 13 to 15 include impurity diffusion layers 32 and 33 as drain or source regions,
Alternatively, each gate region 12 may be electrically connected to the gate region 12.

Here, in the buried channel thin film transistor shown in FIG. 4, a P-type gate region 12 is formed with respect to an N-type channel region 31, so that when the gate electrode 14 is in a non-voltage state, the source-drain region is normal. Although it is off, if a predetermined voltage is applied to the gate electrode 14, the width of the depletion layer in the channel region 31 changes, and the current between the source and drain is controlled.

In addition, since offset regions 35 and 36 are provided between the source and the gate and between the gate and drain, the polycrystalline Si that forms the channel region 31 has a high breakdown voltage in both directions between the source and the drain. Since the grain size is increased by annealing, the carrier mobility in the channel region 31 increases. On the other hand, since the gate oxide film 34 is formed by oxidizing the polycrystalline Si, the channel region 31 and the gate oxide film 34 As a result, the interfacial properties between the two and the two sides become good, and as a result, it has a bidirectional offset structure and a high mutual conductance.

Regarding the manufacturing method and characteristics, please refer to the "Semiconductor device" (patent application filed in 1986-
215038), so the details are omitted.

Therefore, the transistor shown in FIG. 4 has high bidirectional withstand voltage and high mutual conductance, and can be manufactured using an ordinary device formation technology using a single crystal Si substrate.
If applied as No. 2, ideal characteristics can be obtained at the same time as miniaturization.

FIG. 5 shows an equivalent circuit according to the configuration of FIGS. 1 to 3, in which one electrode of the EL element 4 is connected to either the drain or the source of the transistor 2, and the other electrode of the EL element 4 is connected to one of the drain and source of the transistor 2. is power line 7
In addition, the reference line 8 is connected to either the drain or the source of the transistor 2, and is connected to the transistor 2 via the capacitor 3.
The signal line 6 is connected to the gate of the transistor 2 via the drain and source of the transistor 1, and the scanning line 5 is connected to the gate of the transistor 1.

Therefore, if a voltage that turns on transistor 1 is applied to scanning line 5, transistor 1 turns on, capacitor 3 is charged, and its terminal voltage becomes equal to the voltage on signal line 6, and transistor 2 also turns on. The EL element 4 is turned on, and the AC voltage of the power line 7 is applied to the EL element 4, causing the EL element 4 to emit light.

However, if the voltage of the scanning line 5 becomes below a predetermined value,
Even when transistor 1 is turned off, transistor 2 remains on due to the charge in capacitor 3,
EL until the voltage is applied to the scanning line 5 again.
The element 4 is brought into a light emitting state.

Note that the charge in the capacitor 3 is discharged via a resistance component in parallel with this, but since the discharge time constant is determined according to the period of voltage application to the scanning line 5, the EL element 4 is discharged during the period of voltage application. luminescence is maintained.

FIG. 6 shows an example of the applied voltage-luminance characteristics of the EL element 4 in which the ZnS vapor-deposited film is doped with Mn.
The brightness is 10 cd/m ² at an applied voltage of 70 Vrms.

FIG. 7 shows an example of the relationship between the applied voltage waveform A and the light emission waveform B of the EL element 4. In order to achieve high-intensity light emission, an applied voltage of about 70 Vrms is required, and a change of about 100 V in the positive and negative directions is required. According to the configuration shown in FIG. 4, this condition can be fully satisfied.

FIG. 8 shows an example of the relationship between the offset gate length and breakdown voltage in the configuration shown in FIG.
The breakdown voltage increases rapidly from an offset gate length of about 10 μm.

Note that the dotted line indicates the offset region as a normal single crystal.
This is a case where the structure is made of Si, and in order to obtain a withstand voltage of 100V or more, it is necessary to make the offset gate length 15μm or more. For example, a sufficient breakdown voltage can be obtained with a short offset gate length, making it easy to miniaturize the transistors 1 and 2.

FIG. 9 is an example showing the device breakdown voltage with respect to the offset gate length when changing the laser power Po during laser annealing when obtaining the configuration shown in FIG. This shows that the device breakdown voltage is about 100%, and the deviation of the device breakdown voltage is small with respect to changes in the laser power Po.

Figure 10 shows the transistor characteristics when the offset gate length is 5 μm in Figure 4,
Element breakdown voltage 100V or more, mutual conductance 25μS,
The threshold voltage is 7V, which is sufficient for driving the EL element 4.

11A is the power supply voltage waveform of the power supply line 7 in FIG. 5, and FIG. 11B is the EL element 4 in FIG. 5.
By using the terminal voltage waveform of FIG. 4 as transistor 2, when it is off, it becomes the waveform of C, and when it is on, it becomes the waveform of D,
In waveform D, the EL element 4 emits light, and in waveform C, the EL element 4 dims, and the EL
It has been shown that the element 4 can be sufficiently driven by the configuration shown in FIG.

In addition, for the one in Figure 4, the channel length is 3 to 5μ.
If m, the element width is about 20 μm, and element formation technology using a normal single-crystal Si substrate can be applied, so if transistors 1 and 2 and capacitor 3 are manufactured in the same process, photolithography technology etc. By applying this, the pixel density can be increased to 4 lines/mm or more, which is more than 4 times that of the conventional method.

However, the transistor 1 only needs to be turned on and off according to the voltage of the scanning line 5, and various switching elements other than the one shown in FIG. 4 can be used, and the transistor 1 shown in FIGS. The arrangement shown in FIG. 5 may be any arrangement that allows the circuit shown in FIG. 5 to be constructed, and can be freely modified according to the conditions.

As is clear from the above description, according to the present invention, a display device with high pixel density is realized, and the reproducibility, uniformity, reliability, etc. of electrical characteristics are significantly improved, and the display surface becomes multicolored. It becomes easy to add optical input functions, etc., and a remarkable effect can be obtained as a flat display device for various uses.

[Brief explanation of drawings]

The figures show an embodiment of the present invention; FIG. 1 is a plan view of one pixel, FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1, and FIG. 3 is a cross-sectional view taken along line B-B' in FIG. , FIG. 4 is a cross-sectional view showing the details of the transistor, FIG. 5 is a diagram showing the equivalent circuit of FIGS. 1 to 3, FIG. 6 is a diagram showing an example of applied voltage-luminance characteristics of an EL element, The figure shows an example of the relationship between the applied voltage waveform and the emission waveform of the EL element, Figure 8 shows an example of the relationship between the offset gate length and breakdown voltage, and Figure 9 shows the relationship between the offset gate length and the breakdown voltage. Figure 10 is a diagram showing the transistor characteristics when the offset gate length is 5 μm, and Figure 11 is a diagram showing the power supply voltage waveform and the terminal voltage waveform of the EL element. It is. 1...transistor (switching element), 2
...Transistor, 3...Capacitor, 4...EL (electroluminescence) element, 5...Scanning line, 6
...Signal line, 7...Power line, 8...Reference line, 9...
... Substrate, 12 ... Gate region, 17 ... Transparent electrode, 18 ... EL vapor deposition film, 31 ... Channel region,
32, 33... Impurity diffusion layer, 34... Gate oxide film, 35... Insulating film, 36, 37... Offset region.

Claims (1)

[Claims] 1. A channel region of a first conductivity type made of polycrystalline Si with increased grain size provided on an insulating substrate, and the first channel region provided on each side of the channel region.
first and second impurity diffusion layers of conductivity type; a gate region made of polycrystalline Si in which impurities of second conductivity are diffused and provided in a predetermined portion on the channel region via a gate oxide film; A transistor having an offset region provided between the gate region and the first and second impurity diffusion layers, and connected to one of the first and second impurity diffusion layers. a power supply line connected to one electrode of the electroluminescent element, the other electrode of the electroluminescent element, and the other of the first and second impurity diffusion layers and having a capacitance. a reference line connected to the gate region through the gate electrode; a signal line connected to the gate region through a signal switching element having a gate electrode; and a scanning line connected to the gate electrode of the switching element. A display device characterized by comprising: