JP2002076356A - Semiconductor device - Google Patents

Semiconductor device

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JP2002076356A
JP2002076356A JP2000264885A JP2000264885A JP2002076356A JP 2002076356 A JP2002076356 A JP 2002076356A JP 2000264885 A JP2000264885 A JP 2000264885A JP 2000264885 A JP2000264885 A JP 2000264885A JP 2002076356 A JP2002076356 A JP 2002076356A
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transparent
element
semiconductor
doped
group
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JP4089858B2 (en )
Inventor
Masashi Kawasaki
Hideomi Koinuma
Hideo Ono
英男 大野
雅司 川崎
秀臣 鯉沼
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Japan Science & Technology Corp
科学技術振興事業団
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure

Abstract

PROBLEM TO BE SOLVED: To provide a transparent transistor using a transparent channel layer of zinc oxide doped with a 3d transition metal element, etc., free from the need of heat treatment. SOLUTION: A channel layer 11 is formed of a transparent semiconductor, e.g. zinc oxide ZnO doped with a 3d transition metal element, etc. A source 12, a drain 13 or a gate 14 entirely or partly uses a transparent electrode which uses e.g. a transparent conductive material such as conductive ZnO doped with a III element, etc. A gate insulation layer 15 uses e.g. a transparent insulative material such as insulative ZnO doped with an element capable of taking a monovalence or a V element or 3d transition metal element. A substrate 16 may use a material comparatively easily affected by heat treatment e.g. plastics, polyethylene, polymer films, etc.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、半導体デバイスに係り、特に、透明トランジスタと、透明トランジスタを積層した半導体デバイス、及び、透明トランジスタを発光素子の駆動用又はメモリの読み書き用等に応用した半導体デバイスに関する。 BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, particularly, a transparent transistor, the semiconductor device obtained by laminating a transparent transistor, and a semiconductor which is applied a transparent transistor or the like for reading and writing of the drive or memory of the light emitting element about the device. なお、本発明において、説明の簡略上、「透明」という概念には、「透明又は透光性を有する」という概念が含まれるものとする。 In the present invention, for simplicity of explanation, the concept of "transparent" is intended to include the concept of "transparent or having light-transmitting property".

【0002】 [0002]

【従来の技術】基板上への高性能薄膜トランジスタは、 High-performance thin film transistor to the Background of the Invention on the substrate,
液晶表示デバイスへの応用を筆頭に、面発光レーザ、エレクトロルミネセンス素子等の発光素子の駆動素子、メモリ等のように、光デバイス分野での多種多様な応用に用いることができる。 Led by application to the liquid crystal display device, a surface emitting laser, the driving element of the light emitting element such as an electroluminescent element, as a memory or the like, can be used in a wide variety of applications in optical devices field.

【0003】また、一般に、液晶表示デバイスの駆動用等のトランジスタとしては、アモルファスシリコンや多結晶シリコン等を用いた薄膜トランジスタが用いられている。 [0003] Generally, as the transistors, such as for driving the liquid crystal display device, a thin film transistor using amorphous silicon or polycrystalline silicon or the like is used. これらの材料は、可視光領域に光感度を有しているので、光によりキャリアが生成されて抵抗が低下する。 Since these materials have a photosensitivity in the visible light region, carriers are generated resistance decreases by light. そのため、光が照射されると、トランジスタが、オフ状態に制御されているはずなのに、オン状態となってしまう場合がある。 Therefore, when light is irradiated, the transistor, but it should be controlled to the OFF state, in some cases turned on. そこで、トランジスタをオフ状態に持続するために、従来では、金属被膜等の光の遮断層を用いて、光によるキャリア抵抗の低下を防止している。 Therefore, in order to sustain the transistor in an off state, conventionally, with a blocking layer of the light, such as a metal film, thereby preventing a decrease in carrier resistance by light.

【0004】一般に、液晶表示デバイスは、ノード型パソコン等に多く使用されており、省エネルギー化、高輝度化及び小型化が求められている。 In general, liquid crystal display devices are widely used in the node-type personal computer, etc., energy saving, high brightness and miniaturization is required. そのためには、単位画素に占める有効な表示部面積の割合を向上させることが有効である。 For this purpose, it is effective to increase the proportion of the effective display portion area occupying the unit pixel. しかしながら、上述のように、駆動用等のトランジスタでは、金属薄膜等の光の遮断層が形成されるため、画素の面積割合(開口率)が減少する。 However, as described above, in a transistor, such as driving, since the blocking layer of the light, such as a metal thin film is formed, the ratio area of ​​the pixel (aperture ratio) is reduced. よって、輝度の明るい表示素子の開発には、トランジスタの高性能化によるトランジスタ面積の縮小、又は、バックライトの高輝度化が必要であった。 Therefore, the development of a bright display device luminance is reduced transistor area by the performance of the transistor, or was required high luminance of the backlight. しかしながら、トランジスタの高性能化による対策では、歩留まりの限界があり、コストが上昇することになる。 However, the measures according to the performance of the transistor, there is a limit of yield, so that the cost is increased. また、バックライトを明るくすることによる対策では、エネルギー消費量が多くなってしまう。 In addition, the measures taken by it to brighten the backlight, energy consumption becomes many.

【0005】本発明者等は、これまで、酸化亜鉛(Zn [0005] The present inventors have found that, up to now, zinc oxide (Zn
O)を半導体として用いたトランジスタに関する研究を行い、ガラス基板上に透明な薄膜トランジスタが形成可能であることを明かにしてきた。 The O) engaged in the study of a transistor using a semiconductor has been revealed that the transparent thin film transistor on a glass substrate can be formed. 酸化亜鉛をチャネルとして用いる透明薄膜トランジスタについて、特許出願中である(特願平10−326889号、特願平11−0 For transparent thin film transistor using zinc oxide as a channel, a patent pending (Japanese Patent Application No. 10-326889, Japanese Patent Application No. 11-0
82043号参照)。 See No. 82043).

【0006】また、本発明者等はこれまでに、ガラス基板上に透明酸化亜鉛電界効果トランジスタ(ZnO−T Further, the present inventors have so far transparent zinc oxide field effect transistor on a glass substrate (ZnO-T
FT)を作製し、ON/OFF比4.5×10 、しきい値電力1.3V、電界効果移動度150cm /V To prepare a FT), ON / OFF ratio 4.5 × 10 5, the threshold power 1.3V, field-effect mobility 150 cm 2 / V 3
の特性が得られたことを報告した(七種ら、2000. Properties were reported that were obtained (seven species, et al., 2000.
3 応用物理学会予稿集、29P―YL−16、参照)。 3 Japan Society of Applied Physics Proceedings, 29P-YL-16, see).

【0007】このように、従来困難であった酸化亜鉛の配向制御や価電子制御が現在可能となったため、本発明者らの既出願では、酸化亜鉛等の透明チャネル層を用いた一部又は全部が透明なトランジスタを提供した。 [0007] Thus, since the alignment control and the valence control of conventionally difficult a zinc oxide became possible now, in the foregoing prior application of the present inventors, some using a transparent channel layer, such as zinc oxide, or all have provided a transparent transistor. すなわち、チャネル層(導電層)に透明な酸化亜鉛等の材料を用いることにより、可視光領域に光感度を有しないようにし、遮光層を形成する必要を無くし、液晶表示デバイス等の表示部の面積割合を向上させるようにしたトランジスタを提供した。 That is, by using a material such as transparent zinc oxide channel layer (conductive layer), so has no photosensitivity in the visible light region, eliminating the need to form a light shielding layer, the display portion of the liquid crystal display device or the like It provided the transistor so as to improve the area ratio.

【0008】 [0008]

【発明が解決しようとする課題】一般に、薄膜トランジスタでは、移動度もさることながら、on/off比(ゲートの電圧でドレイン電流のスイッチを行う際のo Generally [0005] In the thin film transistor, even more than mobility, o when performing switching of the drain current on / off ratio (the gate voltage
n状態の電流とoff状態のリーク電流との比)がデバイスを活用する上で重要な要因となる。 The ratio of the leakage current of the current and the off state of n states) is an important factor in utilizing the device. しかし、十分なon−off比をかせぐためには、通常ではn型の電気伝導性を示すZnOを半絶縁化する必要があった。 However, in order to earn a sufficient on-off ratio is in the normal had to be semi-insulating the ZnO exhibiting n-type conductivity. そのため、従来では、ZnOへのLiのドープが試みられてきた。 Therefore, in the conventional, doped of Li to ZnO it has been attempted. この場合も、所望のon−off比(例えば、1 Again, the desired on-off ratio (e.g., 1
以上)及び易動度(移動度)(例えば、100cm 0 5 or higher) and mobility (mobility) (e.g., 100 cm
/Vs以上)という性能を発揮するには、高温(例えば、500℃程度)のアニ−ル処理が必要であった。 To demonstrate the performance of 2 / Vs or more), high temperature (e.g., annealing of about 500 ° C.) - was necessary Le process. そして、アニ−ル処理に耐えるための基板材料等の各材料を選択する必要があった。 Then, annealing - it is necessary to select the materials such as the substrate material to withstand Le process.

【0009】また、従来、米国特許第5744864号のように、電流を流れやすくするためにチャンネル層に不純物を混入して縮退半導体とする試みがある。 Further, conventionally, as in US Patent No. 5,744,864, there is an attempt to degenerate semiconductor by doping impurity in the channel layer in order to facilitate current flow. しかしながら、この場合、off状態でのリーク電流を低く抑えることはむずかしかった。 However, in this case, it was difficult to suppress the leakage current in the off state low.

【0010】本発明は、以上の点に鑑み、ZnO等の透明なチャネル材料にNi等の3d遷移金属元素を添加することにより高低抗化することで、比較的低温(例えば、室温等)における薄膜形成によっても、所望のon [0010] The present invention has been made in view of the above points, by high and low Koka by adding 3d transition metal element such as Ni transparent channel material such as ZnO, in a relatively low temperature (e.g., room temperature, etc.) by thin film formation, it desired on
−off比及び移動度を得て、従来の性能を凌駕する非常に高性能の薄膜トランジスタを形成することを目的とする。 -off ratio and to obtain the mobility, an object of very forming a high performance thin film transistors over conventional performance. また、本発明は、プラスチック基板、高分子材料基板等、従来熱処理に耐えられない材料を用いて、透明電子回路を形成することを目的とする。 Further, the present invention is a plastic substrate, a polymer material substrate or the like, with intolerable material prior heat treatment, intended to form a transparent electronic circuit. また、本発明は、半導体の性能とプロセスの許容度を著しく向上させることを目的とする。 Further, the present invention is intended to significantly improve the acceptability of the semiconductor performance and process.

【0011】また、本発明は、透明トランジスタを、面発光レーザやエレクトロルミネセンス素子等の発光素子の駆動用、メモリ用等のように光デバイス分野での多様な応用に用いることを目的とする。 Further, the present invention is a transparent transistor, and an object thereof is used for driving the light emitting element such as surface emitting lasers and electroluminescent devices, in a variety of applications in optical devices field as such for memory . さらに、本発明は、 In addition, the present invention is,
透明な電子素子として、各種の幅広い応用に用いた半導体デバイスを提供することを目的とする。 As a transparent electronic device, and an object thereof is to provide a semiconductor device using a variety of wide applications.

【0012】 [0012]

【課題を解決するための手段】本発明の第1の解決手段によると、酸化亜鉛ZnO、酸化カドミウムCdO、Z According to the first solving means of the present invention SUMMARY OF THE INVENTION, zinc oxide ZnO, cadmium oxide CdO, Z
nOにIIB元素若しくはIIA元素若しくはVIB元素を加えた化合物又は混合物の内いずれかを用い、3d Using any of the compounds or mixtures were added IIB element or IIA element or VIB element nO, 3d
遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物をドープした透明チャネル層と、III族元素若しくはVII族元素若しくはI族元素若しくはV族元素のいずれかをドープした若しくはドープしない導電性ZnO等の透明導電性材料、In 若しくはSnO 若しくは(In−Sn)O などの透明導電体、又は、透明でない電極材料を、その全部又は一部に用いた、ソース及びドレイン及びゲートと、前記透明チャンネル層が形成されるための絶縁性基板を備えた半導体デバイスを提供する。 A transparent channel layer impurity-doped to the high resistance without loss of transparency of the transition metal element or rare earth or transparent semiconductor, doped with one of group III elements or Group VII element or Group I elements or Group V elements or doped not transparent conductive material of the conductive ZnO or the like, an in 2 O 3 or SnO 2 or (in-Sn) transparent conductor such as O x, or a non-transparent electrode material, was used in whole or in part provides a semiconductor device comprising an insulating substrate for the source and drain and a gate, wherein the transparent channel layer is formed.

【0013】前記半導体デバイスは、さらに、前記半導体デバイスの前記ドレイン若しくはソースと連続した領域、又は、前記ドレイン若しくはソースと接続された他の半導体の領域と、前記領域に接合された半導体層とにより形成される発光部を備えてもよい。 [0013] The semiconductor device further said drain or source a continuous region of the semiconductor device, or, the other semiconductor region connected to the drain or source, by a semiconductor layer joined to said region emitting portion formed may be provided. 前記半導体デバイスは、さらに、前記半導体デバイスの前記ドレイン若しくはソースと連続した領域、又は、前記ドレイン若しくはソースと接続された他の半導体若しくは導体の領域と、前記領域上の前記ゲート絶縁層若しくは他の絶縁層と、前記ゲート絶縁層若しくは前記他の絶縁層上の半導体層又は導体層とにより形成されるコンデンサを備えてもよい。 The semiconductor device further wherein said drain or source and contiguous regions of a semiconductor device, or, the other semiconductor or conductor region connected to the drain or source, on the area of ​​the gate insulating layer or other an insulating layer may comprise a capacitor formed by a semiconductor layer or conductor layer on the gate insulating layer or said another insulating layer.

【0014】本発明の第2の解決手段によると、III族元素若しくはVII族元素をドープし、さらに3d遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物をドープしたZnO等の透明n形半導体により形成されたエミッタ並びにコレクタ、又は、 [0014] According to a second aspect of the present invention, doped with impurities doped with a Group III element or Group VII element, to the high-resistance without further loss of transparency of the 3d transition metal element or rare earth or transparent semiconductor It was formed by a transparent n-type semiconductor emitter and collector, such as ZnO, or,
ベースと、I族元素若しくはV族元素をドープし、さらに3d遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物をドープしたZnO等の透明p形半導体により形成されたベース、又は、エミッタ並びにコレクタと、III族元素若しくはVII族元素若しくはI族元素のいずれかをドープした若しくはドープしない導電性ZnO等の透明導電性材料、In 若しくはSnO 若しくは(In−Sn)O などの透明導電体、又は、透明でない電極材料を、その全部又は一部に用い、前記ベース、エミッタ及びコレクタにそれぞれ形成された、ベース電極及びエミッタ電極及びコレクタ電極を備えた半導体デバイスを提供する。 Base and doped with a Group I element or group V element, is formed by further 3d transition metal element or a transparent p-type semiconductor such as ZnO which impurity-doped to the high resistance without loss of transparency of the rare earth or transparent semiconductor base, or an emitter and collector and, III group element or group VII element or the transparent conductive material of the conductive ZnO or the like, not the doped or doped with either group I element, an in 2 O 3 or SnO 2 or (in -sn) O x transparent conductor such as, or a non-transparent electrode material, its use in whole or in part, the base, respectively formed on the emitter and collector, with a base electrode and an emitter electrode and a collector electrode to provide a semiconductor device.

【0015】前記半導体デバイスは、さらに、前記半導体デバイスの前記コレクタ若しくはエミッタと連続した領域、又は、前記コレクタ若しくはエミッタと接続された他の半導体の領域と、前記領域に接合された半導体層とにより形成される発光部を備えてもよい。 [0015] The semiconductor device further said collector or emitter and continuous regions of the semiconductor device, or, the other semiconductor region connected to the collector or emitter, the semiconductor layer which is joined to the region emitting portion formed may be provided. 前記半導体デバイスは、さらに、前記半導体デバイスの前記コレクタ若しくはエミッタと連続した領域、又は、前記コレクタ若しくはエミッタと接続された他の半導体若しくは導体の領域と、前記領域上の絶縁層と、前記絶縁層上の半導体層又は導体層とにより形成されるコンデンサを備えてもよい。 The semiconductor device further wherein said collector or emitter and contiguous regions of a semiconductor device, or, the other semiconductor or conductor areas connected to the collector or emitter, an insulating layer on the region, said insulating layer it may comprise a capacitor formed by a semiconductor layer or conductor layer above.

【0016】さらに、上述のような半導体デバイスを複数備え、複数の前記トランジスタ間の配線の全部又は一部に、III族元素若しくはVII族元素若しくはI族元素若しくはV族元素のいずれかをドープした若しくはドープしない導電性ZnO等の透明導電性材料、In 若しくはSnO 若しくは(In−Sn)O などの透明導電体、又は、透明でない電極材料を用いてもよい。 Furthermore, a plurality of semiconductor devices as described above, all or part of the wiring between the plurality of transistors, doped with one of group III elements or Group VII element or Group I elements or Group V elements or a transparent conductive material such as doped non conductive ZnO, transparent conductor such as in 2 O 3 or SnO 2 or (in-Sn) O x, or may be used not transparent electrode material.

【0017】前記半導体デバイスは、さらに、III族元素若しくはVII族元素若しくはI族元素若しくはV族元素のいずれかをドープした若しくはドープしない導電性ZnO等の透明導電性材料、In 若しくはSnO [0017] The semiconductor device further, III group element or Group VII element or Group I element or a transparent conductive material such as conductive ZnO which is not the doped or doped with either V group element, an In 2 O 3 or SnO
若しくは(In−Sn)O などの透明導電体により形成されるインダクタを備えるようにしてもよい。 2 or (In-Sn) may be provided with an inductor which is formed of a transparent conductor such as O x.

【0018】半導体デバイスを複数マトリクス状に配列し、各トランジスタによりコンデンサ又は発光部が駆動されるようにしてもよい。 [0018] arranging the semiconductor device into a plurality matrix, capacitor or the light emitting portion may be driven by the transistor. さらに、本発明は、透明トランジスタを積層とした半導体デバイス、発光素子及びメモリ等へ応用した半導体デバイスを提供する。 Furthermore, the present invention relates to a semiconductor device in which a laminated transparent transistor, a semiconductor device is provided, which is applied to the light emitting element and a memory or the like.

【0019】 [0019]

【発明の実施の形態】(1)電解効果トランジスタ(Fi DETAILED DESCRIPTION OF THE INVENTION (1) field effect transistor (Fi
eld Effect Transistor、FET) 図1に、本発明に係るトランジスタの第1の実施の形態の断面図を示す。 eld Effect Transistor, FET) in Figure 1 shows a cross-sectional view of a first embodiment of a transistor according to the present invention. 図1(A)に示されるように、第1の実施の形態のトランジスタは、FETに関するものであり、チャネル層11、ソース12、ドレイン13、ゲート14、ゲート絶縁層15、基板16を備える。 As shown in FIG. 1 (A), the transistor of the first embodiment includes relates FET, the channel layer 11, source 12, drain 13, gate 14, gate insulating layer 15, the substrate 16. 基板1 Substrate 1
6の上には、ゲート14、ゲート絶縁層15を介してチャネル層11が形成される。 On the 6, the gate 14, the channel layer 11 through the gate insulating layer 15 is formed. チャネル層11には、ゲート絶縁層15、ソース12及びドレイン13が形成される。 The channel layer 11, the gate insulating layer 15, the source 12 and drain 13 are formed.

【0020】図1(B)には、第1の実施の形態の変形例が示される。 [0020] FIG. 1 (B), a modification of the first embodiment is shown. このトランジスタは、基板16の上に、 This transistor on the substrate 16,
ゲート14、ゲート絶縁層15が形成される。 Gate 14, the gate insulating layer 15 is formed. さらに、 further,
チャネル層11には、上側に、ソース12及びドレイン13がオーミック接合により、下側に、ゲート14がショットキー接合により、それぞれ形成される。 The channel layer 11 to the upper, by the source 12 and drain 13 ohmic junction, the lower, the gate 14 by Schottky junction, is formed, respectively. この例では、図1(A)と比べてチャネル層とゲート14の間にゲート絶縁層15がない。 In this example, there is no gate insulating layer 15 between the channel layer and the gate 14 than Fig. 1 (A).

【0021】以下に各構成要素の材料について説明する。 [0021] For the material of each component will be described below. 第1に、チャネル層11は、透明な半導体で形成される。 First, the channel layer 11 is formed of a transparent semiconductor. 透明なチャネル層の材料としては、例えば、酸化亜鉛ZnO、酸化カドミウムCdO、ZnOに格子定数やバンドギャップなどを調整するためにIIB元素(C The transparent channel layer, for example, zinc oxide ZnO, cadmium oxide CdO, IIB element for adjusting the lattice constant and the band gap ZnO (C
d、Hg)若しくはIIA元素(Be、Mg、Ca、S d, Hg) or IIA elements (Be, Mg, Ca, S
r、Ba、Ra)若しくはVIB元素(S、Se、T r, Ba, Ra) or VIB elements (S, Se, T
e、Po)を加えた化合物又は混合物等の内いずれかを用い、3d遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物をドープしたものである。 e, using any of such compounds or mixtures were added Po), the impurities in the high-resistance without losing the transparency of the 3d transition metal element or rare earth or transparent semiconductor is obtained by doping. IIB元素を加えたものとしては、例えば、酸化カドミウム亜鉛Cd Zn 1−x O、IIA元素を加えたものとしては、例えば、酸化マグネシウム亜鉛Mg The plus IIB elements, for example, as a plus cadmium oxide, zinc Cd x Zn 1-x O, the IIA element, e.g., magnesium zinc oxide Mg
Zn 1−x O等が挙げられる。 x Zn 1-x O, and the like. 3d遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物をドープすることによりチャネル層の抵抗率を上昇させることができる。 It can raise the resistivity of the channel layer by doping an impurity to a high-resistance without losing the transparency of the 3d transition metal element or rare earth or transparent semiconductor. 3d遷移金属元素としては、 The 3d transition metal element,
例えば、Sc、Ti、V、Cr、Mn、Fe、Co、N For example, Sc, Ti, V, Cr, Mn, Fe, Co, N
i、Cuがある。 i, there is Cu. 一例としては、Ni、Mn、コバルト、鉄等を適宜の量で(例えば、Niを2%程度等)、 As an example, Ni, Mn, cobalt, etc. in an appropriate amount of iron (e.g., a Ni about 2%, etc.),
ドープすることができる。 It can be doped.

【0022】チャネル層11は、複数種類の3d遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物が、各々予め定められた割合又はドープ量でドープするようにしてもよい。 The channel layer 11, impurities in the high-resistance without losing the transparency of the plurality of types of 3d transition metal elements or rare earth or transparent semiconductor, so as to dope in a ratio or amount of doping was determined each previously it may be. 例えば、NiとMnを適宜の量ドープすることができる。 For example, it can be appropriate amount doped Ni and Mn. また、チャネル層11は、3d遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物のドープ量を均一な分布としなくてもよい。 The channel layer 11 may not set the doping amount of impurities into high-resistance without losing the transparency of the 3d transition metal element or rare earth or transparent semiconductor and uniform distribution. その際、基板16に対して平行にグラデーションをかけても、垂直又は両方向にグラデーションをかけてもよい。 At that time, even over parallel to the gradient with respect to the substrate 16 may be subjected to gradation vertical or both directions. さらに、ドープ濃度を一様に増加又は減少させるグラデーションの他に、適宜増域したり又は増減を繰り返したり、離散的又は段階的に濃度を調節したり、複数の異なる濃度の層状態としたり、適宜の均一でない濃度分布とすることができる。 Furthermore, in addition to the gradient of increasing or decreasing the doping concentration uniformly, or repeated as appropriate increase range or or decrease, or modulate discrete or stepwise density, or a layer state of a plurality of different concentrations, it can be a concentration distribution not uniform appropriate.

【0023】図2に、3d遷移金属元素のドープ量と抵抗値の関係についての説明図を示す。 [0023] FIG. 2 is an explanatory view of the relationship doping amount and the resistance value of the 3d transition metal element. なお、黒ぬりつぶしのプロットはドーピング元素が完全に(略完全)に溶けていることを示し、黒ぬりつぶし出ないプロットはドーピング元素が完全に溶けていないことを示す。 Note that the plot of the black filling indicates that the doping element is dissolved in the complete (almost completely), the plot does not appear black filling show that doping elements are not melted completely. これは、熱処理をしない場合のデータである。 This is the data of If you do not want to heat treatment. ドープしないZnOの抵抗に比べ、3d遷移金属元素をドープしたZ Than the resistance of ZnO which is not doped, doped with 3d transition metal element Z
nOは、熱処理をしなくてもいずれも十分な高抵抗を示すことができる。 nO can either without heat treatment shows a sufficiently high resistance. 例えば、Mn、Sc、Cr等は、低い添加濃度でも、抵抗値を比較的高くすることができる。 For example, Mn, Sc, Cr, etc., even at low additive concentrations, can be a resistance relatively high.

【0024】第2に、ソース12、ドレイン13又はゲート14は、各々の内、全部又は一部に透明電極が用いられる。 [0024] Second, source 12, drain 13 or gate 14, within each, a transparent electrode used in whole or in part. 透明電極としては、例えば、III族元素(B、 As the transparent electrode, for example, III group elements (B,
Al、Ga、In、Tl)、VII族元素(F、Cl、B Al, Ga, In, Tl), VII group elements (F, Cl, B
r、I)、I族元素(Li、Na、K、Rb、Cs)、 r, I), I group elements (Li, Na, K, Rb, Cs),
V族元素(N、P、As、Sb、Bi)のいずれかをドープした導電性ZnO、又は各種元素をドープしない導電性ZnO等の透明導電性材料が用いられる。 V group elements (N, P, As, Sb, Bi) or a doped conductive ZnO, or the various elements transparent conductive material such as conductive ZnO which is not doped is used. ここで、 here,
これらの元素をドープする場合、ドープ量は適宜設定することができる(例えば、高濃度にn形をドープしたn In doping these elements, the doping amount can be appropriately set (for example, doped with an n-type at a high concentration n
++ −ZnO等を用いることができるが、これに限定されない)。 ++ -ZnO or the like can be used, but not limited to). さらに、ソース12、ドレイン13又はゲート14としては、その他に、In 、SnO Furthermore, the source 12, the drain 13 and the gate 14, the other, In 2 O 3, SnO 2 ,
(In−Sn)O などの透明導電体を用いることができる。 It can be used transparent conductor, such as (In-Sn) O x. また、透明な材料以外にも、Al、Cu等の金属や、高ドープした半導体ポリシリコン等の透明でない電極材料を用いても良い。 In addition to transparent material, Al, metal, such as Cu, may be used not transparent electrode material such as a semiconductor polysilicon highly doped. さらに、一部透明な材料を採用し、一部透明でない材料を採用することもできる。 In addition, the use of a partially transparent material, may be employed not part transparent material.

【0025】第3に、ゲート絶縁層15としては、例えば、1価の価数を取りうる元素又はV族元素又は、3d [0025] Thirdly, the gate as the insulating layer 15, for example, monovalent valence elements or group V element, or may take, 3d
遷移金属元素をドープした絶縁性ZnO、SiN、Si Insulating ZnO doped with transition metal elements, SiN, Si
等の透明絶縁性材料が用いられる。 Transparent insulating materials such as O 2 is used. 1価の価数を取りうる元素としては、例えば、I族元素(Li、Na、 As the element can take the number of monovalent valence, e.g., I group elements (Li, Na,
K、Rb、Cs)、Cu、Ag、Au等がある。 K, Rb, Cs), Cu, Ag, there is Au. V族元素としては、N、P、As、Sb、Bi等がある。 The group V element, there N, P, As, Sb, Bi and the like. ゲート絶縁層15としては、その他にも、Al 、Mg The gate insulating layer 15, Besides, Al 2 O 3, Mg
O、CeO 、ScAlMgO 、SiO 、等の透明絶縁性酸化物を用いることができる。 O, it can be used CeO 2, ScAlMgO 4, SiO 2 , a transparent insulating oxide and the like. さらに、ポリマーフィルム、ビニール、プラスティック等の透明な絶縁体を用いても良い。 Further, polymer films, vinyl, may be used a transparent insulator plastic or the like. なお、ゲート絶縁層15は、チャネル層11の材料と格子マッチングの良い高絶縁性の材料が好ましい。 Note that the gate insulating layer 15 is highly insulating material with good material and lattice matching of the channel layer 11 is preferred. 酸化亜鉛をチャネル層とした場合、例えば、 If the zinc oxide as a channel layer, for example,
ScAlMgO 等が用いられる。 ScAlMgO 4 or the like is used. これらは、全ての面内の格子定数が1%以内で一致しており、相互にエピタキシャル成長が可能である。 These lattice constant in all aspects is matched to within 1%, it is possible to each other epitaxial growth. また、ゲート絶縁層15 Further, the gate insulating layer 15
に、強誘電性の材料を用いることにより、トランジスタ自体がメモリ機能を有するようにすることもできる。 , By using the ferroelectric material, it is also possible to transistor itself to have a memory function. 強誘電性の材料として、例えば、Zn 1−x Li O、Z As ferroelectric materials, for example, Zn 1-x Li x O , Z
1−x (Li Mg n 1-x (Li y Mg x−y )O等を用いることができる。 can be used x-y) O or the like.

【0026】なお、SiNは、例えば、プラズマCV [0026] In addition, SiN, for example, plasma CV
D、スバッタリング等の工程で作成することができる。 D, can be created in the step of the scan grasshopper ring or the like.
SiO は、例えば、プラズマCVD、スバッタリング、スピンオングラス等の工程で作成することができる。 SiO 2, for example, can be created plasma CVD, scan grasshopper ring, with steps such as spin-on-glass.

【0027】第4に、基板16は、主に、絶縁性の材料が用いられ、特に、加熱に比較的弱い材料も使用することができる。 [0027] Fourth, the substrate 16 is mainly insulating material is used, in particular, can also be used relatively weak material to heating. 例えば、ポリエチレン、ポリエチレンテレフタレート(PET)、プラスチック、ポリマーフィルム、各種高分子材料ガラス、サファイア、紙類、可塑性があり透明な絶縁性基板を用いることができる。 For example, it is possible to use polyethylene, polyethylene terephthalate (PET), a plastic, a polymer film, various polymer materials glass, sapphire, paper, a transparent insulating substrate has a plasticity. 例えば、液晶表示画面等のように透明性が要求されるような用途には、透明の基板を用いると良い。 For example, in applications such as transparency as such as a liquid crystal display screen is required, it is preferable to use a transparent substrate. また、基板は、 In addition, the substrate,
用途によっては、透明でない材料を用いても良い。 In some applications, it may be used not transparent material.

【0028】(2)特性 まず、実験に用いた本発明に係るトランジスタの製法の一例を説明する。 [0028] (2) Characteristics First, an example of a method of a transistor according to the present invention used in the experiment. ここでは、図1(A)の構成に従い説明する。 Here, a description will be given in accordance with the configuration of FIG. 1 (A). ゲート電極14としてITO(インジウムドープ酸化すず)(例、120nm)が形成されたガラス、 ITO (indium-doped tin oxide) as the gate electrode 14 (e.g., 120 nm) is formed of glass,
プラスチック、ポリマー等の基板16(例、0.7n Plastic, the substrate 16 such as a polymer (e.g., 0.7 N
m)を用いる。 m) is used. このITO基板上に適宜の厚さ(例えば、400〜500nm)のゲート絶縁層15は、例えば、アモルファスSiN 、SiO 等のプラズマCV The gate insulating layer 15 of the appropriate thickness on the ITO glass substrate (e.g., 400-500 nm), for example, amorphous SiN x, plasma CV such SiO x
D、Al 、MgO等の蒸着又はスパッタリングなどで形成する。 D, Al 2 O 3, formed like a deposition or sputtering such as MgO. このように、ベーキング工程を省略する方法でゲート絶縁層15を形成することにより、室温等の低温での半導体デバイスの製作が可能となる。 Thus, by forming the gate insulating layer 15 a baking step is omitted method enables fabrication of semiconductor devices at low temperatures such as room temperature. その後に、パルスレーザー堆積法CVD法、スパッタリンク法等で3d遷移金属元素として、例えばNiを添加したZ Thereafter, pulsed laser deposition CVD method, a 3d transition metal elements in the sputtering link method, for example, the addition of Ni Z
nOのチャネル層11を室温で50〜150nm堆積させた。 A channel layer 11 of nO was 50~150nm deposited at room temperature. 成長条件は、例えば、酸素分圧1×10 −1 to The growth conditions are, for example, an oxygen partial pressure of 1 × 10 -1 to
rr、基板温度10〜30℃程度である。 rr, and a substrate temperature of 10 to 30 ° C. approximately. さらに、ウェットエッチング又はドライエッチングによりチャネル層11を加工した後、オーミック電極であるAlのソース12、ドレイン13の各電極を蒸着し、チャネル長及びチャネル幅をそれぞれ、例えば30μm及び150μm Further, after processing the channel layer 11 by wet etching or dry etching, the source 12 of Al is an ohmic electrode, and depositing the electrodes of the drain 13, channel length and the channel width, respectively, for example, 30μm and 150μm
のボトムゲート型の半導体デバイスを作製した。 The semiconductor device of bottom-gate-type was produced. なお、 It should be noted that,
ゲート絶縁層15としてSOGをスピンコートして低温ベーキングすることで形成することもできる。 Can also be formed by low-temperature baking an SOG is spin-coated as a gate insulating layer 15. この場合、製作上最高温度は、低温ベーキングする工程におけるものとなり、低く抑えることができる。 In this case, fabricated on the maximum temperature becomes as in the step of low temperature baking can be kept low. なお、以上の製法は、一例であり、各材料、各種パラメータ、工程は適宜変更することができる。 The above method is an example, each material, various parameters, steps can be changed as appropriate.

【0029】ここで、本発明の顕著な効果を説明するための比較として、図3に、従来のトランジスタ特性の説明図を示す。 [0029] Here, as a comparison to illustrate the remarkable effects of the present invention, FIG. 3 shows an explanatory view of a conventional transistor characteristics. 図3(A)は、ゲート電圧Vgを−5から5Vまで振ったときのソース・ドレイン間の電圧・電流特性を示す。 Figure 3 (A) shows the voltage-current characteristics between the source and the drain when shook gate voltage Vg from -5 to 5V. この図では、キャリアを空乏(deplete) In this figure, the carrier depletion (deplete)
しているはずの負のゲート電圧でも電流が流れてしまっている。 I've current flows even in a negative gate voltage of should have. 本来は横軸に張り付くような(ドレイン電流I Originally as sticks to the horizontal axis (the drain current I
dが0に近づくような)特性でなければいけない。 d is as close to 0) must be the characteristics. 図3 Figure 3
(B)はソース・ドレイン間の電圧Vdsを10Vで固定したときに流れるドレイン電流Idをゲート電圧Vg (B) the drain current Id and gate voltage Vg which flows when a fixed 10V voltage Vds between the source and drain
の関数として表示したものである。 One in which the display as a function. この図では、ゲート電圧Vgを変化させてもたかだか2倍しかドレイン電流Idが変調されていない。 In this figure, at most 2 times only the drain current Id is not modulated also by changing the gate voltage Vg. この理由は、酸素欠損や格子間Znなどの電流を放出するドナーが存在し、チャネルZnO中に多数の電子が注入されているため、電界をかけてもそれらを完全に空乏できないことが原因であると考えられる。 The reason is, there is a donor of releasing current such as oxygen vacancy and interstitial Zn, since a large number of electrons are injected into the channel ZnO, because not Deki depleted them completely even by applying an electric field It is believed that there is. 一般に、Liは、1価の陽イオンで、Zn In general, Li is a monovalent cation, Zn
O中の電子を補償する添加物として知られている。 The electrons in O is known as an additive to compensate. 実際にLiを添加して作ったトランジスタも、アニール処理をしないと、ゲート電圧Vgをオフとしても又はマイナスとしてもドレイン電流Idがオフしない場合があった。 Indeed transistor made by adding Li also unless the annealing treatment, the drain current Id as both or minus as an off-gate voltage Vg is in some cases not clear. なお、例えば、600℃程度でのアニールを施すと、良好なトランジスタ特性を示す。 Incidentally, for example, when subjected to annealing at about 600 ° C., it exhibits good transistor characteristics.

【0030】このように、従来は、チャネル層の抵抗を十分に上げられないため、off状態でもon状態と同じオーダーのドレイン電流が流れている。 [0030] Thus, conventionally, since not sufficiently increase the resistance of the channel layer, the drain current of the same order are flows on state even in the off state. この様なトランジスタの特性は、純粋なZnOをチャネル層に使用した場合や、抵抗率を上げるためにLiを添加した場合でもその後の熱処理(600℃でのアニール)を施さない場合等にあらわれる。 The characteristics of such transistors, and when using pure ZnO for the channel layer, appear in such case not subjected to subsequent heat treatment even when added Li (annealing at 600 ° C.) to increase the resistivity.

【0031】つぎに、図4に、本発明のトランジスタの特性図(1)を示す。 Next, FIG. 4 shows a characteristic diagram of the transistor of the present invention (1). これは、各々のゲード電圧Vgにおいてドレイン・ソース電圧Vdsを変化させたときのドレイン電流Idを示す。 This indicates the drain current Id with respect to a change in the drain-source voltage Vds in each of Gade voltage Vg. 図示のように、ゲート電圧V As shown, the gate voltage V
gの変化に対して、ドレイン電流Idの増幅がみられ、 For the g changes in, the amplification of the drain current Id is observed,
ドレイン・ソース電圧Vdsが4〜6V付近でピンチオフしていることが確認できる。 Drain-to-source voltage Vds can be confirmed to be pinched off in the vicinity of 4~6V. このように、本発明のトランジスタは、チャネル層の形成工程等でアニールをしなくても、良好なon−off特性とピンチオフがみられる。 Thus, the transistor of the present invention, without the annealing in forming process such as the channel layer, good on-off characteristics and pinch-off is observed.

【0032】図5に、本発明のトランジスタの特性図(2)を示す。 [0032] FIG. 5 shows the characteristic diagram of the transistor of the present invention (2). 図5(A)、(B)は、あるドレイン・ Figure 5 (A), (B) is the drain-
ソース電圧Vds(例、10V)においてゲート電圧V Source voltage Vds (eg, 10V) at the gate voltage V
gを変化させたときのドレイン電流Id及びその平方根Idをそれぞれ示す。 It shows the drain current Id and its square root Id when changing the g respectively. 図5(A)は、on/off比を見やすい形にしたもので、off状態で10 −10 A、 FIG. 5 (A), obtained by the easily visible shape of the on / off ratio, in the off state 10 -10 A,
ON状態で10 −5 Aと5桁以上のon/off比(例、2×10 )を実現している。 10 -5 A and 5-digit or more on / off ratio in the ON state (e.g., 2 × 10 5) is realized. 図5(B)は、トランジスタがon状態になるしきい値を求めるためのグラフで、ここでは、一例として、1.4Vというしきい値が得られた。 FIG. 5 (B), a graph for obtaining the threshold transistor is turned on, as an example, threshold of 1.4V is obtained. また、本発明のトランジスタは、LiドープのZnOと比較して、電界効果移動度の向上も確認できた。 The transistor of the present invention, as compared to ZnO of Li doped, it was confirmed improving field.

【0033】(3)他の実施の形態のFET 図6に、本発明に係るトランジスタの第2の実施の形態の断面図を示す。 [0033] (3) the FET 6 of another embodiment, showing a cross-sectional view of a second embodiment of a transistor according to the present invention. 図6(A)に示されるように、第1の実施の形態のトランジスタは、FETに関するものあり、チャネル層11、ソース12、ドレイン13、ゲート14、ゲート絶縁層15、基板16を備える。 As shown in FIG. 6 (A), the transistor of the first embodiment, there relates FET, comprises a channel layer 11, source 12, drain 13, gate 14, gate insulating layer 15, the substrate 16. 基板1 Substrate 1
6に上には、チャネル層11が形成される。 The upper 6, the channel layer 11 is formed. チャネル層11には、ゲート絶縁層15、ソース12及びドレイン13が形成される。 The channel layer 11, the gate insulating layer 15, the source 12 and drain 13 are formed. ゲート絶縁層15の上には、ゲート14が形成される。 On the gate insulating layer 15, a gate 14 is formed.

【0034】図6(B)には、第1の実施の形態の変形例が示される。 [0034] in FIG. 6 (B), a modification of the first embodiment is shown. このトランジスタは、基板16の上に、 This transistor on the substrate 16,
チャネル層11が形成される。 The channel layer 11 is formed. さらに、チャネル層11 Further, the channel layer 11
には、ソース12及びドレイン13がオーミック接合により、ゲート14がショットキー接合により、それぞれ形成される。 The source 12 and drain 13 by ohmic junction, gate 14 by Schottky junction, is formed, respectively. この例では、図1(A)と比べてゲート絶縁層15がないため、ソース12及びドレイン13とゲート14との間は適当な隙間が設けられる。 In this example, since there is no gate insulating layer 15 than Fig. 1 (A), between the source 12 and drain 13 and the gate 14 is suitable clearance is provided.

【0035】図7に、本発明に係るトランジスタの第3 [0035] FIG. 7, the third transistor according to the present invention
の実施の形態の断面図を示す。 It shows a cross-sectional view of the embodiment. 図7(A)に示される第3の実施の形態のトランジスタは、FETに関するもので、チャネル層21、ソース22、ドレイン23、ゲート24、ゲート絶縁層25、基板26を備える。 Transistor of the third embodiment shown in FIG. 7 (A), comprises relates FET, the channel layer 21, source 22, drain 23, gate 24, gate insulating layer 25, the substrate 26. 基板2 Substrate 2
6の上にソース22及びドレイン23が形成される。 The source 22 and drain 23 are formed on the 6. これらを覆うように、チャネル層21が形成される。 As to cover them, the channel layer 21 is formed. チャネル層21には、さらに、ゲート絶縁層25が形成される。 The channel layer 21 further, the gate insulating layer 25 is formed. ゲート絶縁層25の上には、ゲート24が形成される。 On the gate insulating layer 25, a gate 24 is formed. ここでは、ゲート24、ゲート絶縁層25及びチャネル層21が、MIS構造となっている。 Here, the gate 24, the gate insulating layer 25 and the channel layer 21 has a MIS structure.

【0036】図7(B)に、本発明に係るトランジスタの第3の実施の形態の変形の断面図を示す。 [0036] in FIG. 7 (B), it shows a cross-sectional view of a modification of the third embodiment of the transistor according to the present invention. このトランジスタは、第2の実施の形態の変形であり、図7(A) This transistor is a modification of the second embodiment, FIG. 7 (A)
に示されたトランジスタとは、ゲート絶縁層25が形成されておらず、ゲート24とチャネル層21とがショットキー接合の構造となっている。 In The indicated transistors, not the gate insulating layer 25 is formed, a gate 24 and the channel layer 21 has a structure of the Schottky junction. 図7(A)のようにゲート絶縁層25を有する場合は、ゲートの印加電圧の制限が少ない。 If having a gate insulating layer 25 as shown in FIG. 7 (A) is less restrictive of the voltage applied to the gate. これに対し、図7(B)のようにゲート絶縁層25を有しない場合は、ゲート−ソース間及びゲート−ドレイン間の絶縁耐圧が低くなる。 In contrast, when no gate insulating layer 25 as shown in FIG. 7 (B), the gate - source and gate - dielectric strength between the drain is lowered. また、この場合は、製造プロセスは簡単となる。 In this case, the manufacturing process becomes simple.

【0037】図8に、本発明に係るトランジスタの第4 [0037] Figure 8, a fourth transistor of the present invention
の実施の形態の断面図を示す。 It shows a cross-sectional view of the embodiment. 第4の実施の形態のトランジスタは、FETに関するものであり、チャネル層3 Transistor of the fourth embodiment relates to a FET, the channel layer 3
1、ソース32、ドレイン33、ゲート34、ゲート絶縁層35、基板36を備える。 Comprising 1, source 32, drain 33, gate 34, gate insulating layer 35, the substrate 36. 基板36の上にチャネル層31が形成される。 Channel layer 31 is formed on the substrate 36. チャネル層31には、ゲート絶縁層35が形成され、ゲート絶縁層35の上には、ゲート34が形成される。 The channel layer 31, a gate insulating layer 35 is formed on the gate insulating layer 35, a gate 34 is formed. ソース32及びドレイン33は、例えば、ゲート絶縁層35をマスクとする拡散又はイオン注入等により、形成されることができる。 The source 32 and drain 33, for example, by diffusion or ion implantation or the like to the gate insulating layer 35 as a mask, may be formed. また、この実施例の変形としてゲート34のサイズを適宜設定することにより、ゲート絶縁層35を省略することもできる。 Further, by appropriately setting the size of the gate 34 as a modification of this embodiment, it is also possible to omit the gate insulating layer 35.

【0038】なお、上述の第2〜第4の実施の形態において、各構成要素の材料は、第1の実施の形態で説明したものと同様である。 [0038] Note that in the second to fourth embodiments described above, the material of each component is the same as that described in the first embodiment.

【0039】(4)バイポーラトランジスタ 図9に、本発明に係るトランジスタの第5の実施の形態の断面図を示す。 [0039] (4) in the bipolar transistor 9 shows a cross-sectional view of a fifth embodiment of a transistor according to the present invention. 第5の実施の形態のトランジスタは、 Transistor of the fifth embodiment,
バイポーラトランジスタに関するもので、ベース41、 It relates to a bipolar transistor, the base 41,
エミッタ42及びコレクタ43、ベース電極44、エミッタ電極45及びコレクタ電極46、基板47を備える。 Emitter 42 and collector 43, base electrode 44, emitter electrode 45 and collector electrode 46 includes a substrate 47.

【0040】npn形トランジスタでは、エミッタ42 [0040] In npn type transistor, the emitter 42
及びコレクタ43は、n形透明半導体により形成され、 And the collector 43 is formed of n-type transparent semiconductor,
ベース41はp形透明半導体により形成される。 Base 41 is formed by p-type transparent semiconductor. ベース電極44、エミッタ電極45及びコレクタ電極46は、 Base electrode 44, emitter electrode 45 and collector electrode 46,
ベース41、エミッタ42及びコレクタ43上にそれぞれ形成される。 Base 41, are formed respectively on the emitter 42 and the collector 43. 同様に、pnp形トランジスタでは、括弧内で示したように、エミッタ42及びコレクタ43 Similarly, pnp-type transistor, as shown in parentheses, the emitter 42 and collector 43
は、p形透明半導体により形成され、ベース41は、n Is formed by p-type transparent semiconductor, base 41, n
形透明半導体により形成される。 It is formed by the shape transparent semiconductor. バイポーラトランジスタは、FETと比較して、大電流を流すことができるので、レーザ駆動等の大電流を必要とする場合等に、特に有利である。 Bipolar transistors, as compared to FET, it is possible to flow a large current, such as when requiring a large current of the laser driving such, is particularly advantageous.

【0041】以下に、各構成要素の材料について説明する。 [0041] The following describes the material of each component. n形透明半導体としては、例えばn形ZnOが使用される。 The n-type transparent semiconductor, for example, n-type ZnO is used. n形ZnOは、例えば、III族元素(B、A n-type ZnO, for example, III group elements (B, A
l、Ga、In、Tl)、VII族元素(F、Cl、B l, Ga, In, Tl), VII group elements (F, Cl, B
r、I)をドープし、さらに3d遷移金属元素をドープしたZnOである。 r, doped I), and ZnO was further doped with 3d transition metal elements. p形透明半導体としては、例えばp As the p-type transparent semiconductor, for example p
形ZnOが使用される。 Form ZnO is used. p形ZnOは、例えば、I族元素(Li、Na、K、Rb、Cs)、V族元素(N、 p-type ZnO is e.g., I group elements (Li, Na, K, Rb, Cs), V group elements (N,
P、As、Sb、Bi)をドープし、さらに3d遷移金属元素をドープしたZnOである。 P, doped As, Sb, Bi) and a doped ZnO more 3d transition metal element. これらの各元素のドープ量は、素子の寸法、厚さ、集積度、性能等に応じて適宜の量とすることができる。 Doping amount of each of these elements, the dimensions of the device, thickness, density, may be an appropriate amount depending on the performance and the like.

【0042】ベース電極44、エミッタ電極45及びコレクタ電極46の材料は、第1の実施の形態で説明したソース12、ドレイン13又はゲート14の材料と同様である。 The material of the base electrode 44, emitter electrode 45 and collector electrode 46, a source 12 described in the first embodiment is the same as the material of the drain 13 and the gate 14. すなわち、透明電極としては、例えば、III族元素(B、Al、Ga、In、Tl)、VII族元素(F、Cl、Br、I)、I族元素(Li、Na、K、 That is, as the transparent electrode, for example, III group elements (B, Al, Ga, In, Tl), VII group elements (F, Cl, Br, I), I group elements (Li, Na, K,
Rb、Cs)のいずれかをドープした導電性ZnO、又は各種元素をドープしない導電性ZnO等の透明導電性材料が用いられる。 Rb, or a doped conductive ZnO of Cs), or the various elements transparent conductive material such as conductive ZnO which is not doped is used. ここで、これらの元素をドープする場合、ドープ量は適宜設定することができる(例えば、 Here, when doping these elements, the doping amount can be appropriately set (e.g.,
高濃度にn形をドープしたn ++ −ZnO等を用いることができるが、これに限定されない)。 It can be used n ++ -ZnO like the heavily doped n-type, but not limited to). さらに、ベース電極44、エミッタ電極45及びコレクタ電極46としては、その他に、In 、SnO 、(In−S Furthermore, as the base electrode 44, emitter electrode 45 and collector electrode 46, the other, In 2 O 3, SnO 2 , (In-S
n)O などの透明導電体を用いることができる。 transparent conductor such as n) O x can be used. また、透明な材料以外にも、Al、Cu等の金属や、高ドープした半導体ポリシリコン等の透明でない電極材料を用いても良い。 In addition to transparent material, Al, metal, such as Cu, may be used not transparent electrode material such as a semiconductor polysilicon highly doped. さらに、透明又は透明でない材料を、これら電極の全部又は一部に適宜選択して用いることができる。 Furthermore, the non-transparent or transparent material, may be suitably selected in all or part of the electrodes.

【0043】また、このように、本発明の他の実施の形態では、ゲート電圧を負に大きくかけたとき、ホールのチャネルが反転し、電界でp型酸化亜鉛ができる。 [0043] Also, in this way, in other embodiments of the present invention, when subjected increasing the gate voltage in the negative, the channel hole is inverted, it is p-type zinc oxide in an electric field. p型ZnOは、発光ダイオードやレーザーなどpn接合に利用できるだけでなく、C−MOS型トランジスタを作成できるので、回路設計や応用に格段の広がりができる。 p-type ZnO can be used not only in the pn junction such as a light emitting diode or a laser, it is possible to create a C-MOS type transistor can remarkably spread in the circuit design and application.

【0044】(5)積層形半導体装置 図10に、積層形半導体装置の断面図を示す。 [0044] (5) Laminated semiconductor device Figure 10 shows a cross-sectional view of a stacked-type semiconductor device. これは、 this is,
一例として、第1の実施の形態のトランジスタを積層した場合を示す。 As an example, a case of stacking the transistors of the first embodiment. すなわち、チャネル層11、ソース1 That is, the channel layer 11, source 1
2、ドレイン13、ゲート14、ゲート絶縁層15及び基板16を備えたトランジスタの上に、さらに、第2のトランジスタが形成される。 2, a drain 13, a gate 14, over the transistor with a gate insulating layer 15 and the substrate 16, further, the second transistor is formed. その際、第1のトランジスタと第2のトランジスタの間には、絶縁層57及び導電遮蔽層58が形成される。 At that time, between the first transistor and the second transistor, the insulating layer 57 and the conductive shielding layer 58 is formed. 導電遮蔽層58は、第1と第2のトランジスタを電気的に遮蔽するものである。 Conductive shielding layer 58 is to electrically shield the first and the second transistor. 第2 The second
のトランジスタとしては、基板となる絶縁層59が形成され、その上に、第2のソース52、第2のドレイン5 The transistor, an insulating layer 59 serving as a substrate is formed, thereon, the second source 52, second drain 5
3が形成される。 3 is formed. さらに、これらを覆うように第2のチャネル層51が形成され、その上に、第2のゲート絶縁層55及び第2のゲート54が形成される。 Further, the second channel layer 51 so as to cover these forms, on its second gate insulating layer 55 and the second gate 54 is formed.

【0045】絶縁層57、59の材料は、ゲート絶縁層15と同様のものでも良いし、透明基板16と同様の他の絶縁材料を用いても良い。 The material of the insulating layer 57 and 59 may be the same as the gate insulating layer 15, it may be used other similar insulating material as the transparent substrate 16. 導電遮蔽層58の材料は、 Material of the conductive shield layer 58,
ソース12、ドレイン13及びゲート14等と同様のものを使用することができる。 Source 12, can be used the same drain 13 and gate 14 or the like. なお、絶縁層57(又は5 The insulating layer 57 (or 5
9)を、チャネル層11(又は、チャネル層11とゲート絶縁層15)の厚さより十分厚くすることにより、導電遮蔽層58及び絶縁層59(又は57)を省略することもできる。 9), the channel layer 11 (or, by sufficiently thicker than the thickness of the channel layer 11 and the gate insulating layer 15), it is also possible to omit the conductive shielding layer 58 and an insulating layer 59 (or 57).

【0046】トランジスタを積層する際は、チャネル層11、第2のチャネル層51又は絶縁層57等は、必要に応じ適宜平坦化されると良い。 [0046] When stacking the transistors, the channel layer 11, such as the second channel layer 51 or insulating layer 57, may be appropriately flattened as needed. なお、平坦化プロセスが加わるとコスト増加の可能性があるので、これらの内適宜の層のみを平坦化するようにしても良い。 Note that it there is a possibility of cost increases when applied planarization process, be flattened only appropriate layer of these. また、積層するトランジスタの数は、必要に応じて適宜の個数重ねることができる。 Further, the number of transistors to be stacked can be superimposed appropriate number if necessary. また、上述の第1〜第5の実施の形態のトランジスタを適宜選択して積層することができる。 Further, it can be laminated by properly selecting the transistors of the first to fifth embodiments described above. さらに、複数の種類のトランジスタを選択して混合して積層しても良い。 Furthermore, it may be laminated and mixed to select multiple types of transistors.

【0047】(6)発光素子への適用 図11(A)及び(B)に、本発明に係るFETを発光素子の駆動に適用した半導体装置の断面図及び回路図を示す。 [0047] (6) applied to the light emitting element Figure 11 (A) and (B), a sectional view and a circuit diagram of a semiconductor device to which the FET according to the present invention for driving the light emitting element. 図11(A)の断面図のa、b及びcは、図11 a cross-sectional view of FIG. 11 (A), b and c, FIG. 11
(B)の回路図のa、b及びcに対応する。 a circuit diagram of a (B), corresponding to b and c. このデバイスでは、チャネル層61、ソース62、ドレイン63、 In this device, the channel layer 61, source 62, drain 63,
ゲート64、ゲート絶縁層65及び基板66によりトランジスタが形成される。 Gate 64, the transistor is formed by the gate insulating layer 65 and the substrate 66. さらに、ドレイン63の領域の上に、半導体層67が形成されることにより、ドレイン63と半導体層67で発光部が形成される。 Further, on the area of ​​the drain 63, by the semiconductor layer 67 is formed, the light emitting portion in the drain 63 and the semiconductor layer 67 is formed. また、ソース電極68、ゲート電極69及び発光部電極60が設けられている。 The source electrode 68, gate electrode 69 and the light emitting portion electrode 60 is provided. 発光部としては、ドレイン63としてn形半導体を使用した場合は、半導体層67はp形半導体を用いる。 The light-emitting unit, in the case of using an n-type semiconductor as a drain 63, the semiconductor layer 67 is a p-type semiconductor. 一方、ドレイン63としてp形半導体を用いた場合は、半導体層67はn形半導体を用いる。 On the other hand, in the case of using a p-type semiconductor as a drain 63, the semiconductor layer 67 is an n-type semiconductor.

【0048】半導体層67に、ゲート64と同様の透明な半導体材料を用い、発光部電極60に透明な電極材料を用いることにより、発光部は、図において上方向に面発光が可能となる。 [0048] semiconductor layer 67, using the same semiconductor material transparent to the gate 64, by using a transparent electrode material in the light emitting portion electrode 60, the light emitting portion, it is possible to surface-emitting upward in FIG. また、基板66を透明な材料とすることにより、発光部は、図において下方向に面発光が可能となる。 Further, by making the substrate 66 and the transparent material, the light emitting portion, it is possible to surface-emitting downward in FIG. さらに、発光領域が紫外線領域等であれば、 Further, the light emitting region is as long as the ultraviolet region, and the like,
蛍光体を発光部の上又は下(すなわち、半導体層67や発光部電極60の上、又は、基板66の下)等に配置することにより、可視光に変換することもできる。 Above or below the phosphor of the light emitting portion (i.e., on the semiconductor layer 67 and the light emitting portion electrode 60, or below the substrate 66) by placing the like, it can also be converted into visible light.

【0049】図12(A)及び(B)に、本発明に係るバイポーラトランジスタを発光素子の駆動に適用した半導体装置の断面図及び回路図を示す。 [0049] FIG. 12 (A) and (B), a sectional view and a circuit diagram of a semiconductor device using the bipolar transistor according to the present invention for driving the light emitting element. 図12(A)の断面図のa、b及びcは、図12(B)の回路図のa、b 12 of a cross-sectional view of (A) a, b and c, the circuit diagram of FIG. 12 (B) a, b
及びcに対応する。 And corresponding to c. このデバイスでは、ベース71、エミッタ72及びコレクタ73、ベース電極74及びコレクタ電極76、基板77により、トランジスタが形成される。 In this device, the base 71, emitter 72 and collector 73, base electrode 74 and the collector electrode 76, the substrate 77, the transistor is formed. さらに、エミッタ72の領域の上に、半導体層7 Further, on the area of ​​the emitter 72, the semiconductor layer 7
8が形成されることにより、エミック72と半導体層7 By 8 is formed, Emikku 72 and the semiconductor layer 7
8で発光部が形成される。 Emitting portion is formed by 8. また、半導体層78には、発光部電極79が形成される。 Further, the semiconductor layer 78, the light emitting portion electrode 79 is formed. エミッタ72としてn形半導体を使用した場合は、半導体層78はp形半導体を用いる。 When using an n-type semiconductor as the emitter 72, the semiconductor layer 78 is a p-type semiconductor. 一方、エミッタ72としてp形半導体を用いた場合は、半導体層78はn形半導体を用いる。 On the other hand, in the case of using a p-type semiconductor as the emitter 72, the semiconductor layer 78 is an n-type semiconductor.

【0050】半導体層78に、ベース71と同様の透明な半導体材料を用い、発光部電極79に透明な電極材料を用いることにより、発光部は、図において上方向に面発光が可能となる。 [0050] The semiconductor layer 78, using the same semiconductor material transparent base 71, by using a transparent electrode material in the light emitting portion electrode 79, the light emitting portion, it is possible to surface-emitting upward in FIG. また、基板77等を透明な材料とすることにより、発光部は、図において下方向に面発光が可能となる。 Further, by making the substrate 77 and the like with transparent material, the light emitting portion, it is possible to surface-emitting downward in FIG. さらに、発光領域が紫外線領域等であれば、蛍光体を発光部の上又は下(すなわち、半導体層7 Further, if the light emitting region ultraviolet region or the like, above or below the light emitting portion of the phosphor (i.e., the semiconductor layer 7
8や発光部電極79の上、又は、基板77の下)等に配置することにより、可視光に変換することもできる。 On the 8 and the light emitting portion electrode 79, or by placing the bottom) of the substrate 77, it can be converted into visible light.

【0051】なお、第1〜第3の実施の形態のトランジスタについても、同様に、発光部を形成して駆動用として組み合わせることができる。 [0051] Incidentally, for the transistors of the first to third embodiments, similarly, by forming a light-emitting portion can be combined as the drive. また、上述の説明では、 In addition, in the above description,
発光部の一部にソース若しくはドレイン(コレクタ若しくはエミッタ)と連続した領域を使用したが、これに限られず、ソース若しくはドレイン(コレクタ若しくはエミッタ)と接続された他の半導体の領域を形成して、これを発光部の一部として使用しても良い。 Source or drain portion of the light emitting portion is formed from a (collector or emitter) and contiguous regions is not limited thereto, to form other semiconductor region connected to the source or drain (collector or emitter), This may be used as a part of the light-emitting portion. また、発光部は、発光ダイオードでもレーザダイオードでもよく、適宜の発光デバイスを形成することができる。 The light emitting unit may be a laser diode in the light emitting diode, it is possible to form a suitable light emitting devices. さらに、本発明を適用すると、透明なトランジスタにより透明なZ Furthermore, when applying the present invention, clear the transparent transistor Z
nO発光素子を駆動することにより、全て透明な半導体装置を作成することもできる。 By driving the nO light emitting element, it is also possible to create all transparent semiconductor device. また、一部を透明とすることもできる。 In addition, it is also possible to a part transparent.

【0052】さらに、発光部としては、多層反射膜や、 [0052] Further, as the light-emitting portion, and the multilayer reflective film,
ダブルへテロ構造、面発光レーザ構造など、適宜の構成を採用して組み合わせることができる。 A double heterostructure, such as a surface emitting laser structure can be combined by employing an appropriate configuration. また、発光部及びトランジスタを複数個マトリクス状に配列し、各発光部を各々透明なトランジスタで駆動することにより、ディスプレー、照明パネル、部分調光照明パネル等に適宜応用することができる。 Further, the light emitting portion and a transistor arranged in a plurality matrix, by driving each light-emitting portion in each transparent transistors, displays, lighting panels, can be applied appropriately to the partial dimming lighting panel.

【0053】(7)メモリへの適用 図13(A)及び(B)に、本発明に係るFETをメモリ素子の制御に適用したデバイスの断面図及び回路図を示す。 [0053] (7) for application to the memory Figure 13 (A) and (B), a sectional view and a circuit diagram of a device of the FET according to the present invention is applied to control of a memory device. 図13(A)の断面図のa、b及びcは、図13 a cross-sectional view of FIG. 13 (A), b and c, FIG. 13
(B)の回路図のa、b及びcに対応する。 a circuit diagram of a (B), corresponding to b and c. このデバイスでは、チャネル層81、ソース82、ドレイン83、 In this device, the channel layer 81, source 82, drain 83,
ゲート84、ゲート絶縁層85及び基板86によりトランジスタが形成される。 Gate 84, the transistor is formed by the gate insulating layer 85 and the substrate 86. ソース82上には、これと同様の透明導電性材料による導電層88が形成される。 On the source 82, the conductive layer 88 is formed by the same transparent conductive material therewith. さらに、ドレイン83の領域の上に、ゲート絶縁層85を介して半導体層又は導体層87が形成され、これら構成要素により、コンデンサが形成される。 Further, on the area of ​​the drain 83, the semiconductor layer or conductor layer 87 is formed via a gate insulating layer 85, these components, a capacitor is formed. ここでは、コンデンサの電極間絶縁体としてゲート絶縁層85を用いているが、これとは別の絶縁層を形成して使用しても良い。 Here, although the use of the gate insulating layer 85 as an electrode between the insulator of the capacitor may be used to form another insulating layer to this.
また、コンデンサの電極としては、ドレイン又はソースと連続した領域を用いても良いし、ドレイン又はソースと接続されたその他の半導体領域又は導体領域を用いても良い。 Further, as the electrode of the capacitor, it may be used a continuous region and the drain or source, or may be other semiconductor regions or conductor areas connected to the drain or source. コンデンサを形成する電極材料としては、透明材料でも透明でない材料でもよく、一部透明材料を用いても良い。 As an electrode material for forming a capacitor, may be a non-transparent in a transparent material materials may be used partially transparent material. これら各層又は領域に対して適宜透明な材料を用いることにより、全体又は一部が透明なメモリを作成することができる。 By using an appropriate material transparent to these layers or regions may be whole or in part to create a clear memory.

【0054】また、本発明に係るバイポーラトランジスタを用いた場合にも、基板上に適宜コンデンサを形成することにより、メモリへ応用することができる。 [0054] In the case of using a bipolar transistor according to the present invention also, by forming the appropriate capacitor on a substrate, it can be applied to the memory. すなわち、例えば、上述の実施の形態のようなバイポーラトランジスタにおいて、コレクタ若しくはエミッタと連続した領域、又は、コレクタ若しくはエミッタと接続された他の半導体若しくは導体の領域と、この領域上の絶縁層と、絶縁層上の半導体層又は導体層とによりコンデンサを形成することができる。 That is, for example, in a bipolar transistor such as the embodiment described above, a continuous region and the collector or emitter, or with other semiconductor or conductor areas connected to the collector or emitter, an insulating layer on the region, it is possible to form the capacitor by a semiconductor layer or conductor layer on the insulating layer.

【0055】なお、メモリに応用する際は、トランジスタ及びコンデンサをマトリクス状に配列し、各コンデンサを各トランジスタで駆動することにより、メモリデバイスを実現することができる。 [0055] Incidentally, when applying to the memory, by arranging the transistors and capacitors in a matrix, to drive each capacitor in each transistor, it is possible to realize a memory device.

【0056】(8)表面弾性波素子SAW(Surface Ac [0056] (8) surface acoustic wave device SAW (Surface Ac
oustic Wave) 図14に、本発明に係る半導体デバイスのSAWに適用した構成図を示す。 The oustic Wave) FIG. 14 shows a block diagram applied to SAW semiconductor device according to the present invention. 図14(A)には、SAWの斜視図を、図14(B)には、そのB−B'断面図をそれぞれ示す。 The FIG. 14 (A), the perspective view of SAW, in FIG. 14 (B) shows the cross section B-B 'view, respectively.

【0057】SAWは、基板111、半導体層112、 [0057] SAW a substrate 111, a semiconductor layer 112,
入力電極113及び出力電極114を備える。 An input electrode 113 and output electrode 114. SAW SAW
は、入力電極113から、高周波信号が入力されると、 From the input electrode 113, the high frequency signal is input,
SAWのフィルタ特性により、適宜の信号が出力電極1 The filter characteristics of the SAW, appropriate signals are output electrode 1
14から出力される半導体デバイスである。 A semiconductor device that is output from the 14. 半導体層1 Semiconductor layer 1
12は絶縁性半導体であり、ベースとしては、第1の実施の形態で述べた各材料を適宜用いることができる。 12 is an insulating semiconductor, as the base, it is possible to use the materials described in the first embodiment as appropriate. 半導体層112としては、例えば、1価の価数を取りうる元素又はV族元素又は3d遷移金属元素をドープした絶縁性ZnO、SiN、SiO 等の透明絶縁性半導体を用いることができる。 As the semiconductor layer 112, for example, can be used a monovalent element or group V element can take the valence or 3d transition metal element-doped insulating ZnO, SiN, a transparent insulating semiconductor such as SiO 2.

【0058】(9)その他の応用 本発明のトランジスタは、発光素子、コンデンサ等の他の素子と同一基板に作成することができる。 [0058] (9) transistors other applications present invention, it is possible to create light-emitting element, in addition to the elements and the same substrate such as a capacitor. また、本発明のトランジスタを、同一種類又は違う種類にて複数形成し、それらトランジスタ間の配線に透明材料を用いることもできる。 Further, the transistor of the present invention, a plurality formed in the same type or different types, may be used a transparent material in the wiring between these transistors. トランジスタ又はこのトランジスタで駆動される素子は、その一部又は全部を、適宜透明とすることができる。 Element driven by transistor or a transistor, a part thereof or all, may be an appropriate transparent. また、トランジスタの大きさ、厚さ、寸法、などは、用途やプロセス等に応じて適宜設計することができる。 The size of the transistor, thickness, dimension, etc., may be appropriately designed depending on the application or process or the like. ドープ量は、製造プロセス、デバイス性能等、必要に応じて適宜設定することができる。 Doping amount, the manufacturing process, device performance, etc., it can be set as needed.

【0059】また、透明n形半導体、透明p形半導体、 [0059] In addition, a transparent n-type semiconductor, transparent p-type semiconductor,
透明導電性材料及び透明絶縁性材料として、半導体をZ As the transparent conductive material and a transparent insulating material, a semiconductor Z
nOをベースとして各元素をドープする例を述べたが、 It has been described an example of doping elements each of nO as a base,
これに限られるものではない。 The present invention is not limited to this. 例えば、酸化亜鉛ZnO For example, zinc oxide ZnO
以外にも、酸化マグネシウム亜鉛Mg Zn 1−x O、 Besides, magnesium zinc oxide Mg x Zn 1-x O,
酸化カドミウム亜鉛Cd Zn 1−x O、酸化カドミウムCdO等適宜の透明材料をベースとして各元素をドープするようにしても良い。 Cadmium oxide, zinc Cd x Zn 1-x O, each element of transparent material cadmium oxide CdO, or the like as appropriate as a base so as to dope the.

【0060】以上述べた他にも、本発明は、紫外光〜X [0060] Also in addition to described above, the present invention is ultraviolet light ~X
線領域の検出器を駆動して信号処理するトランジスタ、 Transistors for signal processing to drive the detector line region,
酸素センサ、そのほか、音波、SAW(Surface Acousti Oxygen sensor, the other, sound waves, SAW (Surface Acousti
c Wave)、圧電性を組み合わせたデバイスに応用することにより、一部又は全部が透明な半導体装置を実現することができる。 c Wave), by applying the device combined piezoelectricity, can be partially or wholly realize the transparent semiconductor device. さらに、本発明は、自動車や家屋等の窓ガラスや透明プラスティック板等に電子回路を作りつけることができる。 Furthermore, the present invention can be applied to make a electronic circuit on a window glass or a transparent plastic plate such as an automobile or a house. また、本発明は、コンピュータ周辺機器、例えば、キーボード、タッチパネル、ポインティングデバイスに、透明にすることができる。 Further, the present invention is a computer peripheral device, for example, a keyboard, a touch panel, pointing device, it can be transparent. 透明であることにより、密かに作成したり、他から見にくいように作成したり、また、デザイン面で斬新なものを提供したりすることができる。 By being transparent, secretly or create, or create so hard to see from the other, also, it is possible or to provide what innovative in terms of design. その他にも、本発明の応用範囲は、 Besides, the application range of the present invention,
非常に広範である。 It is very extensive.

【0061】 [0061]

【発明の効果】本発明によると、以上のように、ZnO According to the present invention, as described above, ZnO
等の透明なチャネル材料にNi等の3d遷移金属元素を添加することで、比較的低温(例えば、室温等)における薄膜形成によっても、所望のon−off比及び移動度を得て、従来の性能を凌駕する非常に高性能の薄膜トランジスタを形成することができる。 By a transparent channel material such addition of 3d transition metal elements such as Ni, a relatively low temperature (e.g., room temperature, etc.) by a thin film formation in, to obtain the desired on-off ratio and mobility, conventional it can very form a high-performance thin film transistor to surpass the performance. また、本発明によると、プラスチック基板、高分子材料基板等、従来熱処理に耐えられない材料を用いて、透明電子回路を形成することができる。 Further, according to the present invention, a plastic substrate, a polymer material substrate or the like, using conventional heat treatment unbearable material, it is possible to form a transparent electronic circuit. また、本発明によると、半導体の性能とプロセスの許容度を著しく向上させることができる。 Further, according to the present invention, it is possible to significantly improve the acceptability of the semiconductor performance and process.

【0062】また、本発明によると、透明トランジスタを、面発光レーザやエレクトロルミネセンス素子等の発光素子の駆動用、メモリ用等のように光デバイス分野での多様な応用に用いることができる。 [0062] According to the present invention, it is possible to use a transparent transistor, for driving the light emitting element such as surface emitting lasers and electroluminescent devices, in a variety of applications in optical devices field as such memory. さらに、本発明によると、透明な電子素子として、各種の幅広い応用に用いた半導体デバイスを提供することができる。 Furthermore, according to the present invention, as a transparent electronic device, it is possible to provide a semiconductor device using a variety of wide applications.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明に係るトランジスタの第1の実施の形態の断面図。 Cross-sectional view of a first embodiment of a transistor according to the present invention; FIG.

【図2】3d遷移金属元素のドープ量と抵抗値の関係についての説明図。 Illustration of the relationship [2] 3d doping amount and the resistance value of the transition metal element.

【図3】従来のトランジスタ特性の説明図。 Figure 3 is an explanatory view of a conventional transistor characteristics.

【図4】従来のトランジスタ特性の説明図。 Figure 4 is an illustration of a conventional transistor characteristics.

【図5】本発明のトランジスタの特性図(2)。 [5] Characteristics of a transistor diagram of the present invention (2).

【図6】本発明に係るトランジスタの第2の実施の形態の断面図。 Cross-sectional view of a second embodiment of a transistor according to the present invention; FIG.

【図7】本発明に係るトランジスタの第3の実施の形態の断面図。 Cross-sectional view of a third embodiment of a transistor according to the present invention; FIG.

【図8】本発明に係るトランジスタの第4の実施の形態の断面図。 Sectional view of a fourth embodiment of the transistor according to the present invention; FIG.

【図9】本発明に係るトランジスタの第5の実施の形態の断面図。 5 cross-sectional view of an embodiment of a transistor according to the present invention; FIG.

【図10】積層形半導体装置の断面図。 FIG. 10 is a cross-sectional view of a stacked-type semiconductor device.

【図11】本発明に係るFETを発光素子の駆動に適用した半導体装置の断面図及び回路。 FIG. 11 is a cross-sectional view and a circuit of a semiconductor device to which the FET according to the present invention for driving the light emitting element.

【図12】本発明に係るバイポーラトランジスタを発光素子の駆動に適用した半導体装置の断面図及び回路図。 Sectional view and a circuit diagram of a semiconductor device according to the bipolar transistor for driving the light emitting device according to the present invention; FIG.

【図13】本発明に係るバイポーラトランジスタを発光素子の駆動に適用した半導体装置の断面図及び回路図。 Sectional view and a circuit diagram of a semiconductor device according to the bipolar transistor for driving the light emitting device according to [13] the present invention.

【図14】本発明に係る半導体デバイスのSAWに適用した構成図。 Diagram applied to SAW semiconductor device according to [14] the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

11 チャネル層 12 ソース 13 ドレイン 14 ゲート 15 ゲート絶縁層 16 基板 11 channel layer 12 and the source 13 drain 14 gate 15 gate insulating layer 16 substrate

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Claims (11)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】酸化亜鉛ZnO、酸化カドミウムCdO、 1. A zinc oxide ZnO, cadmium oxide CdO,
    ZnOにIIB元素若しくはIIA元素若しくはVIB IIB element in ZnO or IIA element or VIB
    元素を加えた化合物又は混合物の内いずれかを用い、3 Using any of the elements of the compound or mixture were added, 3
    d遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物をドープした透明チャネル層と、 III族元素若しくはVII族元素若しくはI族元素若しくはV族元素のいずれかをドープした若しくはドープしない導電性ZnO等の透明導電性材料、In 若しくはSnO 若しくは(In−Sn)O などの透明導電体、又は、透明でない電極材料を、その全部又は一部に用いた、ソース及びドレイン及びゲートと、 前記透明チャンネル層が形成されるための絶縁性基板を備えた半導体デバイス。 A transparent channel layer impurity-doped to the high resistance without loss of transparency of the d transition metal element or rare earth or transparent semiconductor, any of III group element or Group VII element or Group I elements or Group V elements doped use a transparent conductive material such as the or doped non conductive ZnO, in 2 O 3 or SnO 2 or (in-Sn) transparent conductor such as O x, or a non-transparent electrode material, the whole or a part semiconductor devices having had been, and the source and drain and a gate, an insulating substrate for the transparent channel layer is formed.
  2. 【請求項2】前記絶縁性基板は、ポリエチレン、ポリエチレンテレフタレート、プラスチック、ガラス、各種ポリマー、紙類、可塑性があり透明な絶縁性基板のいずれかを用いたことを特徴とする請求項1に記載の半導体デバイス。 Wherein said insulating substrate, wherein polyethylene, polyethylene terephthalate, plastic, glass, various polymers, papers, to claim 1, characterized by using any of the transparent insulating substrate has a plasticity semiconductor devices.
  3. 【請求項3】前記3d遷移金属元素は、ニッケル、マンガン、コバルト又は鉄であることを特徴とする請求項1 Wherein said 3d transition metal element, according to claim 1, wherein nickel, manganese, that cobalt or iron
    に記載の半導体デバイス。 The semiconductor device according to.
  4. 【請求項4】前記透明チャネル層は、複数種類の3d遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物が、各々予め定められた割合又はドープ量でドープされていることを特徴とする請求項1に記載の半導体デバイス。 Wherein said transparent channel layer, impurities in the high-resistance without losing the transparency of the plurality of types of 3d transition metal elements or rare earth or transparent semiconductor, doped with respective predetermined percentage or amount of doping the semiconductor device of claim 1, wherein the are.
  5. 【請求項5】前記透明チャネル層は、3d遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物のドープ量が均一でないことを特徴とする請求項1に記載の半導体デバイス。 Wherein said transparent channel layer according to claim 1, wherein the doping amount of impurities into high-resistance without losing the transparency of the 3d transition metal element or rare earth or transparent semiconductor is not uniform semiconductor device.
  6. 【請求項6】前記透明チャネル層と前記ゲートとの間に、1価の価数を取りうる元素若しくはV族元素若しくは3d遷移金属元素をドープした絶縁性ZnO、Si Between wherein said and said transparent channel layer gate, monovalent valence element or group V can take the number of elements or 3d transition metal element-doped insulating ZnO, Si
    N、SiO 等の透明絶縁性材料、透明絶縁性酸化物、 N, transparent insulating material such as SiO 2, a transparent insulating oxide,
    又は、プラスチック、ポリマーフィルム等の透明絶縁体を用いたゲート絶縁層をさらに備えた請求項1に記載の半導体デバイス。 Or semiconductor device according to claim 1, further comprising a plastic, a gate insulating layer using a transparent insulator such as a polymer film.
  7. 【請求項7】前記透明チャネル層と前記ゲートとの間に、Zn 1−x Li O又はZn 1− (Li Mg 7. between the said transparent channel layer gate, Zn 1-x Li x O or Zn 1- x (Li y Mg
    x−y )O等の強誘電性の透明絶縁材料を用いたゲート絶縁層をさらに備え、前記ゲート絶縁層がメモリ機能を有することを特徴とする請求項1に記載の半導体デバイス。 The semiconductor device of claim 1, further comprising a gate insulating layer using the x-y) ferroelectric transparent insulating material such as O, the gate insulating layer is characterized by having a memory function.
  8. 【請求項8】前記ドレイン若しくはソースと連続した領域、又は、前記ドレイン若しくはソースと接続された他の半導体の領域と、前記領域に接合された半導体層とにより形成される発光部をさらにを備えた請求項1に記載の半導体デバイス。 8. region contiguous with the drain or source, or, further comprising a further semiconductor region connected to the drain or source, the light-emitting portion formed by a semiconductor layer bonded to the region the semiconductor device of claim 1.
  9. 【請求項9】III族元素若しくはVII族元素をドープし、 9. doped with a Group III element or Group VII element,
    さらに3d遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物をドープしたZn Further 3d transition metal element or Zn which impurity-doped to the high resistance without loss of transparency of the rare earth or transparent semiconductor
    O等の透明n形半導体により形成されたエミッタ並びにコレクタ、又は、ベースと、 I族元素若しくはV族元素をドープし、さらに3d遷移金属元素又は希土類又は透明半導体の透明性を失わせずに高抵抗にする不純物をドープしたZnO等の透明p形半導体により形成されたベース、又は、エミッタ並びにコレクタと、 III族元素若しくはVII族元素若しくはI族元素のいずれかをドープした若しくはドープしない導電性ZnO等の透明導電性材料、In 若しくはSnO 若しくは(In−Sn)O などの透明導電体、又は、透明でない電極材料を、その全部又は一部に用い、前記ベース、 O transparent n-type semiconductor by forming emitter and collector, such as, or base and, doped with a Group I element or group V element, high without further loss of transparency of the 3d transition metal element or rare earth or transparent semiconductor impurity-doped base formed of a transparent p-type semiconductor such as ZnO to the resistance, or the emitter and collector and conductive ZnO which is not doped or doped with either group III elements or group VII element or group I element a transparent conductive material, an in 2 O 3 or SnO 2 or (in-Sn) transparent conductor, such as O x equal, or, a non-transparent electrode material, used in whole or in part, the base,
    エミッタ及びコレクタにそれぞれ形成された、ベース電極及びエミッタ電極及びコレクタ電極を備えた半導体デバイス。 Semiconductor devices having respectively formed on the emitter and collector, the base electrode and the emitter and collector electrodes.
  10. 【請求項10】前記コレクタ若しくはエミッタと連続した領域、又は、前記コレクタ若しくはエミッタと接続された他の半導体の領域と、前記領域に接合された半導体層とにより形成される発光部をさらにを備えた請求項9 10. region continuous with the collector or emitter, or even a further semiconductor region connected to the collector or emitter, the light-emitting portion formed by a semiconductor layer bonded to the region It claims 9
    に記載の半導体デバイス。 The semiconductor device according to.
  11. 【請求項11】請求項1又は7に記載の半導体デバイスを、1価の価数を取りうる元素若しくはV族元素若しくは3d遷移金属元素をドープした絶縁性ZnO、Si 11. The method of claim semiconductor device according to 1 or 7, monovalent element can take the valence or V element or 3d transition insulating ZnO metal element-doped, Si
    N、SiO 等の透明絶縁性材料、透明絶縁性酸化物、 N, transparent insulating material such as SiO 2, a transparent insulating oxide,
    又は、プラスチック、ポリマーフィルム等の透明絶縁体を用いた絶縁層を介して、複数個積層したことを特徴とする半導体デバイス。 Or, plastic, via an insulating layer using a transparent insulator such as a polymer film, a semiconductor device which is characterized in that a plurality stacked.
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