JPH0151228B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a system for outputting processing results of an electronic computer to a facsimile terminal device.

(Background Art) With the spread of facsimile, facsimile terminal devices have been used not only for communication between terminals, but also for communication with computers located at a center, that is, as input/output devices for computers. It has also come to be used as a. However, the information handled by electronic computers is, for example, JIS.
In contrast to code-like codes, the information handled by facsimile terminals is a pattern represented by dots depending on the shade of the image, so communication between a computer and facsimile terminal requires mutual communication. This requires so-called facsimile data conversion. Therefore, in order to output a character code output from a computer to a facsimile terminal, the character code is converted into a dot matrix, which is scanned, converted into a facsimile signal, and sent to the facsimile terminal. A block diagram at this time is shown in FIG. The character code output from the computer CPU is converted into a dot pattern by the character code/dot matrix conversion circuit FNT and written into the buffer memory BUF. The facsimile signal sending circuit FAXS scans the buffer memory BUF, converts it into a facsimile signal, and sends it to the facsimile terminal device. At this time, the amount of data transferred to the buffer memory BUF increases after being converted into a dot pattern by the character code/dot matrix conversion circuit FNT. For example, if the character code is 8 bits and the dot matrix configuration is 16 (horizontal) x When set to 18 (vertical), buffer memory
The amount of data transferred to the BUF is 16 x 18/8 = 36 times.

Figure 1 shows a case where there is one buffer memory BUF and one facsimile signal sending circuit FAXS, but if there are multiple BUFs and FAXS, a character code/dot matrix conversion circuit FNT is provided for each BUF and FAXS.
Although the configuration in which FNTs are provided has the advantage that the amount of data transferred to the BUF after conversion to a dot pattern by FNTs does not further increase, it has the disadvantage that it is expensive because it requires the provision of a large number of FNTs. As shown in Figure 2, it is common to adopt a configuration in which the FNT is shared. However, if the configuration shown in Figure 2 is adopted, the amount of data transferred to the buffer memory BUF after being converted into a dot pattern by the character code/dot matrix conversion circuit FNT is F.
By standardizing NT, there were many drawbacks.

(Problem of the Invention) An object of the present invention is to reduce the amount of data transferred to a buffer memory after being converted into a dot pattern by a character code/dot matrix conversion circuit.

A feature of the present invention is that the information outputted from an electronic computer and output as text to a facsimile terminal device has a considerable number of blank spaces, and the present invention converts it into a facsimile signal and sends it to the facsimile device. After reading out the contents of the buffer memory, the buffer memory is controlled so that the blank part does not need to be transferred to the buffer memory as a dot pattern by writing data of a dot pattern corresponding to the blank space into the read buffer memory.

(Structure and operation of the invention) An embodiment of the invention is shown in FIG. Further, the operation time chart is shown in FIG.

201, 202, 203, 204, 205, 2
06 and 207 are selectors, terminals S are select signals, terminals I ₀ and I ₁ are input signals, and terminal O is an output signal. The data width of I ₀ , I ₁ and O, that is, the number of bits, is not necessarily 1. Not exclusively. 101,10
Reference numeral 2 denotes a buffer memory, which is provided on two sides and used in a so-called toggle format in order to maintain continuity of facsimile signals. Terminal A of the buffer memories 101 and 102 is an address signal, terminal DI is a write data signal converted into a dot pattern, terminal D is a read data signal, and terminal W is a write signal, which are connected to selectors, respectively.
The data width of DI and D, that is, the number of bits, is not necessarily 1 and depends on the situation. A counter 301 creates an address for periodically reading the buffer memory. A latch 302 latches any of the data read out from the buffer memories 101 and 102 and converted into a dot pattern. The terminal DI of the latch 302 is an input data signal, the terminal D is an output data signal, and the terminal CK is a latch clock pulse.
It is the same as that of D of 102. Signal line 1 is a buffer memory write signal from the central control unit CPU (not shown), signal line 2 is a buffer memory address signal from the CPU, and signal line 3 is a buffer memory write signal from the central control unit CPU (not shown).
This is the buffer memory write data signal converted into a dot pattern from the CPU. signal line 4
is the output of the counter 301 already explained,
It is connected to the select terminals S of the selectors 201 to 207, and the signal line 5 is the output of the counter 301.
Selector 2 as buffer memory address signal
Connected to 02,205. The signal line 6 is a buffer memory write signal from a control circuit (not shown), and the signal line 7 is a latch 3 signal from the control circuit.
02 latch clock. The signal lines 8 and 9 are used as data to be written into the buffer memory, and are blank dot pattern data, which are all 0's in the figure.

Next, the operation will be explained based on the time charts of FIGS. 3 and 4. According to the signal line 4 which is the output of the counter 301, the buffer memories 101 and 1
02 terminals A, DI, and W are connected to signal lines 2, 3, and 1 from the central control unit CPU via selectors, respectively.
Alternatively, it is connected to the signal line 5 which is the output of the counter 301, the signal line 8 or 9, and the signal line 6 from the control circuit. It is connected to a signal line from the central control unit CPU, and data converted into a dot pattern from the central control unit is sequentially written into the buffer memory, and its operation is random. That is, when writing data converted into a dot pattern to the buffer memory, the buffer memory is
According to the random address signal given from the CPU via the signal line 2, the data given from the CPU via the signal line 3 is written when the write signal given from the CPU via the signal line 1 is input.
A time chart at this time is shown in FIG. On the other hand, when reading data from the buffer memory, the buffer memory connected to the output of the counter 301, the signal line 8 or 9, and the signal line from the control circuit is periodically read out according to the address of the output 5 of the counter 301. The data read out and converted into a dot pattern is latched in the latch 302 and then sent to the facsimile signal sending circuit FAXS (not shown) via the signal line 10. The timing chart at this time is shown in FIG. show. As shown in FIG. 4, the data converted into a dot pattern read out from the buffer memory according to the address of the signal line 5, which is the output of the counter 301, is transferred to the signal line 7.
However, the signal line 6 is latched to the latch 302 at the same address of the read buffer memory.
The data of the blank dot pattern on the signal line 8 or 9 is written by the write signal. Therefore, the contents of the buffer memory will have changed to a blank dot pattern when all the data has been read out, and at this stage the counter 30 will have changed to a blank dot pattern.
According to the signal line 4 which is the output of 1, the buffer memory is connected to the signal line from the central control unit CPU,
This is the stage where the data converted into a dot pattern is written from the CPU to the buffer memory. At this stage, as shown in Figure 5, a random address signal corresponding to the data in the character part is sent from the CPU to the buffer memory via signal line 2, and the data and write signal in the character part are sent to the buffer memory through the signal line 2. 3,1 to the buffer memory. In the buffer memory, only the character data sent from the CPU is written to the address indicated by the address signal at the timing of the write signal.

(Effect of the invention) As explained above, in the embodiment, the buffer memory is connected to the signal line from the central control unit CPU,
At the stage of writing the data converted into a dot pattern from the central control unit CPU to the buffer memory, the contents of the buffer memory are all blank dot patterns, so the central control unit CPU only has to write dot patterns for the parts where the characters are. This has the effect of reducing the amount of data transferred to the buffer memory.

In the above case, the buffer memory stores data converted into a dot pattern, but even when data is stored in character code format, writing a blank character code reduces the amount of data transferred to the buffer memory. There is an effect.

[Brief explanation of drawings]

1 and 2 are block configuration diagrams showing the application of the technology related to the present invention, FIG. 3 is a block configuration diagram of an embodiment of the present invention, FIG. 4 is a time chart explaining the operation, and FIG. 5 is a time chart showing the write operation to the buffer memory by the CPU. (Explanation of symbols), CPU...Central control unit, F
NT... Character code/dot matrix conversion circuit, BUF... Buffer memory, FAXS... Facsimile signal sending circuit, 1, 6... Write signal, 2, 5... Address signal, 3... Write data, 4... Buffer memory switching signal, 7... Latch signal, 8, 9... Write data corresponding to blank dot pattern, 10... Latched read data, 101, 102... Buffer memory, 201, 202, 203, 204, 205,
206, 207...Selector, 301...Counter, 302...Latch.

Claims (1)

[Claims] 1. A buffer memory control method in which text information is stored in a single memory in order to send text information from a CPU to a terminal device, and then the content of the memory is sequentially read out to send the text information to the terminal device. After reading the contents of the memory in order to send the text information to the terminal device, data corresponding to the blank information is written in the memory, and when the next text information is written from the CPU to the buffer memory, the text information is A buffer memory control method characterized in that the information in the blank part is not transferred to the buffer memory, but only the information in the character part is transferred and written to the buffer memory according to a random address signal specified by the CPU.