JPS59193663A - Buffer memory control system - Google Patents

Abstract

PURPOSE:To decrease the amount of transfer of data to a buffer memory by storing only the information excluding space information among document information from a CPU to a memory and writing a dot pattern only to a part having characters from the CPU. CONSTITUTION:The data converted into the dot pattern read from buffer memories 101, 102 is latched 302 by a signal line in response to an address of the signal line 5 being an output of a counter 301, and the data of the space dot pattern of signal lines 8, 9 is written in the identical address of the read buffer memory by a write signal of the signal line 6. Further, contents of the memories 101, 102 are converted all into space dot patterns in the stage when all the data are read. moreover, since the CPU has only to write the dot pattern only to the part having characters in the stage when the data converted into the dot pattern is written from the CPU to the memories 101, 102, the amount of transfer of data to the memories 101, 102 is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for outputting processing results etc. of an electronic computer to a facsimile terminal device.

(Background technology) With the spread of facsimile, facsimile terminal devices
It has come to be used not only for communication between terminals, but also for communication with, for example, a computer located at a center, that is, as an input/output device for a computer. However, while the information handled by electronic computers is in the form of codes such as JIS codes, the information handled by facsimile terminals is represented by dots or F-turns depending on the shading of the image. To communicate with the device, so-called facsimile data conversion is required to convert mutual information. Therefore, in order to output a character code output from a computer to a facsimile terminal, the character code is converted into a dot matrix, which is scanned, converted into a facsimile signal, and sent to the facsimile terminal. A block diagram at this time is shown in FIG. The n'ft character code outputted from the computer CPU is converted into a dot/gap by the character code/dot matrix conversion circuit FδNT and written into the buffer memory BUF. FAX7MI IJ signal sending circuit FAXS is buffer memory BUF
'i scan, convert it into a facsimile signal, and send it to the facsimile terminal device. At this time, after the character code/dot matrix conversion circuit 1"ONT converts the data into a dot pattern, the amount of data transferred to the buffer memory IJ BUF increases. For example, if the character code is 8 bits in total and the dot matrix configuration is 16 If (IJ)X18(kl), the amount of data transferred to the buffer memory IJ BUF is 1
6X18/8=36 times.

Figure 1 shows a case where there is one buffer memory BUF and one fan/millimeter signal sending circuit FAXS, but if there are multiple BUFs and FAXS, the configuration is such that a character code/dot matrix conversion circuit FONT is provided for each BUF and FAXS.
FONT has the advantage that the amount of data transferred to BUF after conversion does not increase further.
Since it is necessary to provide a large number of FONTs, there is a disadvantage that the FONTs are expensive, and generally a configuration in which FONTs are shared as shown in FIG. 2 is adopted. However, if the configuration shown in Figure 2 is adopted, the character code/dot matrix conversion circuit F (
Buffer candy after conversion to dot pattern by 5NT K
= There was a drawback that the amount of data transferred to the IJ BUF increased significantly due to the common FONT.

(Problem of the Invention) An object of the present invention is to reduce the amount of data transferred to the buffer memory after conversion into dots and turns by a character code/dot matrix conversion circuit.

The feature of the present invention is to focus on the fact that there are many blank parts in the bulletin that is output from an electronic computer and output as text to a facsimile terminal device, and converts it into a facsimile signal and sends it to the facsimile machine. After reading the contents of the buffer memory for transmission, the data of the dots and turns corresponding to the blank spaces are written into the read buffer memory, and the blank parts are transferred to the buffer memory as dots and turns. The purpose is to control balancer memory so that it is not necessary.

(Structure and operation of the invention) An embodiment of the invention is shown in FIG. The operation time chart is shown in FIG. 4.

201.202,203,204,205,206,2
07 is a selector, terminal S is a select signal, terminal I
O, Il are input signals, terminal O is output signal, IO+
The data width, or number of bits, of I] and O is not necessarily 1.
Not necessarily. Buffer memories 101 and 102 are provided on two sides and used in a so-called toggle format in order to maintain continuity of facsimile signals. Buffer Memo'JIOI
, terminal A of 102 is an address signal, terminal DI is a driver)
Write data signal converted to E turn, terminal D6
is the read data signal, and terminal W is the read signal.
The data width, ie, the number of bits, of 5, A, DI, and Do, which are connected to the selector, is not necessarily 1, but depends on the number of loops. 301 is a counter and buffer memo +
) Creates an address for reading periodically.

302 is a latch, and buffer memories 101 and 10
The dot pattern t read from 2 (latches any of the converted data. The terminal DI of the latte 302 is an input data signal, the terminal D6 is an output data signal, and the terminal CK
is a latch clock pulse, and the data width of DI, ])σ, that is, the number of bits, is the buffer memory IJ 101 , 1
It is the same as that of l)O of 02. Signal line 1 is a buffer memory knowledge signal from a central control unit CPU (not shown), signal line 2 is a buffer memory address signal from the CPU, and signal line 3 is a buffer memory converted into a dot pattern from the CPU. This is the write data signal. The signal line 4 is the output of the counter 301 already explained, and can be connected to the select terminals S of the selectors 201 to 207, and the signal line 5 is the output of the counter 301, and the address signal color of the buffer memory is connected to the select terminals S of the selectors 201 to 207. connected to. Signal line 6 is a buffer memory input signal from a control circuit (not shown), and signal line 7 is a latch clock for latch 302 from the control circuit. Signal lines 8 and 9 are used as data to be written into the buffer memory, and are blank dot pattern data.
In the figure, it is all O.

Next, the operation will be explained based on the time charts of FIGS. 3 and 4. Buffer memo according to signal line 4 which is the output of counter 301! J101.

Terminals A, DI, and W of 102 are connected to signal lines 2, 3.1 from the central control unit CPU via selectors, or signal lines 5, 8, or 9, which are the outputs of the counter 301, respectively.
It is connected to the signal line 6 from the control circuit. Central control device C
It is connected to the signal line from the PU, and the data converted to dots and turns from the central control unit is sequentially written into the buffer memory.The operation is random, but the output of the counter 301 and the signal line 8 or 9, the buffer memory connected to the signal line from the control circuit is read out periodically according to the address of the output 5 of the counter 301, and the data converted into a dot pattern extracted by ml is sent to the latch 3.
02, it is sent to a facsimile signal sending circuit FAXS (not shown) via the signal line 10, and a tie chart at this time is shown in FIG. As shown in FIG. 4, the data read out from the buffer memory according to the address on the signal line 5, which is the output of the counter 301, and converted into dots and patterns, is latched into the latch 302 via the signal line 7. The data of the blank dot pattern on the signal line 8-i tab 9 is written to the same address of the read buffer memory by the write signal on the signal line 6.

Therefore, the contents of the buffer memory are all blank when all data is read.

At this stage, the buffer memory is connected to the signal line from the central control unit CPU according to the signal line 4 which is the output of the counter 301.

(Effects of the Invention) As explained above, in the embodiment, the buffer memory is connected to the signal line from the central control unit CPU, and the buffer memory is connected to the signal line from the central control unit CPU.
At the stage of writing the data converted into a dot pattern from the PU to the buffer memory, the contents of the buffer memory are all blank (blank driver).Since the data is written in zP data, the central control unit CPU only has to write the dot pattern for the part where the characters are. This has the effect of reducing the amount of data transferred to the buffer memory.

In the above case, the buffer memory stores data converted into dots and patterns, but even when data is stored in character code format, the amount of data transferred to the buffer memory can be reduced by writing a blank character code. This has the effect of reducing

[Brief explanation of drawings]

Figures 1 and 2 are professional block diagrams showing the application of the technology related to the present invention, the third figure is a block diagram of an embodiment of the present invention, and Figure 4 is a time chart explaining the operation. It is. (Explanation of symbols) CPU...Central control unit, i;'oiqT-...Character code. matrix conversion circuit, BUF/buffer memory,
FAXS...Facsimile signal sending circuit, ■, 6 Write signal, 2, 5... Address signal, 3 Write data, 4... Puffer memory change signal, 7... Launch signal, 8, 9 Blank dot pattern Corresponding write data, 10...Latched read data, 10
1.102...Buffer memory, 20]. 202.203.204.205.206.207...
- Selector, 301... Counter, 302... Latch. Patent applicant Oki Electric Industry Co., Ltd. Patent application agent

Claims (1)

[Claims] In a buffer memory control method, in order to send textual information from a CPU to a terminal device, the textual information 1 is stored in a memory, and then the contents of the memory are sequentially read out to send the textual information to the terminal device. After calculating the contents of the memory in order to send text information to the terminal device, data corresponding to the blank information is written in the memory, and the CPU
A buffer memory control method characterized in that only information excluding blank information from textual information is stored in memory.