JPH0150990B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a magnetic recording and reproducing device for home use (hereinafter referred to as
This invention relates to dynamic de-emphasis circuits for improving S/N in devices such as VTRs.

In home VCRs, etc., there is a strong demand for recording on a single magnetic tape for as long as possible, so a long-time recording mode has been added in which the width of the recording track is narrower than in the standard recording mode. There are things that are.

However, as a result, the S/N deteriorates more significantly than in standard recording mode, so in long-time recording mode, in addition to the fixed emphasis applied in standard recording mode, the amount of emphasis changes depending on the input level. Many methods have been used to improve the S/N by applying so-called dynamic enhancement.

That is, dynamic emphasis is applied during long-time recording mode, and dynamic de-emphasis is applied during playback mode to improve the S/N ratio.

As a circuit for providing such dynamic de-emphasis, for example, a circuit as shown in FIG. 1 has been conventionally used.

In the figure, 1 is an input terminal, 2 is a coupling capacitor, 3 and 4 are bias resistors, 5 and 6 are collector and emitter load resistances, 7 is a transistor,
8 and 9 are capacitors and resistors for providing frequency characteristics on the emitter side, 10 and 11 are diodes serving as nonlinear elements, 12 and 13 are capacitors and resistors for providing frequency characteristics on the collector side, and 14 is an output terminal. Note that S indicates an input signal source.

Next, the operation of this circuit will be explained.

Now, if the values of resistors 6 and 9 are R ₆ and R ₉ , the capacitance of capacitor 8 is C ₈ , and the conduction resistance of diodes 10 and 11 is R _D , then the impedance Z _E on the emitter side of transistor 7 is Z _E = R ₆ {1+jωC ₈ (R ₉ +R _D )}/1+jωC ₈ (R ₆ +R ₉ +
R _D ) ω: Can be expressed as angular frequency. Therefore, when a signal is input from the base of transistor 7, the frequency characteristic of emitter current ie is ie∝1/Z _E =1+jωC ₈ (R ₆ +R ₉ +R _D )/R ₆ {1+jωC ₈
(R ₉ +R _D )} and qualitatively illustrated as b in FIG. 2.

Then, the angular frequency ω _S1 at which ie increases by 3 dB is ω _S1 = 1/C ₈ (R ₆ + R ₉ + R _D ) (1).

Furthermore, the emitter current ie in the high range can be expressed as ie∝R ₆ +R ₉ +R _D /R ₆ (R ₉ +R _D ).

Now, if the input signal level becomes sufficiently large, the diodes 10 and 11 will also become sufficiently conductive.
Its conduction resistance becomes negligible compared to _R9 .
Therefore, ie in the high range can be approximately expressed as ie∝R ₆ +R ₉ /R ₆ R ₉ .

Conversely, when the input signal level is sufficiently low, the conduction resistance of the diodes 10 and 11 becomes larger than R ₆ and R ₉ , so ie can be expressed as ie∝1/R ₆ .

Therefore, the frequency characteristics of IE when the input signal level is high and low are as shown in a and c in FIG. 2, respectively.

In addition, the impedance Z _C on the collector side of the transistor 7 is the value of the resistors 5 and 13, respectively, R ₅ and
Letting R ₁₃ and the capacitance of the capacitor 12 be C ₁₂ , it can be expressed as Z _C =R ₅ (1+jωC ₁₂ R ₁₃ )/1+jωC ₁₂ (R ₅ +R ₁₃ ). The characteristic of Z _C due to this is qualitatively illustrated as shown in FIG. 3, and the angular frequency ω _S2 at which Z _C becomes 1/√2 is ω _S2 = 1/C ₁₂ (R ₅ +R ₁₃ ).

Therefore, the overall characteristics of the circuit shown in Figure 1 are obtained by multiplying the characteristics in Figure 2 and the characteristics in Figure 3, and if ω _S2 ω _S1 , then the characteristics will be approximately as shown in Figure 4. , a characteristic is obtained in which the amount of de-emphasis increases as the input signal level decreases.

Note that the curves a, b, and c in FIG. 4 correspond to high, medium, and low input signal levels, respectively.

Therefore, by using the dynamic de-emphasis circuit shown in Figure 1,
It is possible to improve the S/N ratio in the long-time recording/playback mode of a VTR.

By the way, when designing such a dynamic de-emphasis circuit, ω _S1 and ω _S2 are usually set approximately equal. In this case, ω _S2 is determined only by the circuit constants, while ω _S1 is determined by It is not easy to determine because it also depends on the input signal level. This is because R _D in equation (1) is a function of the input signal level. For this reason, the conventional circuit described above has the disadvantage that constants must be determined while actually measuring the characteristics.

Furthermore, in the circuit described above, the diodes 10, 1
Since there are nonlinear elements such as 1, harmonic distortion occurs, but especially when the input signal level is large, the change in conduction resistance of the diode is large, resulting in a high harmonic level, which appears as it is in the output, which significantly affects the image quality. It had the disadvantage of causing interference.

Furthermore, in the circuit described above, when trying to obtain dynamic characteristics up to about -20 dB with respect to the input signal level, even if germanium diodes are used for diodes 10 and 11, a signal of approximately 2 Vpp is required as a 0 dB input. When considering the reduction of the power supply voltage, the disadvantage is that the design becomes quite difficult in terms of dynamic range.Moreover, when considering the integration of this circuit, the diodes are also made of silicon, so the rise The drawback was that it was difficult to integrate because the voltage was high and a signal of approximately 6Vpp was required at 0dB input.

FIG. 5 shows another conventional example of a dynamic de-emphasis circuit. In the figure, 15, 20, 2
1 is a resistor, 16, 17, 19 are transistors, 1
8 is a current source. In FIG. 5, elements having the same functions as those in FIG. 1 are given the same reference numerals.

This conventional circuit has a nonlinear element inserted into a negative feedback circuit, and by selecting appropriate constants, it is possible to obtain characteristics almost similar to the characteristics of the conventional circuit shown in FIG. 1 shown in FIG. It is possible to configure a dynamic de-emphasis circuit.

However, even in the conventional example shown in FIG. 5, it is necessary to generate a signal of about 0.2 Vpp at the base of the transistor 17 when inputting -20 dB for the reason mentioned above, and in that case, the signal at the output terminal 14 is
A signal of 0.2Vpp or more will be generated. Therefore, at 0dB input, a signal of 2Vpp or more is output to the output terminal 14, and when considering the reduction of the power supply voltage, there is no margin for dynamic range, making integration difficult, etc. There were flaws.

An object of the present invention is to provide a dynamic de-emphasis circuit which eliminates the drawbacks of the prior art described above, which is easy to design, easy to obtain accurate characteristics, provides a wide dynamic range and is easy to integrate. be.

To achieve this object, the present invention is characterized in that the circuit providing the time constant does not include any nonlinear elements.

Embodiments of the dynamic de-emphasis circuit according to the present invention will be described below with reference to FIGS. 6 to 12 of the drawings.

FIG. 6 is a block diagram showing the basic configuration for explaining the principle of the present invention. In the figure, 22 is a high pass filter (hereinafter referred to as HPF), 23 is a compressor, and 24 is a subtracter. Note that 1 and 2 are an input terminal and an output terminal, respectively. Next, the operation will be explained with reference to FIGS. 7 to 10.

Figure 7 shows the frequency characteristics of the HPF 22, and Figure 8 shows the input level (output level)/(input level) characteristics of the compressor 23. At this time, the characteristics of the compressor 23 are dependent on the frequency. You need to make sure that it doesn't happen. And these Figure 7,
As is clear from FIG. 8, the overall characteristics of the HPF 22 and compressor 23 are as shown in FIG. 9. 9th
In the figure, a, b, and c have high, medium, and high input levels, respectively.
It corresponds to the small size.

Therefore, when the output of the compressor 23 is adjusted to an appropriate level and subtracted from the original signal by the subtracter 24, the frequency characteristic at the output terminal 14 becomes as shown in FIG. In FIG. 10, a, b, and c correspond to high, medium, and low input signal levels, respectively.

That is, in the present invention, by adopting the block configuration shown in FIG. 6, the characteristics shown in FIG. 10 can be determined only by the time constant of the HPF 22, which is composed of only passive elements, making it easy to set the circuit constants. It is.

Furthermore, when the input signal level is high, the output of the compressor 23, which contains a lot of harmonic distortion, has a very low level compared to the input signal level, so the level of harmonic distortion in the output of the subtractor 24 is small.
When the input signal level is low, the output of the compressor 23 becomes equal to the input signal level, but in this case, the compression effect by the compressor 23 is small, and therefore the harmonic distortion is also small.

FIG. 11 shows a more specific embodiment of the present invention, 25 is a battery, 26, 30, 37, 40, 4
7, 48, 52 are transistors, 27, 41, 4
3 is a diode-connected transistor, 28,
33, 34, 36, 38, 39, 42, 44, 4
5, 49, 50, 51, 55 are resistances, 29, 3
1, 46, 53 are power currents, 32, 35 are resistances, 5
4 is an external terminal.

In this embodiment, a battery 25, transistors 26 and 30, and a diode-connected transistor 2
7. Bias circuit with current sources 29 and 31, resistor 3
3, 34, 36, and capacitor 35 in Figure 6.
HPF22, transistors 37, 40, diode-connected transistors 41, 43, current source 46,
Resistors 38, 39, 42, 44, 45, and 55 constitute a compressor 23, and transistors 47, 48, and 52, a current source 53, and resistors 49, 50, and 51 constitute a subtracter 24, respectively.

Next, the operation of this circuit will be explained.

A video signal input from input terminal 1 is supplied to the bases of transistor 37 and transistor 47 via capacitor 32 and transistor 30. On the other hand, at the base of the transistor 40,
Since the output of a low pass filter (LPF) made up of resistors 34 and 36 and a capacitor 35 is supplied, the input of the differential pair made up of transistors 37 and 40 has HPF characteristics.

Therefore, the time constant of the portion corresponding to HPF 22 in Fig. 6 is C ₃₅ (R ₃₄ + R ₃₆ ), where the values of resistors ₃₄ and ₃₆ are R 34 and R 36 and the capacitance of capacitor 35 is C ₃₅ , and the input level There is no dependency on . Its characteristics are shown in FIG.

In addition, the collector load Z _C of the transistor 37 is
The operating resistance of the diode-connected transistors 41 and 43 is R _D , and the values of the resistors 42, 44, and 45 are R ₄₂ , R ₄₄ ,
If R ₄₅ , then Z _C = R _D + R ₄₂ /2・(R ₄₄ + R ₄₅ )/R _D + R ₄₂ /2 + (R ₄₄
+R ₄₅ )...(2) It depends only on the signal level, and no frequency dependence appears.

When the signal level is high, R _D ≪ R ₄₂ , so Z _C = R ₄₂ /2・(R ₄₄ + R ₄₅ )/R ₄₂ /2 + (R ₄₄ + R ₄₅ )...
…(3) becomes.

On the other hand, when the input level decreases, Z _C is expressed by equation (2), and when the input level decreases further, the diode 41,
43 is turned off, and Z _C = R ₄₄ + R ₄₅ ...(4). Therefore, the characteristics due to this change in Z _C are the 8th
It will look like the figure.

Therefore, the characteristics of the collector of transistor 37 are as shown in FIG.

Now, the collector output of the transistor 37 is adjusted to an appropriate level by resistors 44 and 45, and then subtracted from the original video signal by a subtracter 24 consisting of a transistor 47, etc., and the characteristics at the output terminal 14 are shown in FIG. It comes to show.

Now, considering the signal level, when the signal level is high and low, the transistor 37
The collector load ratio of is R ₄₂ /2/R ₄₂ /2+(R ₄₄ +R ₄₅ )...(5) from equations (3) and (4).

On the other hand, due to the circuit configuration, the values of R ₄₂ and (R ₄₄ + R ₄₅ ) are selected to be approximately equal, so the value of equation (5) is approximately
0.33, and even when the input signal level is high, the signal level appearing at the collector of the transistor 37 is not so large, and diodes made of silicon transistors can be used as the diodes 41 and 43, making it extremely easy to integrate the circuit. become.

Furthermore, in addition to the input/output terminals 1 and 14, only the external terminal 54 for connecting the filter is required as external terminals, and since a differential amplifier can be used, the output DC potential is stabilized. It can be said that it is highly suitable for

Note that the HPF 22 can also be inserted between the compressor 23 and the subtracter 24.

Further, according to this embodiment, switching between use and non-use of the dynamic de-emphasis is performed by the resistors 34 and 36 and the capacitor 35 shown in FIG.
This can be easily done by simply inserting and removing the LPF. In other words, if the LPF consisting of the capacitor 35 and the resistor 36 is removed from the circuit, the same signal will be input to the bases of the differential pair transistors 37 and 40, so that the compressor signal will be applied from the collector of the transistor 37 to the transistor 52. The output of will be zero and therefore there will be no dynamic de-emphasis characteristic.

FIG. 12 shows an embodiment of this switching circuit portion.

In the figure, 56 is a switching transistor, 57 is a base current limiting resistor, and 58 is a switching signal input terminal. Note that elements with the same symbols as in FIG. 11 have similar functions.

Now, if the terminal 58 is set to a high potential, the transistor 56 is turned on, and the dynamic de-emphasis characteristic can be obtained as shown in FIG. 11.

Furthermore, if the terminal 58 is grounded, the transistor 56
is turned OFF, the LPF effect disappears, and the dynamic de-emphasis characteristic also disappears.

As is clear from this embodiment, even when integrated, switching can be performed using one transistor and one resistor without requiring any increase in the number of IC pins.

As explained above, according to the dynamic de-emphasis circuit of the present invention, the time constant can be determined only by passive elements.

2. Low harmonic distortion when inputting large signals, and little deterioration in image quality.

3. Since the signal level is small, there is plenty of dynamic range, and it is advantageous for power saving by lowering the power supply voltage.

4 When integrating, the external terminals are 1 except for input and output.
Only a pin is required, and the peripheral components are one resistor and one capacitor.
It is suitable for integration because it can be configured in individual pieces.

5. When integration is assumed, it is easy to switch whether or not to provide dynamic de-emphasis characteristics.

It is possible to achieve the following effects, and to provide a dynamic de-emphasis circuit with excellent characteristics while eliminating the drawbacks of the prior art.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional example of a dynamic de-emphasis circuit, Figs. 2, 3, and 4 are characteristic diagrams for explaining its operation, and Fig. 5 similarly shows another conventional example. The circuit diagram, FIG. 6, is a block diagram showing the basic configuration for explaining the principle of the dynamic de-emphasis circuit according to the present invention, and FIGS.
9 and 10 are characteristic diagrams for explaining its operation, FIG. 11 is a circuit diagram showing a more specific embodiment of the present invention, and FIG. 12 is a circuit diagram showing an embodiment of the switching circuit. It is a diagram. 1...Input terminal, 14...Output terminal, 22...
High pass filter, 23...compressor, 24...subtractor.

Claims (1)

[Claims] 1. A first and a second transistor, a circuit means for interconnecting the emitters of the first and second transistors, a video signal input terminal, and a circuit means for connecting the emitters of the first and second transistors to each other, a video signal input terminal, and a circuit means for connecting the emitters of the first and second transistors to each other; a low pass filter element connected between the input terminal and the base of the second transistor, a resistor connected between the collectors of the first and second transistors and each other; A series circuit including first and second diodes connected in parallel with opposite polarities, and a subtraction circuit whose inputs are an output signal of one of the first and second transistors and a signal of the input terminal, A dynamic day emphasis circuit characterized in that it is configured to extract an output signal from the subtraction output of the subtraction circuit. 2. The dynamic de-emphasis circuit according to claim 1, wherein at least a capacitor constituting the low-pass filter element is an external element, and the entirety is integrated into an integrated circuit. 3. The dynamic de-emphasis circuit according to claim 1 or 2, further comprising a transistor switch element for switching between activation and deactivation of the low-pass filter element.