JPH0147892B2 - - Google Patents

Info

Publication number
JPH0147892B2
JPH0147892B2 JP55104122A JP10412280A JPH0147892B2 JP H0147892 B2 JPH0147892 B2 JP H0147892B2 JP 55104122 A JP55104122 A JP 55104122A JP 10412280 A JP10412280 A JP 10412280A JP H0147892 B2 JPH0147892 B2 JP H0147892B2
Authority
JP
Japan
Prior art keywords
mark
alignment
electron beam
chip
detected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55104122A
Other languages
Japanese (ja)
Other versions
JPS5728333A (en
Inventor
Takayuki Myazaki
Toshihiko Osada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10412280A priority Critical patent/JPS5728333A/en
Publication of JPS5728333A publication Critical patent/JPS5728333A/en
Publication of JPH0147892B2 publication Critical patent/JPH0147892B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/304Controlling tubes by information coming from the objects or from the beam, e.g. correction signals
    • H01J37/3045Object or beam position registration

Description

【発明の詳細な説明】 本発明は、チツプに設けた位置合わせ用マーク
を容易、迅速に検出可能とする位置合わせ用マー
クの検出方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for detecting alignment marks that allows alignment marks provided on a chip to be detected easily and quickly.

半導体ウエハ上の各チツプに電子ビーム露光で
パターンを転写する場合、該パターンとチツプま
たは該チツプに前段工程で形成されたパターンと
を高精度に位置合わせするために、予めチツプに
は位置合わせ用のマークを形成しておく。第1図
はその一例を示すもので、10はウエハ、11は
該ウエハに多数形成したチツプである。位置合わ
せ用のMKは特定形状(例えば+字状、方形な
ど)の凹部であり、通常1つのチツプ11に3〜
4個形成される。第2図はこのマークMKの検出
系の一例であり、概略的には分つているマーク
MKの近傍を電子ビームEBでXおよびY方向に
走査するとその反射電子REが反射電子検出器1
2で検出される。検出器12は図面では1個しか
示していないが実際には電子ビームを中心にその
前後左右に4個程度配置され、各出力の和が求め
られる。検出器12の出力は反射電子量に比例し
たもので、それを増幅器13で増幅した後微分回
路14で微分するとマークMKの前、後縁に対応
した正負の微分波形DIFが得られる。15は微分
波形DIFの各ピークの振幅および走査開始点から
の時間をデイジタル量に変換するA/D変換器で
あり、その出力はメモリ16に格納される。17
はメモリ16に記憶された各ピークの振幅、各ピ
ークの発生タイミングからマークMKを検知し、
かつその中心位置を算出するCPUであり、その
処理方法の一例を第3図で説明する。
When transferring a pattern to each chip on a semiconductor wafer by electron beam exposure, in order to precisely align the pattern with the chip or the pattern formed on the chip in the previous step, the chip is coated with an alignment material in advance. Form a mark. FIG. 1 shows an example, in which 10 is a wafer and 11 is a large number of chips formed on the wafer. The MK for positioning is a concave part with a specific shape (for example, + shape, square, etc.), and there are usually 3 to 3 on one chip 11.
Four pieces are formed. Figure 2 shows an example of the detection system for this mark MK, and schematically shows the separate marks.
When the electron beam EB scans the vicinity of MK in the X and Y directions, the backscattered electrons RE are detected by the backscattered electron detector 1.
Detected at 2. Although only one detector 12 is shown in the drawing, in reality, about four detectors 12 are arranged around the electron beam at the front, back, left and right sides of the electron beam, and the sum of each output is determined. The output of the detector 12 is proportional to the amount of reflected electrons, and when it is amplified by an amplifier 13 and then differentiated by a differentiating circuit 14, positive and negative differential waveforms DIF corresponding to the front and rear edges of the mark MK are obtained. Reference numeral 15 denotes an A/D converter that converts the amplitude of each peak of the differential waveform DIF and the time from the scanning start point into digital quantities, and its output is stored in the memory 16. 17
detects the mark MK from the amplitude of each peak stored in the memory 16 and the timing of occurrence of each peak,
This is a CPU that calculates the center position, and an example of its processing method will be explained with reference to FIG.

第3図aに示すように電子ビームEBでマーク
MKの存在予定地を含む一定範囲が走査される
と、微分回路14からはそれに対応する微分波形
DIFが出力されメモリ16に記憶されるので、そ
の後CPU17は先ずメモリ16の内容を全て検
索して最大値を検出する。最大値L1が検出さ
れるとこれはマークMKの前縁位置を示してい
る。次に再度メモリ16内を全て検索して最小
値を検出する。最小値S1が求まるとこれはマーク
MKの後縁位置を示している。最大値L1と最小値
S1の間隔がマーク幅である。かゝる操作をX,Y
方向について行い、位置合わせの基準点をX,Y
方向のマーク巾の中心点とする。そしてこの解析
結果で検出されたマークMKの中心と、電子ビー
ム露光すべきチツプの予定位置とがずれている場
合には、その差に応じてステージ移動系またはビ
ーム偏向系を修正した後露光する。この位置合わ
せはチツプ毎に行う。
Marked with electron beam EB as shown in Figure 3a.
When a certain range including the expected location of MK is scanned, the differential circuit 14 outputs a differential waveform corresponding to the area.
Since the DIF is output and stored in the memory 16, the CPU 17 first searches all the contents of the memory 16 and detects the maximum value. If the maximum value L 1 is detected, this indicates the leading edge position of the mark MK. Next, the entire memory 16 is searched again to detect the minimum value. If the minimum value S 1 is found, this is a mark
The trailing edge position of MK is shown. Maximum value L 1 and minimum value
The interval S1 is the mark width. Perform such operations as X and Y.
direction, and set the reference points for alignment to X and Y.
The center point of the direction mark width. If the center of the mark MK detected as a result of this analysis deviates from the planned position of the chip to be exposed with the electron beam, the stage movement system or beam deflection system is corrected according to the difference before exposure is performed. . This alignment is performed for each chip.

ところで、上述した従来の位置合わせ用マーク
検出方法には次の欠点がある。(1)第3図aのよう
にマークMKを検出するためにCPU17でメモリ
16を2回()検索しなければならず、解析
時間が長くなる。(2)最大値と最小値を組としてマ
ークMKを検出するため、第3図bのようにマー
クMKの近傍にパターンP1,P2があるとそれらの
最大値L2および最小値S0,S2も微分波形DIFに現
われるので、この様な場合にはマークMKの検出
が不可能となる。このため通常は巾15μm程度の
マークMKの周囲30μm程度の範囲はパターン形
成禁止領域とするので、その分集積度が低下す
る。
However, the conventional alignment mark detection method described above has the following drawbacks. (1) As shown in FIG. 3a, in order to detect the mark MK, the CPU 17 must search the memory 16 twice ( ), which increases the analysis time. (2) Since the mark MK is detected using the maximum value and minimum value as a set, if there are patterns P 1 and P 2 near the mark MK as shown in Figure 3b, their maximum value L 2 and minimum value S 0 , S 2 also appear in the differential waveform DIF, so in such a case it is impossible to detect the mark MK. For this reason, a region of about 30 μm around the mark MK having a width of about 15 μm is usually set as a pattern formation prohibited region, and the degree of integration is reduced accordingly.

本発明は、これらの点を解決するためになされ
たもので、その特徴とするところはウエハのチツ
プ表面に形成された位置合わせ用マークを電子ビ
ームで走査してその反射電子から該マークひいて
はチツプの正確な位置を検出する位置合わせ用マ
ークの検出方法において、予め該ウエハの適所に
位置合わせ用マークの1つを形成しておき、それ
を電子ビームで走査してマーク幅を実測し、以後
の位置合わせ時には、位置合わせマークの存在予
定地を電子ビームで走査して該位置合わせマーク
の一端を検知し、次いで該一端より前記マーク幅
だけ離れた位置近傍を電子ビームで走査して該位
置合わせマークの他端を検出し、こうしてチツプ
の位置合わせ用マークを検出する点にある。以下
図示の実施例を参照しながらこれを詳細に説明す
る。
The present invention was made to solve these problems, and its feature is that alignment marks formed on the chip surface of a wafer are scanned with an electron beam, and the reflected electrons are used to scan the alignment marks and the chips. In the alignment mark detection method for detecting the accurate position of the wafer, one of the alignment marks is formed in advance at a suitable location on the wafer, and the width of the mark is actually measured by scanning it with an electron beam. When aligning, an electron beam is used to scan the expected position of the alignment mark to detect one end of the alignment mark, and then an electron beam is used to scan a position in the vicinity of the mark width apart from the one end to detect the position. The point is to detect the other end of the alignment mark and thus detect the alignment mark on the chip. This will be explained in detail below with reference to the illustrated embodiments.

本発明ではウエハ10の適所例えばチツプが形
成されないウエハ周辺にマーク検出用のマーク
MDを設けておく。これは該ウエハ上のチツプに
設ける位置合わせ用のマークMKと同じ形状、寸
法のものであり、該マークMKと同じ工程で作
る。そして位置合わせに際しては先ずこのマーク
検出用のマークMDを前記の要領で検出し、マー
ク幅MWを読み取つておく。マーク幅は例えば前
述のように15μmと定められているが、ウエハに
よつては、また該ウエハに施す各工程においては
マークサイズを前記の15μmとは異なる他のサイ
ズ例えば3〜5μmなどにすることも多い。また過
剰露光してしまつてマークサイズが予定値から変
つてしまうことも稀ではない。従つてマーク検出
用マークMD、つまりチツプの位置合わせマーク
のサンプルを実測してその正確なサイズを知るこ
とは有効である。こうしてマークサイズを知れ
ば、チツプの位置合わせマークの検出は極めて容
易になる。これは次に説明する。
In the present invention, a mark detection mark is placed at a suitable location on the wafer 10, for example, around the wafer where no chips are formed.
Set up an MD. This has the same shape and dimensions as the alignment mark MK provided on the chip on the wafer, and is made in the same process as the mark MK. When aligning, first detect the mark MD for mark detection in the manner described above, and read the mark width MW. For example, the mark width is determined to be 15 μm as mentioned above, but depending on the wafer and in each process performed on the wafer, the mark size may be set to a different size from the above-mentioned 15 μm, such as 3 to 5 μm. Often. Furthermore, it is not uncommon for the mark size to change from the intended value due to overexposure. Therefore, it is effective to actually measure a sample of the mark detection mark MD, that is, the chip alignment mark, and find out its exact size. Knowing the mark size in this way makes it extremely easy to detect the alignment marks on the chip. This will be explained next.

第4図は本発明の一実施例の説明図で、第3図
と同一部分には同一符号が付してある。本例でも
第2図の検出系を利用するが、CPU17の処理
が第3図と異なる。つまり、第4図aに示すよう
にCPU17の1回目の検索で最大値L1を検出
したら、2回目の検索はL1からマーク幅MW
隔てた一部分だけについて行なう。このようにす
れば最小値S1の検出が容易、迅速になる。また
CPU17の解析時間も短縮される。しかも、最
大値からMW隔てた位置でしか検索をしなけれ
ば第4図bのように最小値S0,S2は検出されない
ので、パターンP1,P2をマークMKと誤認識する
ことはない。従つて、マークMKの近傍にまでパ
ターンを形成できるので、位置合わせの信頼性を
低下させることなく集積度を向上させ得る。
FIG. 4 is an explanatory diagram of one embodiment of the present invention, and the same parts as in FIG. 3 are given the same reference numerals. The detection system shown in FIG. 2 is also used in this example, but the processing of the CPU 17 is different from that shown in FIG. 3. In other words, as shown in FIG .
Do this only on the isolated part. In this way, the minimum value S 1 can be easily and quickly detected. Also
The analysis time of the CPU 17 is also shortened. Moreover, if the search is performed only at positions separated by MW from the maximum value, the minimum values S 0 and S 2 will not be detected as shown in Figure 4b, so it is impossible to mistakenly recognize the patterns P 1 and P 2 as marks MK. do not have. Therefore, since a pattern can be formed even close to the mark MK, the degree of integration can be improved without reducing the reliability of alignment.

以上述べたように本発明によれば、電子ビーム
露光における位置合わせの信頼性を低下させずに
高集積化を可能とし、且つCPUによる解析時間
を短縮できる利点がある。
As described above, according to the present invention, there is an advantage that high integration is possible without reducing the reliability of alignment in electron beam exposure, and analysis time by the CPU can be shortened.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は位置合わせ用マークの説明図、第2図
は該マークの検出系を示す概略構成図、第3図は
従来の位置合わせマーク検出方法の説明図、第4
図は本発明の一実施例の説明図である。 図中、10はウエハ、MKは位置合わせ用マー
ク、EBは電子ビーム、MWはマークサイズであ
る。
Fig. 1 is an explanatory diagram of the alignment mark, Fig. 2 is a schematic configuration diagram showing the detection system of the mark, Fig. 3 is an explanatory diagram of the conventional alignment mark detection method, and Fig. 4 is an explanatory diagram of the alignment mark detection system.
The figure is an explanatory diagram of an embodiment of the present invention. In the figure, 10 is the wafer, MK is the alignment mark, EB is the electron beam, and MW is the mark size.

Claims (1)

【特許請求の範囲】[Claims] 1 ウエハのチツプ表面に形成された位置合わせ
用マークを電子ビームで走査してその反射電子か
ら該マークひいてはチツプの正確な位置を検出す
る位置合わせ用マークの検出方法において、予め
該ウエハの適所に位置合わせ用マークの1つを形
成しておき、それを電子ビームで走査してマーク
幅を実測し、以後の位置合わせ時には、位置合わ
せマークの存在予定地を電子ビームで走査して該
位置合わせマークの一端を検知し、次いで該一端
より前記マーク幅だけ離れた位置近傍を電子ビー
ムで走査して該位置合わせマークの他端を検出
し、こうしてチツプの位置合わせ用マークを検出
することを特徴とする、位置合わせ用マークの検
出方法。
1. In an alignment mark detection method in which an alignment mark formed on the surface of a chip of a wafer is scanned with an electron beam and the accurate position of the mark and thus of the chip is detected from the reflected electrons, One of the alignment marks is formed, and the width of the mark is measured by scanning it with an electron beam. During subsequent alignments, the position where the alignment mark is expected to be is scanned with the electron beam and the alignment is performed. One end of the mark is detected, and then the other end of the alignment mark is detected by scanning an area in the vicinity of the mark width away from the one end with an electron beam, thereby detecting the alignment mark of the chip. A method for detecting alignment marks.
JP10412280A 1980-07-29 1980-07-29 Method for detecting aligning mark Granted JPS5728333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10412280A JPS5728333A (en) 1980-07-29 1980-07-29 Method for detecting aligning mark

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10412280A JPS5728333A (en) 1980-07-29 1980-07-29 Method for detecting aligning mark

Publications (2)

Publication Number Publication Date
JPS5728333A JPS5728333A (en) 1982-02-16
JPH0147892B2 true JPH0147892B2 (en) 1989-10-17

Family

ID=14372312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10412280A Granted JPS5728333A (en) 1980-07-29 1980-07-29 Method for detecting aligning mark

Country Status (1)

Country Link
JP (1) JPS5728333A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2687256B2 (en) * 1991-03-26 1997-12-08 株式会社ソルテック X-ray mask making method
JP2007136260A (en) * 2005-11-14 2007-06-07 Okamura Corp Shredder

Also Published As

Publication number Publication date
JPS5728333A (en) 1982-02-16

Similar Documents

Publication Publication Date Title
US4423959A (en) Positioning apparatus
JPS6275206A (en) Electron beam length measuring instrument
JPH0147892B2 (en)
EP0130497B1 (en) Alignment technique for a scanning beam
US4808829A (en) Mark position detection system for use in charged particle beam apparatus
JPS6352328B2 (en)
EP0538675B1 (en) Electron beam lithography method
JPH0416707A (en) Pattern recognizing method by electron beam
JP3146568B2 (en) Pattern recognition device
JPS62149127A (en) Device for charged beam exposure
JPH0210819A (en) Inspection method of pattern defect
JPH04269614A (en) Pattern-position detecting method and executing apparatus thereof
JPS6258140B2 (en)
JPH01136332A (en) Electron beam lithography method
JP2550104B2 (en) Mark position detection method
JPH02126108A (en) Length measuring instrument by electron beam
JP2903584B2 (en) Registration mark detection processing method
JPH09106945A (en) Alignment method of particle beam, irradiation method and device using the method
JP2507566B2 (en) Electronic beam measuring method and apparatus
JPH01187409A (en) Method and device for electron beam length measurement
JPS61290313A (en) Solid shape measuring apparatus
JPH03266444A (en) Detection of pattern and measurement of pattern dimension in measuring device using electron beam
JPH07120618B2 (en) Particle beam drawing method
JPH04274711A (en) Measuring method of size of pattern using charged beam
JP2003158163A (en) Method of inspecting mark, apparatus for inspecting mark, and method of manufacturing semiconductor device