JPH0145586B2 - - Google Patents

Info

Publication number
JPH0145586B2
JPH0145586B2 JP56048733A JP4873381A JPH0145586B2 JP H0145586 B2 JPH0145586 B2 JP H0145586B2 JP 56048733 A JP56048733 A JP 56048733A JP 4873381 A JP4873381 A JP 4873381A JP H0145586 B2 JPH0145586 B2 JP H0145586B2
Authority
JP
Japan
Prior art keywords
signal
period
output
channel
repeated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56048733A
Other languages
Japanese (ja)
Other versions
JPS57161662A (en
Inventor
Tsutomu Hashizume
Kenji Enohara
Kozo Ooba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Zosen Corp
Original Assignee
Hitachi Zosen Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Zosen Corp filed Critical Hitachi Zosen Corp
Priority to JP4873381A priority Critical patent/JPS57161662A/en
Publication of JPS57161662A publication Critical patent/JPS57161662A/en
Publication of JPH0145586B2 publication Critical patent/JPH0145586B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/005Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing phase or frequency of 2 mutually independent oscillations in demodulators)

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)

Description

【発明の詳細な説明】 この発明は、複数の測定対象の周期的な機械運
動で同時に発生した周期的なくり返し信号それぞ
れの固有成分のみを適確に抽出するようにした信
号処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing device that accurately extracts only the characteristic components of periodic repeating signals generated simultaneously due to periodic mechanical movements of a plurality of measurement objects.

歯車装置等の複数の測定対象それぞれの回転運
動や往復運動などの周期的な機械運動により同時
に発生した同一周期のくり返し信号には、周期的
な運動の固有成分とともに不規則雑音成分が含れ
る。そして、たとえば、複数の測定対象の回動運
動により発生したくり返し信号の固有成分を比較
し、各測定対象の正常、異常を判別して各測定対
象の状態を迅速かつ正確に把握することが望まれ
ている。
Repetitive signals of the same period generated simultaneously by periodic mechanical motions such as rotational motion and reciprocating motion of a plurality of measurement objects such as gear devices include random noise components as well as the characteristic components of the periodic motions. For example, it is desirable to quickly and accurately grasp the state of each measurement object by comparing the unique components of repeated signals generated by the rotational movements of multiple measurement objects and determining whether each measurement object is normal or abnormal. It is rare.

この発明は、前記の点に留意してなされたもの
であり、つぎにこの発明を、その1実施例を示し
た図面とともに詳に説明する。
This invention has been made with the above points in mind, and will now be described in detail with reference to drawings showing one embodiment thereof.

1aは第1チヤンネルの測定対象から第2図a
に示すように、周期的なくり返し信号が入力され
る第1信号検出器であり、1bは第2チヤンネル
の測定対象から、同図bに示すように、周期的な
くり返し信号が入力される第2信号検出器であ
る。
1a is from the measurement target of the first channel to Fig. 2a
1b is the first signal detector to which the periodic repeating signal is input, and 1b is the first signal detector to which the periodic repeating signal is input from the measurement target of the second channel, as shown in FIG. It is a two-signal detector.

そして、両信号検出器1a,1bにより各チヤ
ンネルのくり返し信号が電圧信号に変換され、両
信号検出器1a,1bの出力それぞれが、帯域ろ
波器である遮断周波数可変型の第1、第2帯域フ
イルタ2a,2bそれぞれに入力され、各帯域フ
イルタ2a,2bの遮断周波数で設定された所定
の周波数範囲の信号成分のみが抽出され、各帯域
フイルタ2a,2bの出力が第1、第2包絡線検
出器3a,3bそれぞれに入力され、各帯域フイ
ルタ2a,2bの出力のピーク成分のみが抽出さ
れ、両包絡線検出器3a,3bの出力がマルチプ
レクサ4に入力される。
Then, the repeated signals of each channel are converted into voltage signals by both signal detectors 1a and 1b, and the outputs of both signal detectors 1a and 1b are transmitted to the first and second filters of variable cut-off frequency type, which are bandpass filters. The signal components are input to each of the band filters 2a and 2b, and only signal components in a predetermined frequency range set by the cutoff frequency of each band filter 2a and 2b are extracted, and the output of each band filter 2a and 2b is the first and second envelope. The signal is input to each of the line detectors 3a and 3b, and only the peak component of the output of each band filter 2a and 2b is extracted, and the output of both envelope detectors 3a and 3b is input to the multiplexer 4.

一方、くり返し信号の周期が周期検出器5によ
り検出され、周期検出器5が第2図cに示すよう
に、くり返し信号の各周期の最初にトリガパルス
を発生し、周期検出器5のトリガパルスがタイミ
ング制御信号としてマイクロコンピユータ6に入
力される。さらに、操作パネル7の操作により、
マルチプレクサ4から出力されるくり返し信号の
サンプリング周期が予じめ単位時間間隔Tとして
設定され、操作パネル7からマイクロコンピユー
タ6にサンプリング周期設定信号が入力される。
なお、各帯域フイルタ2a,2bおよび各包絡線
検出器3a,3bの遮断周波数は、マイクロコン
ピユータ6により固有成分の抽出に有効な周波数
範囲になるように設定される。
On the other hand, the period of the repeated signal is detected by the period detector 5, and the period detector 5 generates a trigger pulse at the beginning of each period of the repeated signal, as shown in FIG. is input to the microcomputer 6 as a timing control signal. Furthermore, by operating the operation panel 7,
The sampling period of the repetitive signal output from the multiplexer 4 is set in advance as a unit time interval T, and a sampling period setting signal is inputted from the operation panel 7 to the microcomputer 6.
Note that the cutoff frequencies of each band filter 2a, 2b and each envelope detector 3a, 3b are set by the microcomputer 6 so as to fall within a frequency range effective for extracting the eigencomponent.

そして、各チヤンネルのくり返し信号は1周期
毎に出力順を逆にしてマルチプレクサ4から時間
間隔Tで交互に出力され、その出力タイミングは
第2図cのt1時、t2時、…t6時、t1′時、t2′時、
…、t1″時、t2″時、…になる。
Then, the repeated signals of each channel are outputted alternately from the multiplexer 4 at time intervals T by reversing the output order every cycle, and the output timings are t1, t2, ... t6, t1 in Fig. 2c. ′ time, t2′ time,
…, at t1″, at t2″, and so on.

また、サンプル・ホールド回路8が時間間隔T
でサンプル・ホールドをくり返し、第1信号検出
器1aに入力された第1チヤンネルのくり返し信
号が、同図dに示すように、N番目の1周期に
は、t1時、t3時、t5時…の2T時間の間隔でサンプ
リングされ、N+1番目の1周期にはN番目の1
周期のサンプリング開始よりT時間遅れたt2′時、
t4′時、t6′時…の2T時間の間隔でサンプリングさ
れ、N+1番目の1周期には、N番目の1周期の
間と同様に、t1″時、t3″時、t5″時…の2T時間の
間隔でサンプリングされ、第2信号検出器1bに
入力された第2チヤンネルのくり返し信号が、同
図eに示すように、N番目の1周期には、t2時、
t4時、t6時…の2T時間の間隔でサンプリングさ
れ、N+1番目の1周期の間には、N番目の1周
期のサンプリング開始よりT時間早いt1′時、
t3′時、t5′時…の2T時間の間隔でサンプリングさ
れ、N+2番目の1周期には、N番目の1周期の
間と同様に、t2″時、t4″時、t6″時…の2T時間の
間隔でサンプリングされる。なお、t1時、t1′時、
t1″時は、くり返し信号の各1周期の開始時刻そ
れぞれを示す。
Also, the sample-and-hold circuit 8 has a time interval T
As shown in d of the same figure, the repeated signal of the first channel inputted to the first signal detector 1a by repeating sample and hold at t1, t3, t5... is sampled at an interval of 2T time, and in one period of N+1, the Nth 1
At time t2', which is T time behind the start of period sampling,
It is sampled at 2T time intervals at t4', t6', etc., and in the N+1st period, 2T at t1'', t3'', t5'', etc. is sampled in the N+1 period. As shown in FIG.
Samples are taken at time intervals of 2T at time t4, time t6, etc., and during the N+1st cycle, at time t1', which is T time earlier than the start of sampling for the Nth cycle,
It is sampled at 2T time intervals at t3', t5', etc., and in the N+2 period, 2T at t2'', t4'', t6'', etc. is sampled in the N+2 period. It is sampled at time intervals.In addition, at t1, t1′,
Time t1'' indicates the start time of each cycle of the repeated signal.

したがつて、各信号検出器1a,1bの出力が
同一サンプリング間隔で交互にサンプリングさ
れ、サンプル・ホールド回路8の出力がA/D変
換器9によりデジタル信号に変換されてマイクロ
コンピユータ6に入力され、各チヤンネルにおけ
る各周期のサンプリング開始時刻から同一時間経
過後のデジタル信号、たとえば、t1時、t1′時、
t1″時…のデジタル信号が、マイクロコンピユー
タ6の所定メモリ領域に格納され、格納された各
所定メモリ領域のデジタル信号のチヤンネル別の
平均が求められる。
Therefore, the outputs of the signal detectors 1a and 1b are sampled alternately at the same sampling interval, and the output of the sample-and-hold circuit 8 is converted into a digital signal by the A/D converter 9 and input to the microcomputer 6. , digital signals after the same time has elapsed from the sampling start time of each period in each channel, for example, at t1, t1′,
The digital signal at time t1'' is stored in a predetermined memory area of the microcomputer 6, and the average of the stored digital signals in each predetermined memory area for each channel is determined.

そして、くり返し信号の周期を多くすることに
より、各チヤンネル毎のくり返し信号がT時間間
隔でサンプリングされ、そのチヤンネル別の出力
が重ね合わせて平均されるため、各チヤンネルの
くり返し信号の不規則雑音成分が除去され、マイ
クロコンピユータ6から出力器10に、各チヤン
ネル毎のくり返し信号の重ね合わせ平均による固
有成分のみを有する信号が同時に出力される。
By increasing the period of the repetitive signal, the repetitive signal of each channel is sampled at T time intervals, and the outputs of each channel are superimposed and averaged, so that irregular noise components of the repetitive signal of each channel are generated. are removed, and the microcomputer 6 simultaneously outputs to the output device 10 a signal having only the characteristic component resulting from the superimposed average of the repeated signals for each channel.

また、各信号検出器1a,1bの出力それぞれ
が、自乗回路11a,11bに入力され、各信号
検出器1a,1bにより自乗された各チヤンネル
のくり返し信号が、マルチプレクサ4、サンプ
ル・ホールド回路8、A/D変換器9を介してマ
イクロコンピユータ6に入力され、各くり返し信
号の固有成分および不規則雑音成分を含む全周波
数成分が自乗平均され、いわゆる全周波数のパワ
ーが求められる。さらに、マイクロコンピユータ
6から出力器10への出力信号により各チヤンネ
ルにおけるくり返し信号の固有成分のみのパワー
も求められる。
Further, the outputs of the signal detectors 1a and 1b are respectively input to the square circuits 11a and 11b, and the repeated signals of each channel squared by the signal detectors 1a and 1b are sent to the multiplexer 4, the sample/hold circuit 8, The signal is inputted to the microcomputer 6 via the A/D converter 9, and all frequency components including the characteristic components and irregular noise components of each repetition signal are root-mean-squared to obtain the so-called power of all frequencies. Furthermore, the power of only the unique component of the repeated signal in each channel is determined from the output signal from the microcomputer 6 to the output device 10.

したがつて、前記実施例によると、同時に発生
した各チヤンネルのくり返し信号の固有成分を適
確に抽出することができるとともに、各チヤンネ
ルの全周波数成分のパワーおよび固有成分のパワ
ーを求めることができ、たとえば、各測定対象の
異常状態を迅速かつ正確に検知することができ
る。
Therefore, according to the embodiment, it is possible to accurately extract the eigencomponents of the repeated signals of each channel that occur simultaneously, and it is also possible to obtain the power of all frequency components and the power of the eigencomponents of each channel. For example, abnormal states of each measurement target can be detected quickly and accurately.

なお、前記実施例では測定対策を2個にした
が、測定対象の数を増加させることは容易であ
る。
Note that in the above embodiment, the number of measurement targets is two, but it is easy to increase the number of measurement targets.

以上のように、この発明は、複数の測定対象の
周期的な機械運動で同時に発生した各チヤンネル
の同一周期のくり返し信号が入力される複数個の
信号検出器と、 該各信号検出器の出力の所定の周波数範囲の信
号成分のみを通過させる遮断周波数可変型の複数
個の帯域フイルタと、 該各帯域フイルタの出力が入力される複数個の
包絡線検出器と、 該各包絡線検出器の出力を前記くり返し信号の
各1周期に単位時間間隔毎に切換えて出力するマ
ルチプレクサと、 該マルチプレクサの出力を前記単位時間間隔で
サンプル・ホールドするサンプル・ホールド回路
と、 該サンプル・ホールド回路のホールド出力のデ
ジタル信号を出力するA/D変換器と、 前記くり返し信号の周期を検出する周期検出器
と、 前記各帯域フイルタの遮断周波数を設定すると
ともに前記周期検出器の検出信号のタイミング制
御により前記デジタル信号をチヤンネル別に重ね
合わせて平均し、各チヤンネルの前記くり返し信
号の固有成分を抽出するコンピユータと を備えた信号処理装置を提供するものである。
As described above, the present invention includes a plurality of signal detectors into which repetitive signals of the same period of each channel generated simultaneously due to periodic mechanical motion of a plurality of measurement objects are input, and an output of each of the signal detectors. a plurality of variable cutoff frequency bandpass filters that pass only signal components in a predetermined frequency range; a plurality of envelope detectors into which the output of each of the bandpass filters is input; and a plurality of envelope detectors of each of the envelope detectors. a multiplexer that switches and outputs the output at each unit time interval for each period of the repeated signal; a sample-and-hold circuit that samples and holds the output of the multiplexer at the unit time interval; and a hold output of the sample-and-hold circuit. an A/D converter that outputs a digital signal; a period detector that detects the period of the repetitive signal; and a period detector that sets a cutoff frequency of each of the band filters and controls the timing of the detection signal of the period detector to detect the period of the repetitive signal. The present invention provides a signal processing device comprising a computer that superimposes and averages signals for each channel and extracts the characteristic component of the repeated signal of each channel.

したがつて、同時に発生した各チヤンネルの周
期的なくり返し信号の順次のサンプル・ホールド
がくり返し信号の各1周期にくり返えされ、その
結果のデジタル信号がチヤンネル別に重ね合わせ
て平均され、各チヤンネルのくり返し信号から不
規則雑音成分が除去され、各チヤンネルのくり返
し信号の固有成分が同時に抽出される。
Therefore, the sequential sample and hold of the periodically repeated signals of each channel occurring simultaneously is repeated for each period of the repeated signal, and the resulting digital signals are superimposed and averaged for each channel. Irregular noise components are removed from the repeated signals, and unique components of the repeated signals of each channel are simultaneously extracted.

そのため、歯車装置等の複数の被測定対象の機
械運動で同時に発生した周期的な各信号の固有成
分を迅速かつ適確に抽出することができ、たとえ
ば、抽出した固有成分を比較して各測定対象の状
態を迅速かつ正確に把握することができる。
Therefore, it is possible to quickly and accurately extract the characteristic components of each periodic signal that occurs simultaneously in the mechanical motion of multiple objects to be measured, such as gear devices. The state of the object can be grasped quickly and accurately.

【図面の簡単な説明】[Brief explanation of drawings]

図面はこの発明の信号処理装置の1実施例を示
し、第1図はブロツク図、第2図a,bは各チヤ
ンネルのくり返し信号の波形図、同図cは周期検
出器の出力信号の波形図、同図d,eは各チヤン
ネル毎のサンプリングのタイミング説明図であ
る。 1a,1b……第1、第2信号検出器、2a,
2b……第1、第2帯域フイルタ、3a,3b…
…第1、第2包絡線検出器、4……マルチプレク
サ、5……周期検出器、6……マイクロコンピユ
ータ、8……サンプル・ホールド回路、9……
A/D変換器。
The drawings show one embodiment of the signal processing device of the present invention, in which FIG. 1 is a block diagram, FIG. 2 a and b are waveform diagrams of repeated signals of each channel, and FIG. 1, d and e are explanatory diagrams of sampling timing for each channel. 1a, 1b...first and second signal detectors, 2a,
2b...first and second band filters, 3a, 3b...
...First and second envelope detectors, 4...Multiplexer, 5...Period detector, 6...Microcomputer, 8...Sample and hold circuit, 9...
A/D converter.

Claims (1)

【特許請求の範囲】 1 複数の測定対象の周期的な機械運動で同時に
発生した各チヤンネルの同一周期のくり返し信号
が入力される複数個の信号検出器と、 該各信号検出器の出力の所定の周波数範囲の信
号成分のみを通過させる遮断周波数可変型の複数
個の帯域フイルタと、 該各帯域フイルタの出力が入力される複数個の
包絡線検出器と、 該各包絡線検出器の出力を前記くり返し信号の
各1周期に単位時間間隔毎に切換えて出力するマ
ルチプレクサと、 該マルチプレクサの出力を前記単位時間間隔で
サンプル・ホールドするサンプル・ホールド回路
と、 該サンプル・ホールド回路のホールド出力のデ
ジタル信号を出力するA/D変換器と、 前記くり返し信号の周期を検出する周期検出器
と、 前記各帯域フイルタの遮断周波数を設定すると
ともに前記周期検出器の検出信号のタイミング制
御により前記デジタル信号をチヤンネル別に重ね
合わせて平均し、各チヤンネルの前記くり返し信
号の固有成分を抽出するコンピユータと を備えたことを特徴とする信号処理装置。
[Claims] 1. A plurality of signal detectors into which repeated signals of the same period of each channel generated simultaneously by periodic mechanical motion of a plurality of measurement objects are input, and a predetermined output of each of the signal detectors. a plurality of variable-cutoff frequency bandpass filters that pass only signal components in a frequency range of; a plurality of envelope detectors into which the outputs of each of the bandpass filters are input; and an output of each of the envelope detectors. a multiplexer that switches and outputs the output at each unit time interval for each cycle of the repeated signal; a sample-and-hold circuit that samples and holds the output of the multiplexer at the unit time interval; and a digital hold output of the sample-and-hold circuit. an A/D converter that outputs a signal; a period detector that detects the period of the repeated signal; and a period detector that sets the cutoff frequency of each of the band filters and controls the timing of the detection signal of the period detector to detect the digital signal. A signal processing device comprising: a computer that superimposes and averages each channel, and extracts the characteristic component of the repeated signal of each channel.
JP4873381A 1981-03-31 1981-03-31 Signal processor Granted JPS57161662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4873381A JPS57161662A (en) 1981-03-31 1981-03-31 Signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4873381A JPS57161662A (en) 1981-03-31 1981-03-31 Signal processor

Publications (2)

Publication Number Publication Date
JPS57161662A JPS57161662A (en) 1982-10-05
JPH0145586B2 true JPH0145586B2 (en) 1989-10-04

Family

ID=12811484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4873381A Granted JPS57161662A (en) 1981-03-31 1981-03-31 Signal processor

Country Status (1)

Country Link
JP (1) JPS57161662A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6182174A (en) * 1984-03-26 1986-04-25 Otani Denki Kk Peak detecting device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6128253Y2 (en) * 1978-11-02 1986-08-22

Also Published As

Publication number Publication date
JPS57161662A (en) 1982-10-05

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