JPH0145251B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a control circuit that delays execution of a predetermined output at a specified time interval from a certain reference time, in which an adder circuit is provided on the output side of a counter for counting the reference time, and the adder circuit The time data output of the adder circuit is compared with the data output of the memory circuit in which the time to be delayed is stored, and the output of the adder circuit is operated so that the output is the original time to be delayed. The present invention is characterized in that the delay execution output control signal is adjusted to the original time at which the delay should be executed in the time correction circuit, thereby ensuring that the delay control is executed at the designated delay time without error.

Generally, in a control circuit that delays execution by a specified time interval from a certain reference time, the specified delay time is stored in, for example, a memory circuit, and the execution time to be delayed is read out from the output of the memory circuit by a series of address controls. and the output of a reference time counting counter that counts at a certain interval that can also be set arbitrarily from a certain standard time that can be arbitrarily set, and if the comparison results match. When there is a specified delay time, a predetermined output is obtained with a specified delay time.

FIG. 1 shows a conventional delay control circuit, and reference numeral 1 is a reference time counting counter. By passing the input and a clock input having a certain interval that can be set arbitrarily through an AND gate circuit 2, a counting clock CL is generated which is output only when the reference time signal TS is a "1" signal. It performs its functions by 3 is execution time data ET
This is a circuit that controls the addresses of the memory circuit 4 that stores the memory circuit 4. This circuit sequentially outputs all addresses of the memory circuit using a clock HC that has a cycle rate several times faster than the reference time counting clock, and controls the writing and writing of the memory circuit 4. This is provided for address control of reading. The specified execution time data ET is written into the memory circuit 4 according to the address designation of the address control circuit 3 which is sequentially output.
The specified execution time AT and execution data ED can be read out from the memory circuit sequentially by address designation from the address control circuit. The specified execution time data AT read from this memory circuit and the output data of the reference time counting counter described above are compared in the comparator circuit 5, and if the comparison results match, a certain arbitrary setting is made. It is determined that the specified delay time has elapsed from the reference time set, and the delay execution output control signal DS is generated, and this control signal DS
By supplying the execution data output generation circuit 6 to the execution data output generation circuit 6, a predetermined execution output EO is obtained.

For example, assume that the reference time counter 1 generates an 8-bit binary count output. The above reference time counter 1 is 00000000.
From 11111111, the reference time counting clock supplied from the AND gate circuit 2 sequentially counts up one count at a time.

On the other hand, the execution time data ET is also 8 bits like the reference time counter 1. Now, assuming that data 00111111 is given to the execution time data ET, the data is written into the memory circuit 4, read out, and input to the comparison circuit 5 as the designated execution time data AT. The reference time counter 1 performs a count-up operation as described above, and the comparator circuit 5 detects that the count value has reached the designated execution time data AT, ie, 00111111, and outputs the delayed execution output control signal DS. Occur.

Conventionally, the output data of the reference time counting counter is simply compared with the time data read from the memory circuit that stores the specified delay execution time, so the delay execution output control signal generated after the comparison is DS is delayed from the time when it should actually be executed, and this delay must be ignored or compensated for when supplying execution time data to the memory circuit, which is troublesome.
First, it can be a cause of errors in execution.

Furthermore, when attempting to obtain delayed execution outputs continuously, it goes without saying that while the execution output signal is being generated, it is impossible to perform a series of control operations for generating the next output signal, including reading the memory circuit. ,
The blank space in this time period also causes a delay with respect to the specified delay execution time, and in order to compensate for this blank space, for example, the cycle rate of the clock pulse that operates the address control circuit of the memory circuit must be made faster and faster, resulting in errors. It is also a major cause of

SUMMARY OF THE INVENTION An object of the present invention is to provide a delay execution control circuit which can eliminate such conventional drawbacks and perform error-free and stable operation with respect to delayed execution.

In this invention, the output of the reference time counting counter 1 is supplied to an adder circuit, and the adder circuit adds a certain amount of time to the reference time so that the original time to be delayed is reached. The time data output of the adder circuit and the execution time data output of the memory circuit are compared in the comparator circuit, and the execution time data read from the memory circuit is stored in, for example, a register, and executed by the delayed execution output control signal generated from the comparator circuit. In addition to obtaining data output, the timing of generation of the control signal output from the comparator circuit is corrected to the original delay execution time.

FIG. 2 shows an embodiment of the present invention. In this figure, parts common to those in FIG. 3 is an address control circuit, 4 is a memory circuit, 5 is a comparison circuit, and 6 is an execution data output generation circuit.

In this invention, an adder circuit 7, an execution time data storage register 8, and a time correction circuit 9 are provided.

That is, by adding a certain period of time to the time data output of the reference time counting counter 1 in the adding circuit 7, the original reference time to be delayed is set. The output is time data that is earlier than the original delay execution time by the time added by the adder circuit, and therefore the delay execution output control signal generated after comparison is also earlier.

In the comparison circuit, when the two data inputs to be compared match, the control signal transfers the execution time data ED ₂ stored in the register 8 to the execution data output generation circuit 6, and at the same time the control signal CO from the comparison circuit is transferred. is input to the time correction circuit 9, and the execution data output _ED1 is controlled by the delayed execution output control signal DS from the time correction circuit. During this time, the execution time data AT has already been read from the memory circuit, and the next reference time ET and execution time are being read.
I am comparing AT. Therefore, even while the execution data output EO is occurring, reading from the memory circuit is performed without any blank time that could be called a waiting state, and a series of control operations are performed to reliably control the time at which the next execution should be performed. .

FIG. 3 is a timing diagram for explaining the above operation. In the figure, since the adder circuit 7 adds 1 to the output of the reference time counter 1 and supplies it to the comparator circuit 5, the output CO of the comparator circuit 5 is
When the execution time data ET is 00111111, the output CO is generated at 00111110, which is one less than this.

Therefore, the output of execution time data storage register 8
As shown in the figure, the ED ₂ can load the data one clock before the output of the reference time counter 1 becomes 00111111, and the execution data output generation circuit 6 loads the data input in advance. Generate execution data output EO using .

As explained above, according to the present invention, the delay with respect to the time when the delay should be executed is theoretically only the error that naturally occurs due to the circuit configuration, and this value is so small that it can be completely ignored. The size can be further reduced by increasing the number of counters, etc. for matching and improving accuracy. In addition, in the case of continuous delayed execution, the memory circuit can be continued without waiting for the output signal generation time, so this time gap can also be removed, and in order to compensate for this gap, the memory circuit There is no need to increase the cycle rate of the clock pulse for address control, and therefore error-free and stable delay control can be performed.

[Brief explanation of drawings]

Figure 1 is a system diagram for explaining the conventional example;
The figure is a system diagram showing one embodiment of the present invention, and FIG. 3 is a timing diagram for explaining the operation of FIG. 2. DESCRIPTION OF SYMBOLS 1...Reference time counter, 2...AND gate circuit, 3...Address control circuit, 4...Memory circuit, 5...Comparison circuit, 6...Execution data output generation circuit, 7...Addition circuit, 8... Execution time data storage register, 9... Time correction circuit. Identical or corresponding parts in the drawings are denoted by the same reference numerals.

Claims (1)

[Claims] 1. An AND gate circuit that inputs a reference time signal and a reference time counting clock, a reference time counting counter that counts the output of the AND gate circuit, and a fixed time period for the time data output of the reference time counting counter. an adder circuit for adding data, a memory circuit for storing execution time data to be executed with a delay, and a clock having a cycle faster than the reference time counting clock to output the address of the memory circuit, and address control of writing and reading of the memory circuit. an address control circuit that compares the output from the adder circuit with the output from the memory circuit, and generates a control signal when the two match; the outputs of the memory circuit and the comparator circuit are accumulated; A register that outputs the accumulated data to the execution data output generation circuit in response to a control signal, and a control signal from the comparison circuit are inputted to correct the timing of generation of the control signal output from the comparison circuit to the original delayed execution time. and a time correction circuit that supplies the execution data to the execution data output generation circuit.