JPH0143326B2 - - Google Patents
Info
- Publication number
- JPH0143326B2 JPH0143326B2 JP57133463A JP13346382A JPH0143326B2 JP H0143326 B2 JPH0143326 B2 JP H0143326B2 JP 57133463 A JP57133463 A JP 57133463A JP 13346382 A JP13346382 A JP 13346382A JP H0143326 B2 JPH0143326 B2 JP H0143326B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- voltage
- terminal
- transistor
- ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000007423 decrease Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
- H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
- H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
- H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads
Landscapes
- Business, Economics & Management (AREA)
- Emergency Management (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Sources (AREA)
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Stand-By Power Supply Arrangements (AREA)
- Direct Current Feeding And Distribution (AREA)
Description
【発明の詳細な説明】
本発明は、停電時において必要とされるメモリ
ーバツクアツプ回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory backup circuit that is required during a power outage.
従来のメモリーバツクアツプ回路の一例を第１
図に示す。同図でRAMは動作切換端子CS及び電
源端子VDDを有するランダム・アクセス・メモリ
ーである。BATTは3Vの起電力を有するバツテ
リー、Ｄはダイオード、Q1，Q2はトランジスタ、
R1〜R3は抵抗、ZDはツエナーダイオード、Vo
は5Vの加わる電源端子である。 The first example of a conventional memory backup circuit is
As shown in the figure. In the figure, RAM is a random access memory having an operation switching terminal CS and a power supply terminal VDD . BATT is a battery with an electromotive force of 3V, D is a diode, Q 1 and Q 2 are transistors,
R 1 to R 3 are resistors, ZD is a Zener diode, Vo
is the power supply terminal to which 5V is applied.
１は定電圧回路で、定電圧出力のための第１の
出力端子２と、前記RAMの動作切替端子CSに接
続された第２の出力端子３とを有し、トランジス
タQ1，Q2ツエナーダイオードZD等により構成さ
れる。 Reference numeral 1 denotes a constant voltage circuit, which has a first output terminal 2 for constant voltage output and a second output terminal 3 connected to the operation switching terminal CS of the RAM, and includes transistors Q 1 and Q 2 Zener. Consists of diode ZD, etc.
上記構成で、常時は端子Voに加わる電源電圧
により、ツエナーダイオードZDが導通し、従つ
てトランジスタQ2がオンとなり、このため抵抗
R2を介してトランジスタQ1のベース電位が低下
してトランジスタQ1もオンとなる。さらに、プ
ルアツプ用の抵抗R1を介してメモリーRAMの動
作切替端子CSにほぼOvが印加され、メモリー
RAMは動作状態になる一方、端子Voに加わる電
源電圧がトランジスタQ1を介して、定電圧化さ
れて前記第１の出力端子２からメモリーRAMの
電源端子VDDに供給されることになる。この時ダ
イオードＤは非導通である。一方、停電により電
源電圧Voが低下すると、ツエナーダイオードZD
がオフ、従つてトランジスタQ1，Q2も共にオフ
となり、トランジスタQ1のコレクタ電圧も低下
しこのためダイオードＤが導通となりバツテリー
BATTからメモリーRAMに電圧が供給される。
しかしダイオードＤによる電圧降下が約0.7Vあ
り、このためバツテリーの使用可能な時間が短か
くなり（電源端子電圧を一定以上に確保するた
め）、停電時のメモリー保持時間が大きく取れな
い欠点があつた。 In the above configuration, the Zener diode ZD is normally conductive due to the power supply voltage applied to the terminal Vo, and therefore the transistor Q 2 is turned on, so that the resistance
The base potential of transistor Q 1 decreases via R 2 and transistor Q 1 also turns on. Furthermore, approximately Ov is applied to the operation switching terminal CS of the memory RAM via the pull-up resistor R1 , and the memory
While the RAM is in an operating state, the power supply voltage applied to the terminal Vo is made constant via the transistor Q1 , and is supplied from the first output terminal 2 to the power supply terminal VDD of the memory RAM. At this time, diode D is non-conductive. On the other hand, when the power supply voltage Vo decreases due to a power outage, the Zener diode ZD
is turned off, so transistors Q 1 and Q 2 are also turned off, and the collector voltage of transistor Q 1 also decreases, causing diode D to conduct and reduce the battery voltage.
Voltage is supplied from BATT to the memory RAM.
However, there is a voltage drop of about 0.7V due to diode D, which shortens the usable time of the battery (to ensure the power supply terminal voltage is above a certain level), and has the drawback that the memory retention time during a power outage cannot be maintained for a long time. Ta.
本発明は上記した従来の欠点を除去したもので
あつて、以下にその一実施例により図面と共に説
明する。 The present invention eliminates the above-mentioned drawbacks of the conventional art, and will be described below with reference to an embodiment thereof with reference to the drawings.
第２図において、Q3，Q4はトランジスタ、R4，
R5は抵抗、また第１図と同じ部分に同符号を付
している。 In Figure 2, Q 3 and Q 4 are transistors, R 4 ,
R5 is a resistor, and the same parts as in FIG. 1 are given the same symbols.
次にこの実施例の動作を説明する。電源電圧
Voが正常時5VのトランジスタQ1，Q2の動作は第
１図の場合と同様で、電源端子VDDに電圧が供給
される一方で、トランジスタQ2がオンになるの
で、トランジスタQ4のベース電位も抵抗R4を介
して低電位に保たれる。このためトランジスタ
Q4はオンになり、さらにトランジスタQ3のベー
ス電位が上昇してオフとなり、バツテリー
BATTと電源端子VDDは切離されたことになる。
一方、電源電圧Voが低下すると、トランジスタ
Q4がオフ、従つてトランジスタQ3は抵抗R5を通
じてオンとなりバツテリーBATTの電圧は、ト
ランジスタQ3のエミツタ・コレクタ間電圧だけ
低下してメモリRAMの電源端子VDDに供給され
る。 Next, the operation of this embodiment will be explained. Power-supply voltage
The operation of transistors Q 1 and Q 2 when Vo is 5 V when normal is the same as in Figure 1. While voltage is supplied to the power supply terminal V DD , transistor Q 2 is turned on, so transistor Q 4 is turned on. The base potential is also kept at a low potential via resistor R4 . For this reason the transistor
Q 4 turns on, and the base potential of transistor Q 3 rises to turn it off, turning off the battery.
BATT and power supply terminal V DD are now disconnected.
On the other hand, when the power supply voltage Vo decreases, the transistor
Q4 is turned off, so transistor Q3 is turned on through resistor R5 , and the voltage of battery BATT is reduced by the emitter-collector voltage of transistor Q3 and is supplied to the power supply terminal VDD of the memory RAM.
トランジスタQ3により電圧降下は抵抗R5の値
を適当に選ぶことにより0.1V程度に止めること
が出来る。 The voltage drop due to the transistor Q3 can be stopped to about 0.1V by appropriately selecting the value of the resistor R5 .
以上説明したように本発明によれば、停電時の
メモリーバツクアツプ回路としてバツテリーに直
列にダイオードを挿入した場合に比較して電圧降
下量を小さく保てる利点を有する。さらに、トラ
ンジスタ回路をバツテリーと直列に挿入したこと
により、トランジスタの種類とそのバイアス条件
を選定することにより、オフ時のコレクタ電流を
ダイオードに比較して小さくする事が可能であ
る。 As described above, the present invention has the advantage that the amount of voltage drop can be kept small compared to the case where a diode is inserted in series with a battery as a memory backup circuit during a power outage. Furthermore, by inserting a transistor circuit in series with the battery, by selecting the type of transistor and its bias conditions, it is possible to reduce the collector current when off compared to a diode.
第１図は従来のメモリーバツクアツプ回路の結
線図、第２図は本発明の一実施例によるメモリー
バツクアツプ回路結線図である。
１……定電圧電源、２……第１の出力端子、３
……第２の出力端子、RAM……メモリー、Q1，
Q2，Q3，Q4……トランジスタ、BATT……バツ
テリー、R1……抵抗、VDD……電源端子、CS…
…動作切替端子。
FIG. 1 is a wiring diagram of a conventional memory backup circuit, and FIG. 2 is a wiring diagram of a memory backup circuit according to an embodiment of the present invention. 1... Constant voltage power supply, 2... First output terminal, 3
...Second output terminal, RAM...Memory, Q 1 ,
Q 2 , Q 3 , Q 4 ... Transistor, BATT ... Battery, R 1 ... Resistor, V DD ... Power supply terminal, CS ...
...Operation switching terminal.
Claims (1)
源端子に電圧を供給するための第１の出力端子を
備えた定電圧電源と、前記定電圧電源に設けられ
前記RAMの動作切替端子と接続され正常電源電
圧時には前記動作切替端子を動作状態に、また停
電時には不動作状態に保つ電圧を出力する第２の
出力端子と、前記RAMの電源端子と、バツテリ
ーの間に挿入したトランジスタと、前記第２の出
力により前記正常電源電圧時には前記トランジス
タをオフに、また停電時にはオンに制御する制御
手段と、前記第１、第２の出力端子間に設けた抵
抗とからなるメモリーバツクアツプ回路。1. A constant voltage power supply having a first output terminal for supplying voltage to a power supply terminal of a RAM (Random Access Memory), and a normal power supply provided in the constant voltage power supply and connected to the operation switching terminal of the RAM. a second output terminal that outputs a voltage that keeps the operation switching terminal in the operating state when the voltage is on, and keeps the operation switching terminal in the non-operating state during the power outage; a transistor inserted between the power supply terminal of the RAM and the battery; A memory backup circuit comprising a control means for controlling the transistor to be turned off at the normal power supply voltage and turned on at the time of a power outage by an output, and a resistor provided between the first and second output terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57133463A JPS5924323A (en) | 1982-07-29 | 1982-07-29 | Memory backup circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57133463A JPS5924323A (en) | 1982-07-29 | 1982-07-29 | Memory backup circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5924323A JPS5924323A (en) | 1984-02-08 |
| JPH0143326B2 true JPH0143326B2 (en) | 1989-09-20 |
Family
ID=15105367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57133463A Granted JPS5924323A (en) | 1982-07-29 | 1982-07-29 | Memory backup circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5924323A (en) |
-
1982
- 1982-07-29 JP JP57133463A patent/JPS5924323A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5924323A (en) | 1984-02-08 |
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