JPH0142515B2 - - Google Patents
Info
- Publication number
- JPH0142515B2 JPH0142515B2 JP56152777A JP15277781A JPH0142515B2 JP H0142515 B2 JPH0142515 B2 JP H0142515B2 JP 56152777 A JP56152777 A JP 56152777A JP 15277781 A JP15277781 A JP 15277781A JP H0142515 B2 JPH0142515 B2 JP H0142515B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- lands
- solder lands
- short
- contribute
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910000679 solder Inorganic materials 0.000 claims description 61
- 239000011888 foil Substances 0.000 claims description 16
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 14
- 238000005476 soldering Methods 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 13
- 229910052742 iron Inorganic materials 0.000 claims description 7
- 238000007598 dipping method Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Description
【発明の詳細な説明】
本発明は導体箔の分断個所を半田で短絡するこ
とにより、予め印刷配線板に構成された電気回路
の電流値や、電気回路を構成する抵抗値等を任意
に選択するようにした印刷配線板に関するもので
ある。[Detailed Description of the Invention] [Detailed Description of the Invention] The present invention allows the current value of the electric circuit configured in advance on the printed wiring board, the resistance value of the electric circuit, etc. to be arbitrarily selected by short-circuiting the divided parts of the conductor foil with solder. The present invention relates to a printed wiring board.
一般に印刷配線板において、予め構成された電
気回路の電流値や電気回路を構成する抵抗値を任
意に選択しようとする場合、第１図及び第２図に
示すように、導体箔１，２の半田ランド４，４に
分断用のスリツト部３が設けられるのが常であ
る。そして必要時には半田ランド４，４上の半田
を用いてスリツト部３を適宜短絡するものであ
る。 Generally, when trying to arbitrarily select the current value of a preconfigured electric circuit or the resistance value constituting the electric circuit in a printed wiring board, as shown in FIGS. A slit portion 3 for dividing is usually provided in the solder lands 4,4. When necessary, the slit portion 3 is appropriately short-circuited using the solder on the solder lands 4, 4.
ところで、第１図及び第２図に示すものでは、
必要時に半田により短絡することが容易となるよ
うに、スリツト部３を曲線にしている。しかし、
この構成では半田デイツプ時の移動によりスリツ
ト部３が意志に反して短絡されてしまう問題が多
く発生した。 By the way, in what is shown in Figures 1 and 2,
The slit portion 3 is curved so that it can be easily short-circuited by soldering when necessary. but,
With this configuration, there were many problems in that the slit portion 3 was unintentionally short-circuited due to movement during solder dipping.
本発明は上述のような欠点を解消するためにな
されたもので、半田デイツプ時には確実に二つの
導体箔の半田ランド間を分断することができ、し
かも必要に応じて半田ランド間を接続して短絡さ
せる場合は、半田ごてのほかにやに入りワイヤー
半田等を添えることなく、半田ランドの近傍に位
置する半田により容易に短絡させることができる
印刷配線板を提供することを目的とするものであ
る。 The present invention has been made to eliminate the above-mentioned drawbacks, and it is possible to reliably separate the solder lands of two conductor foils during solder dipping, and to connect the solder lands as necessary. To provide a printed wiring board that can be easily short-circuited by solder located near a solder land without using a soldering iron or by adding wire solder or the like. It is.
以下、本発明の一実施例を第３図にもとづいて
説明する。 Hereinafter, one embodiment of the present invention will be described based on FIG. 3.
第３図において、１は印刷配線基板上に印刷形
成された第１の導体箔、２は上記第１の導体箔１
との間に直線状のスリツト部３をもつて印刷形成
された第２の導体箔である。 In FIG. 3, 1 is a first conductor foil printed and formed on a printed wiring board, and 2 is the first conductor foil 1.
This is a second conductor foil that is printed and formed with a linear slit portion 3 between the two conductor foils.
そして上記第１、第２の導体箔１，２で構成さ
れる半田ランド４，４は略円形に構成され、かつ
上記半田ランド４，４の近傍には部品の取付けに
寄与しない独立した半田ランド５が印刷形成され
ている。 The solder lands 4, 4 made up of the first and second conductive foils 1, 2 are approximately circular, and there are independent solder lands near the solder lands 4, 4 that do not contribute to the attachment of components. 5 is printed.
第４図は本発明の他の実施例を示したもので、
第３図の一実施例と異なるところは、第１、第２
の導体箔１，２の形状を略円形ではなく角形と
し、そしてソルダーレジストインキによつて略円
形の半田ランド４，４を構成した点であり、また
部品の取付けに寄与しない半田ランド５，５も導
体箔１，２上にそれぞれソルダーレジストインキ
によつて構成されているものである。 FIG. 4 shows another embodiment of the present invention,
The difference from the embodiment in FIG. 3 is that the first and second
The shape of the conductor foils 1 and 2 is square rather than approximately circular, and the approximately circular solder lands 4 and 4 are formed with solder resist ink, and the solder lands 5 and 5 that do not contribute to the attachment of components are formed. The conductor foils 1 and 2 are each made of solder resist ink.
第３図、第４図の実施例において、第１、第２
の導体箔１，２の半田ランド４，４間に設けた直
線状のスリツト部３は半田デイツプ時に移動する
方向とほぼ平行に設けているものであり、かつこ
の直線状のスリツト部３は、半田デイツプ時には
第１、第２の導体箔１，２に設けた半田ランド
４，４間に接続されることなく、確実に分断され
る大きさに設定しているものである。そして必要
に応じて、半田ランド４，４間を接続して短絡し
たい場合には、半田ランド４，４の近傍に位置し
て独立して設けられ、かつ部品の取付けに寄与せ
ず、矢印、数字等の意味を持つ形状とした半田ラ
ンド５に付着している半田を用いて、容易に短絡
することができる。 In the embodiments shown in FIGS. 3 and 4, the first and second
The linear slit portion 3 provided between the solder lands 4 and 4 of the conductor foils 1 and 2 is provided approximately parallel to the direction of movement during solder dipping, and this linear slit portion 3 is The size is set so that the solder lands 4, 4 provided on the first and second conductor foils 1, 2 are not connected to each other and are reliably separated during solder dipping. If necessary, if it is desired to connect and short-circuit the solder lands 4, 4, the solder lands 4, 4 can be provided independently and located near the solder lands 4, 4, and do not contribute to the mounting of the parts, and the arrows, A short circuit can be easily made using the solder attached to the solder land 5 which has a shape having a meaning such as a number.
ここで、半田ランド５は第３図のように、短絡
することによる電気回路の特性の変化を示す矢印
や、第４図のように電気回路のどの部分かを示す
数字や記号にすることにより、同一印刷配線板上
にこのような部分が複数ある場合においても、ど
こを短絡するかが明確となり、誤つて短絡するよ
うなことを防止することができる。 Here, the solder land 5 can be represented by an arrow that indicates the change in the characteristics of the electric circuit due to a short circuit as shown in Fig. 3, or by a number or symbol indicating which part of the electric circuit it is as shown in Fig. 4. Even if there are a plurality of such parts on the same printed wiring board, it becomes clear where to short-circuit, and erroneous short-circuits can be prevented.
また、短絡しようとする半田ランド４，４に付
着した半田では短絡作業において半田の量が不足
する場合があるが、従来においては、部品取付け
に寄与しない半田ランド５を設けていないため、
半田ごてのほかにやに入りワイヤー半田等を添え
る必要があつたが、実施例のものでは、短絡しよ
うとする半田ランド４，４の近傍に、部品取付け
に寄与しない半田ランド５を別個に設けているた
め、半田ランド４，４に付着した半田の量が不足
している場合においても、半田ランド５に付着し
た半田を短絡しようとする半田ランド４，４に簡
単に移動させることができ、これにより、従来の
ようにやに入りワイヤー半田等を別個に用意する
必要もなくなつて、半田ランド４，４の短絡作業
が容易に、かつ短絡の作業ミスもなく確実に行な
うことができる。 Furthermore, the amount of solder adhering to the solder lands 4, 4 to be short-circuited may be insufficient in the short-circuiting work, but conventionally, the solder lands 5, which do not contribute to component attachment, are not provided.
In addition to the soldering iron, it was necessary to attach wire solder or the like, but in the embodiment, a separate solder land 5 that does not contribute to component attachment is placed near the solder lands 4, 4 that are to be short-circuited. Because of this, even if the amount of solder attached to the solder lands 4, 4 is insufficient, the solder attached to the solder lands 5 can be easily moved to the solder lands 4, 4 where a short circuit is to be made. As a result, there is no need to separately prepare wire solder or the like as in the past, and the short-circuiting work of the solder lands 4, 4 can be easily performed and can be carried out reliably without making short-circuiting mistakes. .
以上のように本発明によれば、半田デイツプ時
には半田ランド間は接続されないが、半田ごてに
よる半田付作業時には半田ランド間を接続できる
ように、半田デイツプ時に移動する方向とほぼ平
行に設けた直線状のスリツト部により半田ランド
が分断されている二つの導体箔と、前記半田ラン
ドの近傍に位置して独立して設けられ、かつ部品
の取付けに寄与せず、表面張力により半田が盛り
上がる程度の太さの矢印、数字等の意味を持つ形
状とした半田ランドとを備えた構成としているた
め、半田デイツプ時においては、直線状のスリツ
ト部により二つの導体箔間を確実に分断すること
ができる。また同一の印刷配線板上にこのような
部分が複数ある場合においても、矢印、数字等の
意味を持つ形状とした半田ランドの存在により、
どこを短絡するかが明確となり、その結果、誤つ
て短絡するということも未然に防止することがで
きる。しかも二つの導体箔を短絡させる場合にお
いても、従来のように半田ごてのほかにやに入り
ワイヤー半田等を添えることなく、半田ランドの
近傍に位置して独立して設けられ、かつ部品の取
付けに寄与していない半田ランドに付着している
半田を用いて短絡させることができるため、その
短絡作業を容易に、かつ確実に行なうことができ
るものである。 As described above, according to the present invention, the solder lands are not connected during the soldering process, but the solder lands are provided almost parallel to the direction of movement during the soldering process so that the solder lands can be connected during the soldering work using a soldering iron. Two conductive foils with solder lands separated by linear slits, and two conductive foils that are located near the solder lands and are provided independently, and do not contribute to the attachment of components, and the solder swells due to surface tension. Since the solder land has a shape with a meaning such as an arrow or number with a thickness of can. Also, even when there are multiple such parts on the same printed wiring board, the existence of solder lands shaped like arrows, numbers, etc.
It becomes clear where to short-circuit, and as a result, it is possible to prevent erroneous short-circuiting. Moreover, even when short-circuiting two conductor foils, instead of using a soldering iron or adding wire solder, etc., in addition to the conventional soldering iron, it is possible to use a soldering iron that is installed independently near the solder land, and to Since the short circuit can be made using the solder attached to the solder land that does not contribute to the attachment, the short circuit work can be easily and reliably performed.
第１図、第２図はそれぞれ従来例を示す部分平
面図、第３図、第４図はそれぞれ本発明の実施例
を示す部分平面図である。
１，２……導体箔、３……スリツト部、４……
短絡しようとする半田ランド、５……部品取付に
寄与しない半田ランド。
1 and 2 are partial plan views showing a conventional example, and FIGS. 3 and 4 are partial plan views showing an embodiment of the present invention, respectively. 1, 2... Conductor foil, 3... Slit portion, 4...
Solder land that attempts to short circuit, 5...Solder land that does not contribute to component attachment.
Claims (1)
ないが、半田ごてによる半田付作業時には半田ラ
ンド間を接続できるように、半田デイツプ時に移
動する方向とほぼ平行に設けた直線状のスリツト
部により半田ランドが分断されている二つの導体
箔と、前記半田ランドの近傍に位置して独立して
設けられ、かつ部品の取付けに寄与せず、表面張
力により半田が盛り上がる程度の太さの矢印、数
字等の意味を持つ形状とした半田ランドとを備え
た印刷配線板。1 The solder lands are not connected during soldering dips, but in order to connect the solder lands during soldering work with a soldering iron, the solder lands are connected by a linear slit section provided almost parallel to the direction of movement during soldering dips. The two separated conductor foils are provided with arrows, numbers, etc. that are located independently near the solder land, do not contribute to the attachment of the parts, and are thick enough to cause the solder to swell due to surface tension. A printed wiring board with solder lands that have a meaningful shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15277781A JPS5853880A (en) | 1981-09-25 | 1981-09-25 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15277781A JPS5853880A (en) | 1981-09-25 | 1981-09-25 | Printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5853880A JPS5853880A (en) | 1983-03-30 |
| JPH0142515B2 true JPH0142515B2 (en) | 1989-09-13 |
Family
ID=15547912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15277781A Granted JPS5853880A (en) | 1981-09-25 | 1981-09-25 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5853880A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2502644B2 (en) * | 1987-12-28 | 1996-05-29 | 松下電器産業株式会社 | Thick film circuit board |
| JPH01181497A (en) * | 1988-01-08 | 1989-07-19 | Matsushita Electric Ind Co Ltd | Connecting method of wiring conductor |
| JPH04125471U (en) * | 1991-05-01 | 1992-11-16 | 富士通テン株式会社 | printed circuit board |
| JP5405749B2 (en) | 2008-01-15 | 2014-02-05 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device wiring board, semiconductor device, electronic device and motherboard |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5724758A (en) * | 1980-07-21 | 1982-02-09 | Sanwa Sangyo Kk | End joint base for roof tile |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5515331Y2 (en) * | 1974-05-20 | 1980-04-09 | ||
| JPS5729340Y2 (en) * | 1977-11-14 | 1982-06-26 |
-
1981
- 1981-09-25 JP JP15277781A patent/JPS5853880A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5724758A (en) * | 1980-07-21 | 1982-02-09 | Sanwa Sangyo Kk | End joint base for roof tile |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5853880A (en) | 1983-03-30 |
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