JPH0141056B2 - - Google Patents

Info

Publication number
JPH0141056B2
JPH0141056B2 JP56168152A JP16815281A JPH0141056B2 JP H0141056 B2 JPH0141056 B2 JP H0141056B2 JP 56168152 A JP56168152 A JP 56168152A JP 16815281 A JP16815281 A JP 16815281A JP H0141056 B2 JPH0141056 B2 JP H0141056B2
Authority
JP
Japan
Prior art keywords
pulse train
synchronization word
signal
code
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56168152A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5869151A (ja
Inventor
Tadayoshi Kitayama
Shigeyuki Kawarabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56168152A priority Critical patent/JPS5869151A/ja
Publication of JPS5869151A publication Critical patent/JPS5869151A/ja
Publication of JPH0141056B2 publication Critical patent/JPH0141056B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56168152A 1981-10-21 1981-10-21 復号化回路 Granted JPS5869151A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56168152A JPS5869151A (ja) 1981-10-21 1981-10-21 復号化回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56168152A JPS5869151A (ja) 1981-10-21 1981-10-21 復号化回路

Publications (2)

Publication Number Publication Date
JPS5869151A JPS5869151A (ja) 1983-04-25
JPH0141056B2 true JPH0141056B2 (de) 1989-09-01

Family

ID=15862778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56168152A Granted JPS5869151A (ja) 1981-10-21 1981-10-21 復号化回路

Country Status (1)

Country Link
JP (1) JPS5869151A (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4759040A (en) * 1986-02-01 1988-07-19 Iwatsu Electric Co., Ltd. Digital synchronizing circuit

Also Published As

Publication number Publication date
JPS5869151A (ja) 1983-04-25

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