JPH01320811A - Transversal filter - Google Patents

Abstract

PURPOSE:To minimize an error in a filter output by selecting a tap of a selector sequentially from the center tap toward taps at both ends. CONSTITUTION:Since two storage sections 22, 22' are provided, the processing time is halved. Then data D6-D0 at each tap of the upper stage are selected sequentially by a selector section 21, and the result via a storage section 22 and an accumulator 23 and the result obtained similarly as to data D7-D12 at each tap of the lower stage are added by an adder 15 to obtain a filter output Dout. Since the output of ROM 1 is D6-D0, then the object of missing is D0 being with less effect. Similarly, since the output of a ROM 2 is '0' and D7-D12, the object of missing is D12 with less effect.

Description

[Detailed Description of the Invention] [Summary] Consisting of a plurality of delay elements connected in series to hold input data while sequentially shifting it in synchronization with a sampling clock, taps are provided at the input and output terminals of each delay element. a delay unit in which a delay unit is formed; a selector unit that selectively extracts the input data from each tap; and a multiplier between the input data selected by the selector unit and the tap coefficient at the time of selecting the tap. Regarding a transversal filter consisting of a storage section that is read using an internal clock that is faster than the sampling clock, and an accumulation section that cumulatively adds the multiplication values read from the storage section to generate a filter output. In order to minimize the error in the filter output Dout even if a specified number of internal clocks are not input to the filter, the selection of the taps in the selector section is performed sequentially from the center tap to the taps at both ends. Configure.

[Industrial Application Field] The present invention comprises a plurality of delay elements connected in series to hold input data while sequentially shifting it in synchronization with a sampling clock. a delay unit in which a delay unit is formed; a selector unit that selectively extracts the manual data from each tap; and a multiplier between the input data selected by the selector unit and the tap coefficient at the time of selecting the tap. The present invention relates to a transversal filter that includes a storage section that reads data using an internal clock faster than a sampling clock, and an accumulation section that cumulatively adds the multiplication values read from the storage section to generate a filter output.

Such a transversal filter (transversal type digital filter) is used, for example, when equalizing the distortion of a signal waveform received through a transmission path.

[Prior Art] FIG. 7 is a diagram showing the concept of a general transversal filter. In this figure, reference numeral 11 denotes a delay element, in which a plurality of delay elements are connected in series, and each input/output terminal has a tap 12.
The delay section 13 is formed as a whole. The input data Din is sequentially shifted and held in the delay unit 13 in synchronization with the sampling clock CLs.

The input data Din from each tap 12 is processed by a multiplier 14 to obtain a corresponding tap coefficient a. , al...aN-1
The target filter output Dout is obtained by taking the sum of each multiplied value in an adder 15.

FIG. 8 is a diagram showing a specific example of the configuration of a transversal filter to which the present invention is applied. Since the configuration of FIG. 7 requires a large number of multipliers 14, in order to eliminate this,
A time-sharing method is used. In addition, each tap coefficient (a O+ a
+ "" a N-1) and the input data Din are calculated and stored in advance. That is, the selector section 21 selects any one of the taps one after another, takes out the input data Din, and reads out from the storage section 22 the value multiplied by the tap coefficient at the time of the selected tap. For this readout,
Tap numbers sequentially selected by a timing extractor (counter) and input data Din from the selector are used as addresses. In this example, the multiplication value of the tap coefficient and the input data is stored in the storage unit, but it is also possible to store only the tap coefficient for the tap number and multiply it using a multiplier. However, the effect of the present invention remains unchanged.

The multiplication values sequentially read out from the storage section 22 are cumulatively added in the cumulative addition section 23 and taken out via the gate 25 as the filter output Dout every sampling clock CLs. Within this one sampling clock CLs,
Since time division operations and the like must be performed for the number of taps, the internal clock CLi, which is faster than the clock CLs, is applied to the storage section 22 and the adder 24. The frequency of CLi is set to be more than the number of taps times the frequency of CLs.

[Problem that the invention seeks to solve]

As described above, a certain relationship exists between the sampling clock CLs and the internal clock CLi. That is, a predetermined number of internal clocks CLi must appear within one sampling clock CLs. If even one internal clock CLi is missing,
This is because the adder 15 in FIG. 7 does not sum up all the taps. If this happens, an error will occur in the filter output Dout, reducing reliability.

However, in practice, for example, the clock width of the sampling clock CLs generated by the timing recovery circuit in a demodulator may fluctuate due to jitter, and especially when the clock width becomes short,
A specified number of internal clocks CLi enters within s, the multiplication value for one or several taps is missing, and the filter output]) out
A problem arises in that the data contains errors.

In the present invention, even if a specified number of internal clocks do not enter within one sampling clock, the filter output Dou
It is an object of the present invention to provide a transversal filter that can minimize the error in t.

[Means for Solving the Problems] FIG. 1 is a diagram showing the principle of the present invention, and in particular, the selector section 2I is devised. The selector unit 21 selects taps in the selection order shown in the figure, ■→■→■→■, and accesses the storage unit 22.

FIG. 2 is a diagram showing a modification of the principle of the present invention, and shows ■→■
Select the tap as →−■→■. As is clear from FIGS. 1 and 2, in the transversal filter of the present invention, the tap selection of the selector section 21 is
The taps are sequentially performed from the center tap 12C to the both end taps 12E and 12E'.

[Function] In general, the tap coefficient becomes larger as it approaches the center tap, and conversely becomes smaller as it approaches both end taps. This is more important than the data connected to the center tap, and the filter output Dout
This means that the closer the data connected to the taps at both ends, the less the influence is on the filter output Dout.

Focusing on this fact, ■ sampling clock CLs
When there is an internal clock CLi that cannot be accessed, if the data selected corresponding to this missing internal clock CLi is the data connected to the tap farther from the center tap, it will be possible to prevent this internal clock from missing. The influence of errors on the filter output Dout based on the filter can be minimized.

〔Example〕

FIG. 3 is a diagram showing an embodiment based on the present invention. The transversal filter shown in this figure is of a parallel processing type, and is divided into two halves, an upper half and a lower half in the figure.
OMI) 22 and a second storage unit (RO unit 2) 22'. Compared to having a receiver with k (k is a natural number) taps in one memory section, if the receiver has two memory sections, the processing time is halved. Note that the two-divided structure is indicated by adding ' to the corresponding reference number.

Data bar for each tap in the upper row of the figure. ~D6, and the data of each tap in the lower row is D7~D1°. D.

~D6 are sequentially selected by the selector section 21, and the first storage section (R
O old) 22, the result after passing through the cumulative addition section 23, and D7 to D1
The adder 15 adds the result similarly obtained for □ to obtain the filter output Dout.

FIG. 4 is a diagram showing normal operation when the circuit shown in FIG. 3 is configured with a conventional selector section. Normal state means that a specified number of internal clocks CLs are present within one sampling clock CLs.
This means that i is included.

FIG. 5 is a diagram showing the operation in the event of an abnormality when the circuit of FIG. 3 is configured with a conventional selector section. Abnormal times are one C
This means that the specified number of CLi does not fit within Ls. In Figures 4 and 5, CLi, CLs in the left column
, rl, r2, R, CLs', etc. are all signals of corresponding portions in FIG.

Referring to FIG. 4, at tamp number 0, the ROMI beam.

The value corresponding to (Do XaQ) is output, and the addition result r
1 was also glued at that time. (D o X a O). This Do is the DI (DIXa
(l), and finally rl is added. +-+D
It becomes 6. In this case, the system in the lower column of Figure 3 is DI2. D
I2+ DIl, DI2+DIl + DI.

− is calculated, and finally r2 becomes D1□+−+D. The addition result R, which is the sum of these rl and r2, is finally . +-+ D , □, and the filter output Do
Dout is obtained at the clock CLs' that reads ut.

In the abnormal state shown in FIG. 5, data for D6 in Dout is missing ('D,).

Since D6 is not taken into consideration, Dout includes an error.

In this case, it should be noted that D6 is a value near the center tap (center of all taps 0 to 12) (because a conventional selector section is used).

In other words, the error given to Dout is quite large.

Therefore, when the selector unit 21 (FIG. 1) of the present invention is used, at least the above D6 can be dropped, and the data that is dropped is data that has little influence on Dout (near the taps at both ends).

FIG. 6 is a diagram showing the operation when the selector section of the present invention is introduced into the circuit of FIG. 3, and corresponds to FIGS. 4 and 5 described above. However, ROM 1 output is D6. D5-, which is the opposite of the conventional case. In this case, the items to be omitted are those with a small impact. (Also., D
, ). Also, ROM2 output is “0゛, D?, D8
．． D9'-, which is the opposite of the conventional case. In this case, the items to be omitted are ones with a small impact or □(
Or D1□, D,).

〔Effect of the invention〕

As explained above, according to the present invention, the internal clock CL i
Highly accurate filter output can be obtained despite the lack of .

This method of reversing the conventional method may be extremely simple, for example, by replacing an up counter with a down counter.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a modification of the principle of the present invention, FIG. 3 is a diagram showing an embodiment based on the present invention, and FIG. Figure 5 is a diagram showing normal operation when the circuit is configured with a conventional selector unit, Figure 5 is a diagram representing abnormal operation when the circuit in Figure 3 is configured with a conventional selector unit, and Figure 6 is Figure 3 shows a circle showing the operation when the selector unit of the present invention is introduced into the circuit, Figure 7 shows the concept of a general transversal filter, and Figure 8 shows a transversal filter to which the present invention is applied. FIG. 2 is a diagram showing a specific example of the configuration. 11...Delay element, 12...Tap, 12c...Center tap, 12E, 12E'...Both end taps, 13...Delay section, 21...Selector section, 22...Storage section , 23... Cumulative addition section, CLs... Sampling clock, CLi... Internal clock, Din... Input data, Dout... Filter output.

Claims (1)

[Claims] 1. Input data (Din) is input to a sampling clock (
A delay unit comprising a plurality of delay elements (11) connected in series in order to sequentially shift and hold in synchronization with CLs), and a tap (12) is formed at the input and output terminal of each delay element (11). (13), and the input data (Di
a selector part (21) for taking out n);
21) The multiplication value of the input data (Din) selected by the tap coefficient at the time of selecting the tap is calculated using an internal clock (C) faster than the sampling clock (CLs).
A transversal filter consisting of a storage section (22) that reads out the multiplication values read from the storage section (22), and an accumulation section (23) that cumulatively adds the multiplication values read out from the storage section (22) to generate a filter output (Dout). In, the selection of the tap in the selector section (21) is as follows:
From the center tap (12C) to both end taps (12E, 12E
′).