JPH01317298A - Address control system - Google Patents

Abstract

PURPOSE:To obtain an address switching signal which follows the variation of a clock signal by bringing a high speed clock signal to frequency division and generating a switching signal from this divided signal. CONSTITUTION:High speed and low speed clock signals CK1, CK2 are supplied to high speed and low speed address generating means 1, 2, respectively, and a high speed address signal AD1 and a low speed address signal AD2 are generated, and supplied to a selecting means 5. The high speed clock signal CK1 is supplied to a frequency dividing means 3, as well, brought to frequency division by a prescribed frequency division ratio and supplied as a clock signal CK3 to a switching signal generating means 4. The switching signal generating means 4 detects the address variation point of the low speed address signal AD2, and supplies the pulse of the clock signal CK3 after a prescribed time as a switching signal SW to a selecting means 5 from its variation point. In such a way, when the frequency of the clock signal for generating the address signal is switched, the address switching signal can be changed by following it.

Description

[Detailed Description of the Invention] [Summary] Regarding an address control method that controls writing and reading of a storage device using a plurality of address signals having different speeds, when the frequency of the clock signal that generates the address signal is switched. , the purpose is to provide an address control method that can easily change the address switching signal in accordance with this, and when controlling the address of a storage device using a high-speed address signal and a low-speed address signal. high-speed address generation means for generating the high-speed address signal based on the low-speed clock signal; low-speed address generation means for generating the low-speed address signal based on the low-speed clock signal;
Frequency dividing means for frequency dividing the high speed clock signal at a predetermined frequency division ratio; and switching signal generation for detecting an address change point of the low speed address signal and extracting a specific pulse signal from the output of the frequency dividing means as a switching signal. and a selection means for selectively outputting the high-speed address signal or the low-speed address signal to the storage device based on the switching signal.

[Industrial application field]

The present invention relates to an address control method for controlling writing and reading of a storage device using a plurality of address signals having different speeds, and is particularly suitable for application to address control of a buffer memory for data compression and conversion.

[Conventional technology]

FIG. 5 is a block diagram showing a conventional address control method.

In the figure, a high-speed address signal D1 for data writing and a low-speed address signal D2 for data reading are selectively supplied via a selector 10 to the address input of a memory IJM having a RAM configuration. selector 10
Since the write address signal ADI is normally selected by the address switching signal SW, the memory M is in a write mode in which input data WD is written by the write address signal ADl.

When the address content of read address signal AD2 changes,
The switching signal generation circuit 11 detects the point of change. Two pulse signals P1 and P2 having mutually different phases are input to the switching signal generation circuit 11. When the switching signal generation circuit 11 detects a change point of the address signal AD2, the address signal AD2 of the pulse signals P1 and P2 is
The pulse signal whose phase is shifted from the change point is selected and output as the switching signal SW.

When this selected pulse signal is supplied to the selector 10, the selector 10 selects the read address signal AD2 and supplies it to the memory M. Therefore, while this pulse signal, that is, the switching signal SW is at the "1" level, the memory M is in a read mode in which stored data is read from the position indicated by the address signal AD2.

[Problem to be solved by the invention]

By the way, according to such a conventional example, in a system that selectively switches the frequency of the clock signal that generates the address signal, it is necessary to switch the pulse width of the switching signal SW accordingly. It is necessary to prepare a plurality of pairs of P1 and P2, which poses a problem of complicating the circuit configuration.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address control method that can easily change an address switching signal in accordance with the switching of the frequency of a clock signal that generates an address signal.

[Means to solve the problem]

As shown in the principle diagram of FIG. 1, high-speed clock signal CK1
A high-speed address generation means 1 that generates a high-speed address signal ADI based on the signal ADI, and a low-speed address generation means 2 that generates a low-speed address signal AD2 based on the low-speed clock signal CK2.
, a frequency dividing means 3 that divides the high speed clock signal CKI at a predetermined frequency division ratio, and a specific pulse signal is extracted from the frequency divided signal CK3 from the frequency dividing means 3 by detecting the address change point of the low speed address signal AD2. and a high-speed address signal AD1 based on the output of the switching signal generating means 4.
Alternatively, a selection means 5 for selectively outputting the low-speed address signal AD2 is provided.

[For production]

High speed clock signal CK1 and low speed clock signal CK2
are supplied to the high-speed address generation means 1 and the low-speed address generation means 2, respectively, to generate the high-speed address signal ADI and the low-speed address signal AD2. Both address signals ADI and AD2 are supplied to the selection means 5, and when the switching signal SW is "0", the address signal ADI is selected, and when the switching signal SW is "1", the address signal 02 is selected. The high-speed clock signal C 1 is also supplied to the frequency dividing means 3, and is divided by a predetermined frequency dividing ratio and supplied to the switching signal generating means 4 as a clock signal CK3.

The switching signal generation means 4 detects an address change point of the low-speed address signal AD2, and supplies one pulse of the clock signal CK3 after a predetermined time period or more from this change point to the selection means 5 as a switching signal SW. The selection means 5 selects this address signal AD2 while avoiding the address change point.

〔Example〕

FIG. 2 is a block diagram showing an embodiment of the address control method according to the present invention. In addition, in this figure, the same parts as in FIG. 1 are given the same reference numerals and will be explained.

This address control method uses a write address generation circuit 1 that generates a write address signal formula 01 from a memory M1 having a RAM configuration, a high-speed lock signal (e.g., 6 to 8 MHz) CK1, and a low-speed clock signal (e.g., 64 kHz) CK.
A read address generation circuit 2 generates a read address signal AD2 from 2, a frequency divider circuit 3 divides the high speed clock signal CKI at a predetermined frequency division ratio and outputs a clock signal CK3, and detects an address change point of the read address signal AD2. The switching signal generating circuit 4 extracts a specific pulse signal from the output signal CK3 of the frequency dividing circuit 3 and outputs it as the switching signal SW, and the switching signal SW generates the address signal ADI or 802.
It is composed of a selector 5 for selecting one of the two.

The switching signal generation circuit 4, as shown in the circuit diagram of FIG.
The frequency divided signal CK3 from the frequency dividing circuit 3 is gate-controlled by an AND circuit 41 and outputted to the selector 5 as a switching signal SW. Signal S1 that gate-controls frequency-divided signal CK3
In this case, the detection signal S2 from the change point detection circuit 42 that detects the change point of the address signal AD2 is applied to the D flip-flop (hereinafter referred to as DFF) 43, the NOR circuit ￥＠44 and the second
The AND circuit 41 is gate-controlled so as to output the switching signal SW while avoiding the changing point of the address signal Al112.

The other input of the NOR circuit 44 is connected to the Q output of the third DFF 46. DFF4 for 0 man power of DFF46
The inverted output of 3 and the Q output of DFF45 are connected to AND circuit 4.
After the AND condition is taken at step 7, the signal is supplied via a selector 48 and an OR circuit 49. The other input of the OR circuit 49 is supplied with the inverted output of the DFF 43 and the Q output of the DFF 46 under an AND condition. Also, DFF4
The O output of 6 is supplied to the "0" input of selector 48.

Each of the DFFs 43, 45 and 46 is clock-controlled by the clock signal CKI, and the selector 48 outputs the output of the AND circuit 47 when the signal CK3 is at the "1" level, and outputs the output from the AND circuit 47 when the signal CK3 is at the "0" level. DF
It is configured to select the output of F46 respectively.

Next, the operation of this embodiment having such a configuration will be explained.

Since the switching signal SW is normally at the "0" level, the selector 5 normally selects the write address signal ADl. Therefore, the data WD is written in the memory M at the location specified by the address signal ADI. When the switching signal generation circuit 4 detects the address change point of the address signal AD2, the switching signal SW becomes "1" level, and the selector 5
selects address signal formula D2. For this reason, note 'J
Data R from the position specified by address signal AD2 of M
D is output.

Next, the operation of the switching signal generation circuit 4 shown in FIG. 3 will be explained with reference to the time chart shown in FIG.

First, when the address change point of the address signal AD2 (Δ in FIG. 4) is detected by the change point detection circuit 42 at time t1, a period of one period of the clock signal CK2 (B in FIG. 4) is detected from the change point. A change point detection signal S2 (C and D in FIG. 4) which reaches the "O" level is output.

This signal S2 is supplied to the DFF 43 and output as a signal S3 (FIG. 4F) which falls in synchronization with the rise of the clock signal CKI (FIG. 4E) at time t2. This signal S3 is inverted by the NOR circuit 44 and the signal S4 (FIG. 4G)
After being delayed by one clock by the clock signal CKI, it is supplied to the AND circuit 41 as a signal SL (H in FIG. 4) which rises at time t3.

Selector 48 is DF when signal CK3 is at “0” level.
Since the Q output of F46 is selected, the output signal S5 of the selector 48 (FIG. 4, 1) is at the "0" level. This signal S5 is supplied to the DFF 46 via the OR circuit 49, and
After being delayed by one clock by the clock signal CKI in the FF 46, the signal S6 (J in FIG. 4) is sent to the NOR circuit 44,
The signal is supplied to a selector 48 and an AND circuit 50.

Incidentally, the clock signal CKI is frequency-divided by the frequency dividing circuit 3 and supplied to the AND circuit 41 as a signal CK3 (K in FIG. 4). This signal CK3 converts the clock signal CKI to 1, for example.
This signal is frequency-divided by /6 and is formed by a pulse train having a pulse width equivalent to one period of the clock signal CK1.

When a pulse of 3 arrives at the signal C at time t4, the selector 48 selects the output of the AND circuit 47, so the output signal S5 of the selector 48 becomes "1" level, and after one clock delay, the signal S6 becomes "1" level at time t5. 1” level. When the signal S6 becomes the "1" level, the output signal S4 of the NOR circuit 44 is inverted to the roj level, so that the signal S1 returns to the "0" level at time t6, which is delayed by (1) clock. For this reason,
The AND circuit 41 outputs the pulse of the signal CK3 at time t4 as the switching signal SW (FIG. 4L).

Next, when the next pulse of the signal CK3 arrives at time t7, the selector 48 again selects the output of the AND circuit 47, but since the output of the AND circuit 47 has returned to the "0" level, the output S5 of the selector 48 also It falls to the "0" level. However, since the output of the AND circuit 50 is "1", the output S6 of the DFF 46 remains "1".

Thereafter, when the change point detection signal S2 returns to the "1" level at time t8, the Q output signal S3 of the DFF 43 also returns to the "1" level at the next rising edge of the clock signal CKI, that is, at time t9.

Next, when a pulse of signal CK3 arrives at time tlO, selector 48 again selects the output of AND circuit 47. At this time, since the output of the AND circuit 47 is at "0" level, the output S5 of the selector 48 falls.

At this time, the inverted output of the DFF 43 has returned to the "0" level, so the output of the AND circuit 50 also goes to the "O" level, and the output of the OR circuit 49 falls, and at time tll, which is delayed by one clock, the Q output signal S6 of the DFF 46 becomes Return to "0" level.

In this way, the gate circuit 41 is gate-controlled by the signal S1 which is at the "1" level between time points t3 and t6, so that the switching signal generation circuit 4 sends the address signal to the address signal for a predetermined period of time after the address of 〇2 changes. Thereafter, the pulse of the frequency-divided signal CK3 that arrives first is extracted as the switching signal SW. In this way, the switching signal generation circuit 4 outputs the address signal AD.
Avoid the address change point in 2 and reliably go to the address signal 〇2
A pulsed switching signal SW is output that allows selection of the following.

〔Effect of the invention〕

According to the address control method of the present invention, the frequency of the high-speed clock signal is divided and the switching signal is generated from this frequency-divided signal, so that when the frequency of the high-speed clock signal is switched, the address switching signal is changed accordingly. Since the pulse width also changes, it is possible to obtain an address switching signal that follows changes in the clock signal with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing the address control method of the present invention, FIG. 2 is a block diagram showing an embodiment of the address control method according to the present invention, and FIG. 3 is a circuit diagram of the switching signal generation circuit shown in FIG. 2. , FIG. 4 is a time chart for explaining the operation of the switching signal generation circuit, and FIG. 5 is a block diagram showing a conventional address control system. DESCRIPTION OF SYMBOLS 1... Write address generation circuit, 2... Read address generation circuit, 3... Frequency division circuit, 4... Switching signal generation circuit, 5... Selector, M... Memory.

Claims (1)

[Scope of Claims] An address control method for controlling the address of a storage device using a high-speed address signal and a low-speed address signal, comprising: a high-speed address generation means for generating the high-speed address signal based on a high-speed clock signal; and a high-speed address generation means based on a low-speed clock signal. low-speed address generation means for generating the low-speed address signal; frequency-dividing means for dividing the high-speed clock signal by a predetermined frequency division ratio; and detecting an address change point of the low-speed address signal from the output of the frequency-dividing means. It is characterized by comprising a switching signal generation means for extracting a specific pulse signal as a switching signal, and a selection means for selectively outputting the high speed address signal or the low speed address signal to the storage device based on this switching signal. Address control method.