JPH01317282A - Digital video reproducing device - Google Patents

Abstract

PURPOSE:To attain the inter-field correction and the format conversion at one time and to reduce the circuit scale by using a field memory to a time base control memory which is used to decode a variable length code. CONSTITUTION:A field memory 12 is used to absorb the time base variance of the digital video signal produced when a variable length code is decoded. Then the writing actions are controlled by a write controller 13 to the memory 12 based on a flag signal showing an error for execution of the correction equivalent to the supply of the inter-field picture elements. Then the reading actions are controlled by a read controller 14 to the memory 12 to secure the function of a deformatter for video signals. Thus the memory 12 for control of time base performs the inter-field correction and the format conversion as a memory equivalent to one field. As a result, the memory 12 can be miniaturized together with reduction of its control circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus for recording or transmitting digital video signals and reproducing and decoding them.

Prior Art Prior to discussing the prior art, high-efficiency encoding using variable length codes will be described first. In order to efficiently record or transmit digital video signals, high-efficiency encoding is used to compress the amount of information in the video signals. One effective method for high-efficiency encoding is a method that combines orthogonal transform (including Hadamard transform and cosine transform) and variable length code. The data obtained by orthogonally transforming a rectangular pixel block on the screen is
Since it takes a value near zero except for the DC component, it can be used to compress information. In other words, the overall amount of information can be compressed by assigning codes with short code lengths to values near zero that have a high probability of occurrence, and codes with long code lengths to values with low probability of occurrence. can.

When such a variable length code is used, the length of the code varies, so the data rate after encoding is generally asynchronous with the data rate of the original digital video signal. In order to absorb the temporal data rate fluctuations caused by this, a first-in-0 first-out memory (hereinafter referred to as FIFO) is usually used. The same thing can be said about decoding variable length codes.゛When the variable length code is converted, the decoded data fluctuates in the time axis direction, and in order to return it to the correct digital video signal, the FI
It is necessary to use FO to adjust for temporal data rate fluctuations. A conventional example of video playback in a digital VTR will be described below.

FIG. 2 shows a block diagram of this conventional digital video playback device, in which 1 is an error corrector, 2 is a code converter, 3 is a FIFO, 4 is a defomitter, 5 is a corrector,
6 is an error flag generator.

In the conventional digital video playback device for a digital VTR configured as described above, playback data is highly efficiently coded using variable length codes. The reproduced data is input to an error corrector 1, where correctable errors are corrected, and the reproduced data is input to a code converter 2. Furthermore, for uncorrectable errors, a flag for correction is output. The data rate at this time is given by the clock used inside the digital VTR. The code converter 2 decodes the variable length code, but the data rate of the digital video signal output at this time fluctuates over time, and the FIFO 3 is used to absorb this. FIFO
The write timing of 3 is given by the code converter 2, and the read clock is given at a data rate determined by the format of the video signal. The read digital video signal is converted by a defomitter 4 into a format suitable for a television signal, and is input to a corrector 5. On the other hand, the correction flag generator 6 generates a flag for correction by delaying the flag indicating an uncorrectable error by the delay time of the FIFO or defomster. The corrector 5 corrects the errors in the pixel blocks in which uncorrectable errors have occurred by a method such as inter-field pixel supplementation or inter-field pixel replenishment, and outputs the corrected data. An analog video signal can be obtained by D/A converting the output digital video signal.

Problems to be Solved by the Invention However, in the above configuration, a memory is required for each of the FIFO 1 deformator and corrector, and the circuit size becomes large together with the control section thereof. Furthermore, the timing of the correction flag must be delayed by an amount corresponding to the data delay time in the FIFO or defomster, and a circuit for this purpose is also required.

In view of this point, the present invention includes the following steps in decoding a variable length code:
The object of the present invention is to provide a digital video playback device that has a common memory and a reduced circuit scale.

Means for Solving the Problems The present invention provides a code converter that obtains an asynchronous digital video signal by decoding a signal obtained by highly efficient encoding of a digital video signal using a variable length code; a memory that stores video in units of one field; a write controller that controls writing to the memory based on a flag signal indicating an error in the asynchronous digital video signal; and a read that reads out from the memory in synchronization with the format of the video signal. This is a digital video playback device characterized by comprising a controller.

According to the above-described configuration, the present invention uses a field memory as a memory for absorbing time-base fluctuations in a digital video signal caused by decoding a variable length code. Then, by controlling writing to the field memory based on a flag signal indicating an error, corrections corresponding to inter-field pixel replenishment are performed, and by controlling reading from the field memory, it acts as a deformator for the video signal. .

Embodiment FIG. 1 shows a block diagram of a digital video reproducing apparatus in an embodiment of the present invention. 10 in Figure 1
11 is an error corrector, 11 is a code converter, 12 is a field memory, 13 is a write controller, and 14 is a read controller.

The operation of the digital video reproducing apparatus of this embodiment configured as described above will be described below.

The reproduced data of the digital VTR in this embodiment is highly efficiently encoded using a variable length code as in the conventional example. The reproduced data is input to an error corrector 10, where correctable errors are corrected, and the reproduced data is input to a code converter 11. The data rate at this time is given by the clock used inside the digital VTR. The code converter 11 decodes the variable length code, and the asynchronous digital video signal output at this time is input to the field memory 12. If an uncorrectable error occurs in the error corrector 10, a flag indicating this is output and input to the write controller 13. The write controller 13 uses the field memory 1 at the write timing generated by the code converter 11.
2, but data with an error flag set is not written.

Therefore, a portion where an uncorrectable error has occurred is automatically corrected using data one field before.

Therefore, a special circuit for correction is not required.

Further, reading from the field memory 12 is performed based on the timing and address given by the read controller 14. Since this readout controller 14 controls the signal to be output in a format suitable for television signals,
No special memory is required for the defomatsuta.

As in the conventional example, an analog video signal is obtained by D/A converting the output digital video signal.

As described above, according to this embodiment, the memory for time axis adjustment used for decoding the variable-length code is a memory for one field, and by performing inter-field correction and format conversion, the memory and its control circuit can be made smaller. Furthermore, a flag data delay circuit for correction can be omitted. Furthermore, TBC suppresses jitter (time axis fluctuation) of playback data in digital V'l'R.
The same memory may also serve as both functions.

In this embodiment, only one field memory is used, but correction or format conversion may be performed using a plurality of field memories. In addition to digital VTRs, similar configurations can also be used in the field of video transmission.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, by using a field memory as a memory for time axis adjustment used in decoding a variable length code, it is possible to simultaneously perform field read correction and format conversion, thereby reducing the circuit scale. It can be kept small.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital video reproducing apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional digital video reproducing apparatus. 10... Error corrector, 11... Code converter, 12.
...Field memory, 13...Write controller, 14.
...Many controllers.

Claims (1)

[Claims] a code converter that obtains an asynchronous digital video signal by decoding a signal obtained by highly efficient coding of a digital video signal using a variable length code; and a memory that receives the asynchronous digital video signal and stores video in units of fields. , comprising a write controller that controls writing to the memory using a flag signal indicating an error in the asynchronous digital video signal, and a read controller that reads from the memory in synchronization with the format of the video signal. Digital video playback device.