JPH01316073A - Field detection circuit and frame detection circuit - Google Patents

Abstract

PURPOSE:To detect a field signal having accurate output timing from composite synchronizing signals by combining a monostable multivibrator which is triggered by the composite synchronizing signals and an FF which is cleared by the output signal of the monostable multivibrator. CONSTITUTION:Composite synchronizing signals A impressed upon an input terminal 30 are inverted by an inverting gate 1 and trigger a monostable multivibrator 2 as signals B at their falling timing. The monostable multivibrator 2 outputs signals C having a pulse width T (T1<T<TH/2) by means of a timing circuit constituted of a capacitor 3 and resistance 4. On the other hand, the output, the inverse of Q, of a JKFF 5 which uses the signals B as clock signals and is actuated at the falling timing of the signals B changes from a low level to a high level when the signals C shift from a low level to a high level. By the operation of the JKFF 5, signals D having a one-field period, namely, field signals are obtained at an output terminal 40.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a detection circuit for detecting fields and frames from a composite synchronization signal.

Conventional technology The conventional method for detecting a field signal from a composite synchronization signal is to first integrate the composite synchronization signal, and at the timing when the integrated signal exceeds a reference level, invert the pulse generator to obtain the field signal. more widely used.

3. In addition, as a method for detecting frame signals, a detection method whose purpose is to distinguish between odd and even fields is common, and in this case, the output state is inverted for each field, for example. It's a signal.

Problems to be Solved by the Invention When a field signal is detected using the above integration method, there is a drawback that the output timing of the field signal cannot be accurately determined due to variations in the elements constituting the integration circuit or fluctuations in the amplitude of the composite synchronization signal. There is. Furthermore, if noise is included in the composite synchronization signal, the pulse generator will malfunction.

Furthermore, in a frame signal detected by the conventional method, a rising portion or a falling portion generally exists near the vertical synchronization pulse period. Therefore, when this frame signal is used, for example, for the purpose of video signal processing, there is a drawback that it is not an effective signal for accurately capturing the video signal line starting after the end of the vertical synchronization period.

The present invention solves the above-mentioned problems, and provides a novel field signal that can detect field signals with accurate output timing and frame signals with effective output timing for video signal processing using a series of circuit configurations. The object is to provide a detection circuit and a frame detection circuit.

Means for Solving the Problems In order to achieve the above object, the present invention uses a logic circuit to generate a field signal having accurate output timing from a composite synchronization signal and the first video signal line after the end of the vertical synchronization period in an odd field. The frame signal output in the .

Operation Since the present invention has a logic circuit configuration, it is possible to detect a field signal with accurate output timing that is not affected by noise or amplitude fluctuation contained in a composite synchronization signal.

The frame signal is output at the leading edge of the horizontal 5-channel synchronization signal of the first video signal line after the end of the vertical synchronization period in the odd field, so it becomes an accurate reference signal that indicates the video signal line. have an effect.

Embodiment FIG. 1 shows the configuration of an embodiment in which the present invention is implemented in the NTSC system, FIG. 2 is a timing chart for an odd field, and FIG. 3 is a timing chart for an even field.

In the embodiment shown in FIG. 1, 30 is an input terminal to which a composite synchronization signal is applied, 1 is an inverting gate, 5, 6° 11 is a JK flip-flop, 7 is a 10-base down counter that is decremented at the timing of the composite synchronization signal, 2 and 8 are monostable multivibrators; 40 is an output terminal for a field signal detected from the composite synchronization signal; and 50 is an output terminal for a frame signal detected from the composite synchronization signal.

The monostable multivibrator 2 has a timing circuit consisting of a capacitor 3 and a resistor 4, and its time constant is such that the output pulse width T of the multivibrator 2 is T, <T<TH/2
6, -7. Here, TH represents one horizontal scanning period, and T1 corresponds to the sum of the cutting pulse width and the equalization pulse width.

Furthermore, the monostable multivibrator 8 has a timing circuit consisting of a capacitor 9 and a resistor 10, and its time constant is such that the output pulse width T of the multivibrator 8 is (TH/2
-T2)<T<(TH-T2). Here, T2 represents the equalization pulse width.

The composite synchronizing signal A applied to the input terminal 30 is inverted by the inverting gate 1, and the monostable multivibrator 2 is triggered as the signal B at the falling timing. The multivibrator 2 uses a timing circuit including a capacitor 3 and a resistor 4 to output a signal C having a pulse width T such that T1<T<TH/2. At this time, multivibrator 2
If is triggerable, its output signal has a pulse width of (T + T1) only in the part where the composite sync signal A transitions from the vertical sync pulse period to the post-equalization period.
Therefore, Figure 2 is written in this state (however,
Multipipe Lake 2 does not necessarily have to be Retrigger 7 Pagel).

The JK flip-flop 5, which uses the signal B as a clock signal and operates at the falling timing of the clock signal, normally operates on the signal B.
Since signal C is low level at the falling edge of Q
The output remains high and signal B is in the first post-equalization period.
Since the signal C is at a high level at the falling timing only when it is an equalization pulse, the Q output changes to a low level. This state persists while signal C remains high, but when signal C goes low, the Q output returns to high again. By the above operation, a signal D1 of one field period, that is, a field signal is obtained at the output terminal 4o.

Now, at the timing when the above field signal changes from high level to low level, the JK flip-flop 6
The output (=signal E) becomes low level, and the down counter 7
Set to count operation state. At the same time, the down counter 7 is set to output the given preset data (0101) 2, and the ripple clock signal F is set to a high level. Thereafter, the field signal returns to high level.

Since the TK flip-flop 6 holds its Q output at a low level while the signal F is at a high level, the down counter 7
is decremented at the timing of signal B, and when signal B becomes the last equalization pulse during the post-equalization period, the count output becomes (OOOO)2, and therefore signal F changes to low level.

1, the flip-flop 6 returns its Q output (=signal E) to a high level since the signal F is at a high level when the signal F falls, and the down counter 7 enters a counting stop state. As a result of the above operation, the signal E, which becomes low during the post-equalization period of the composite synchronization signal, triggers the monostable multivibrator 8 at its rising timing.

Multivibrator 8 has capacitor 9 and resistor 1o
The timing circuit consisting of (TH/2-T2)<
A signal G having a pulse width T such that T<(TH-T2) is output.

The TK flip-flop 11 at the final stage maintains its Q output at a low level while the signal G is at a low level on page 9. However, if the clock input signal (=signal A) is an odd field composite synchronization signal, Since the horizontal synchronizing pulse exists υ(TH/2) after the final equalizing pulse within the equalization period,
The high level of the signal G is captured at the falling timing of the horizontal synchronizing pulse, and the Q output (=signal H) is set to the high level.

This signal H remains at a high level while signal G is at a high level,
As the signal G changes to low level, it becomes low level.

If the clock input signal is an even-field composite synchronization signal, there is a TH gap from the final equalization pulse to the next horizontal synchronization pulse in the post-equalization period, The high level of the signal G is not detected at the downstream timing, so the signal H continues to be at the low level.

Through the series of operations described above, signal H is output at the leading edge of the first horizontal synchronization pulse after the end of the post-equalization period only when composite synchronization signal A is an odd field, and has a pulse width smaller than (TH/2). Therefore, it can be obtained from the output terminal 60 as a frame signal 1oh/'.

When the present invention is implemented in the PAL system, the preset data of the down counter 7 may be set to (oloo)2.

FIG. 4 is a block diagram schematically showing an embodiment in which a frame signal detected by the present invention is used for video signal processing.

When a video signal to be analyzed is applied to the input terminal 6o, A
The signal is converted into digital data by the /D converter 61, and at the same time, a composite synchronous signal signal is detected by the synchronous separation circuit 62.

The timing circuit of the monostable multivibrator 63 is selected so that its output pulse width T satisfies ("H/2) < T < TH, and as a result, the equalization pulse and cutting pulse of (TH/2) period increase. The signal with the TH period removed is output.

Since the address counter 64 uses the signal as a clock signal, one address is updated every horizontal line.

At this time, the detection circuit 67 detects the deviation 116 from the composite synchronization signal ■.
- Since the seam signal N is detected and the counter 64 is initialized at the timing of the leading edge of the first horizontal synchronization pulse after the end of the vertical synchronization period in the odd field, the video signal digital data is stored in the memory 66 in order from the first video line of one frame. can be stored.

With the above configuration, the arithmetic processing circuit 66 can process the stored digital data and analyze the video signal of any horizontal line within one frame.In addition, in the above embodiment, the down counter 7 can be used to change the preset data. An up counter may also be used.

Moreover, if the polarity of the composite synchronization signal is taken into account, the JK flip-flops 5, 6, and 11 can also be configured with D flip-flops.

Effects of the Invention As described above, the present invention detects field signals and frame signals using a logic circuit, so that stable and accurate operation is achieved.

Furthermore, since the frame signal is output at the leading edge of the horizontal synchronizing pulse in the first video signal line after the start of an odd field, it can be used as an accurate reference signal during video signal processing. It is also effective as a trigger signal when observing video signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a field detection circuit and a frame detection circuit in one embodiment of the present invention, FIGS. 2 and 3 are timing charts for explaining the operation of the circuit in FIG. 1, and FIG. FIG. 2 is a schematic block diagram when the circuit is used for video signal processing. 1... Inversion gate, 2, 8.63... Monostable multivibrator, 5, 6.11... TK flip-flop, 7... 1o counter, 3, 9
...Capacitor, 4,1Q...Resistor, 30.
...Composite synchronization signal input terminal, 40...Field signal output terminal, 50...Frame signal output terminal, 60...Video signal input terminal, 61...
A/D converter, 62...Synchronization separation circuit, 64...
・Address counter, 65...Memory, 66・
... Arithmetic processing circuit.

Claims (2)

[Claims] (1) A monostable multivibrator triggered by a composite synchronous signal, and a flip-flop which uses the composite synchronous signal as a clock input signal and is cleared by the output signal of the monostable multivibrator, and from the output terminal of the flip-flop. A field detection circuit characterized in that it outputs a field detection signal. (2) a first monostable multivibrator triggered by a composite synchronization signal; and a first flip-flop that uses the composite synchronization signal as a clock input signal and is cleared by the output signal of the first monostable multivibrator; A second flip-flop that is cleared by the field detection signal obtained from the first flip-flop and the composite synchronization signal are used as clock input signals to start counting operation by the output signal of the second flip-flop, and the counting operation completes one cycle. a counter that inputs the signal outputted every time as a clock input signal to the second flip-flop; a second monostable multivibrator that is triggered by the output signal of the second flip-flop; A third flip-flop is provided as a clock input signal and is cleared by the output signal of the second monostable multivibrator, and a frame detection signal is output from the output terminal of the third flip-flop. Features a frame detection circuit.