JPH01314354A - Cache memory control system - Google Patents

Abstract

PURPOSE:To perform cache control at a high speed by providing a move-out buffer register where data to be written in a main storage from a cache memory is held temporarily, and writing the data to be written in the main storage from the cache memory in the buffer register and then fetching data from the main storage to the cache memory. CONSTITUTION:The move-out buffer register 3 holds the (move-in) data to be written in the main storage from the cache memory 2 temporarily. When the cache memory control is performed by a move-in system and it becomes necessary to move the data out of the cache memory 2 to the main storage 4 or move the data in the cache memory 2 from the main storage 4, the data is not moved out directly to the main storage 4, but written in the move-out buffer register 3 which is provided newly speedily and then moved in. Consequently, the time required for the moving-in operation is shortened to speed up the access.

Description

[Detailed Description of the Invention] (Summary) Regarding a cache memory control method for controlling data transfer in the cache memory, a move-out buffer register is provided to temporarily hold data to be written from the cache memory to the main storage device.
After writing the data to be written to the main memory from the cache memory, the data is retrieved from the main memory to the cache memory, and the data read from the main memory is retained for the purpose of high-speed cache control. It is equipped with a cache memory and a move-out buffer register that temporarily holds data that is about to be transferred from the cache memory to the main memory, and the corresponding data is registered in the cache memory in response to an access request. If there is no free space, the data to be written (moved out) from the cache memory to the main memory is stored in the move-out buffer register, and then the data is transferred from the host tα device to the main storage when the cache memory becomes free. The configuration is such that the data is written (moved in) to the area, the data is transferred to the access request source, or the moved-in data is updated, and the data stored in the move-out buffer register is written into the main memory.

[Industrial application field]

The present invention relates to a cache memory control method for controlling data transfer in a cache memory.

As a method to control cache memory data transfer,
There is a so-called store-in method. In this method, if the data to be stored is registered in the cache memory when a store occurs (hinted), the data to be stored is written only to the cache memory, the store process ends, and the next On the other hand, if the data to be stored is not registered in the cache memory (in the case of a miss), the data (block) to be stored is requested from the main storage, registered in the cache memory, and then stored. Writing data in an updated manner eliminates the need to write data to the main memory each time, allowing high-speed access.

[Conventional technology and problems to be solved by invention] Conventionally,
A store-in method is adopted, and when the target data (block) is not registered in the cache memory at the time of read/write, a so-called move-in is performed in which the data is read from the above jf) device and registered in the cache memory. There is a need.

At this time, there is no free block in the cache memory and an attempt is made to move in the least used block, but if this block has been updated with store data and has not yet been written to the main memory, first The updated data is moved out to the main storage device, and then moved in to this empty page area. For this reason, it is not possible to move in from the main memory to the cache memory until the move out from the cache memory to the main memory is completed, which slows down the access processing speed and forces the access requester (CPU) to wait. There was a problem with this.

The present invention provides a move-out buffer register that temporarily holds data to be written from the cache memory to the main memory, and after writing the data to be written from the cache memory to the main memory, the data is transferred from the main memory. The purpose is to import data into cache memory and perform cache control at high speed.

[Means to solve problems]

FIG. 1 shows a basic configuration diagram of the present invention.

In FIG. 1, a cache memory 2 is a memory that can be accessed at high speed and stores data read from the Iri device 4.

The move-out buffer register 3 temporarily holds data to be written (moved in) from the cache memory 2 to the main storage device 4.

The main storage device 4 stores data.

The command processing device 6 is an access request source and performs various processes.

[Effect]

As shown in FIG. 1, in response to an access request (read/write request) from an instruction processing device 6 that is an access request source, when a hint is given, the corresponding data is processed from the cache memory 2 by instruction processing. Data is transferred to the device 6 or written in a manner that updates the corresponding data in the cache memory. On the other hand, there was a miss and there was no free space in the cache memory 2, and an attempt was made to use the least used block, but the data written to this block was updated and was still written to the main storage device 4. If not, after storing this data in moveout buffer register 3,
The corresponding data is read from the main storage device 4 and written to two empty areas of the cache memory 2, and the instruction processing bag W
6 or data newly written in this cache memory 2 is written in an updated manner. And moveout buffer register 3
The data stored in the main storage device 4 is written (moved out) to the main storage device 4.

Therefore, when controlling the cache memory using the so-called move-in method, if it becomes necessary to move data from the cache memory to the main memory device 4 and move data from the main memory device 4 to the cache memory, the move-out It becomes possible to perform move-in after writing to the newly provided move-out buffer register 3 at high speed instead of directly writing it to the main memory bag N4, and the access request source can perform access at high speed.

〔Example〕

First, the overall configuration will be explained using FIG. 2.

In FIG. 2, the instruction processing device 6 is a CPU or the like, and accesses the main storage device 4 to perform various processes. This instruction processing device 6 has address lines (1) shown in the figure,
An access request is made to the storage control device 1 using the control line +11 and the data line (1).

The storage control device 1 has a cache memory 2, a move-out buffer register 3, etc. according to this embodiment,
It controls access to the main storage device 4.
This storage control device 1 has an address line (2) shown in the figure, 1
1 L'A f21, uJ data line (2?) is used to control access to the main storage device 4.

The main storage device 4 stores data, programs, and the like.

Next, the configuration and operation of one embodiment of the present invention will be sequentially explained in detail using FIG.

In FIG. 3, the cache memory 2 is a main storage device 4.
It holds the data read from. When a read request is made, the corresponding data registered in this cache memory 2 is transferred to the access request source, and when a write request is made, the data specified for writing is transferred to the corresponding data registered in this cache memory 2. The data is written in a manner that updates the data. This cache memory 2 has a capacity of, for example, 64 bytes, and is configured to perform move-in/move-out in units of 16 bytes.

The TAG memory 2-1 stores information (hit/miss information) as to whether or not the data requested to be accessed is registered in the cache memory 2.

The LRU memory 2-2 stores data registered in the cache memory 2 in the order of newest and oldest.

As mentioned above, the moveout buffer register 3 is
It is capable of high-speed operation and is used to temporarily store data to be moved out from the cache memory 2 to the main storage device 4. This moveout buffer register 3
The capacity is, for example, 16 bytes, which is the move-in/move-out unit of the cache memory 2, divided into two, and is made up of 8 bytes x 2. Data lines (1), (2)
has a width of 8 bytes.

The selection circuit 5-1 selects either the data transferred from the instruction processing device 6 in response to a write request or the data read from the main storage device 4, and writes it into the corresponding area in the cache memory 2. It is something.

The selection circuit 5-2 selects the data read from the cache memory 2 or the main memory bag! This is for selecting any one of the data read from 4 and transferring it to the instruction processing device 6.

The address register 7 holds an address notified from the instruction processing device 6 via the address line (1).

The comparison circuit 8 compares the address held in the address register 7 and the block address information read from the TAG memory 2-1, and determines whether they match (determines hits/misses). It is something to do.

When the mistake detection circuit and device ta control circuit 9 receives a notice of a mistake (-not defeated) from the comparison circuit 8, the LRU
The most recently used block address read from the memory 2-2 is retrieved, and if the data therein remains updated, a move-out instruction is issued to the main storage device 4.

The operation of the configuration shown in FIG. 3 will be explained.

First, when there is an access request from the instruction processing device 6 to the storage control device 1, the address to which the access request was made is set in the address register 7, and the TAG memory 2-
If you search for 1 and get a hint, when the access request is a read request, the data read from cache memory 2 is
The data is transferred to the instruction processing device 6 via the selection circuit 5-2, buffer and data L%(1), and when the access request is a write request, the write data transferred via the selection circuit 5-1 is The data is written to the corresponding area of the cache memory 2 in an updated manner. Then, the LRU information of the corresponding block in the LRU memory 2-2 is updated.

Second, if there is a miss and there is a free block after searching the LRU memory 2-2, the corresponding data read from the main storage device 4 is transferred to the cache memory 2-2 via the selection circuit 5-1.
At the same time, when the access request is a read request, the data continuing from the main storage device 4 is transferred to the instruction processing device 6 via the selection circuit 5-2 as is. At the time of a write request, write data is written in a manner that updates the data written in the cache memory 2.

Third, if there is a miss, and there is no free block when searching the LRU memory 2-2, and the block retrieved as the least used block has not been updated in the previous store,
This block is processed in the same way as the second one.

Fourth, if there is a miss and the LRU memory 2-2 is searched and there is no free block, and the block retrieved as least used has been updated in the previous store, the data of this block is moved to the moveout buffer. register 3
Then, similarly to the second case, the corresponding data read from the main memory 4 is registered in this block in the cache memory 2 via the selection circuit 5-1, and when the access request is a read request, the selection circuit 5-2. The data read from the main storage device 4 is transferred as is to the instruction processing device 6 via the buffer and data Natg. On the other hand, when the access request is a write request, the data written in the cache memory 2 is updated. The write data is written in a manner that The data stored in the move-out buffer register 3 is then written to the main storage device 4.

Therefore, at the fourth time, after writing the data to be moved out from the cache memory 2 to the main memory bag 4 to the moveout buffer register 3 at high speed, the data is moved in from the main memory device 4 to the cache memory 2 and at the same time a read request is made. In response to this, the data is transferred to the instruction processing device 6, and on the other hand, in response to a write request, Mr. B writes the write data to the data in this cache memory 2, thereby executing the move-out process. It becomes possible to perform the processing at high speed, and as a result, the instruction processing device 6 can access the data at high speed.

Next, the operation at the fourth time will be explained in detail using FIG.

In FIG. 4, 1τ indicates a state in which an address is sent from the instruction processing device 6.

The second τ indicates a state in which the TAG memory 2-1 is searched using this sent address and a mistake is detected.

In the 3rd τ, a mistake is detected in the 2nd τ, and the LRU memory 2
If it is determined that the oldest block indicated by -2 is an updated block, MVIRequest (
move-in request) to main memory, and
As shown in (2), 8 bytes of the data (16 bytes) to be moved in from the cache memory 2 are stored in the move-out buffer register 3.

At the 4th τ, the main memory device 4 is activated, and the remaining 8 bytes are stored in the move-out buffer register 3, as shown in (3).

° As shown in RDTI and RDT2, the 5τ, 6τ, and 7τ are read from the main storage device 4 in two parts of 8 bytes each, and are written in the corresponding El area of the cache memory 2 in two parts of 8 bytes each ( Then, at the 7th τ, the month νOR request is sent to the main storage device 4.

8τ, 9τ, and 10τ write (move out) the data read from the move-out buffer register 3 into the main storage device 4 in two parts of 8 bytes each, as shown at T1 and WDT2.

Through the above processing, the instruction processing device 6 can sequentially receive the transfer of 8 bytes of the corresponding data at the 5th and 6th τ, and can access the data at high speed.

Note that this embodiment uses a plurality of central processing units (instruction processing units).
In a so-called multiprocessor system in which multiple processors share a main memory, it is possible to reduce the number of accesses to the main memory and perform high-speed access.

〔Effect of the invention〕

As explained above, according to the present invention, when performing cache memory control using the so-called move-in method, it is necessary to move data out from the cache memory to the main storage device 4 and to move data in from the main storage device 4 to the cache memory. When a move-out occurs, the move-out is not performed directly to the main memory 4, but is written to the newly provided move-out buffer register 3 at high speed, and then the move-in is performed. It is possible to shorten the time and perform access at high speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2I21 is a detailed explanatory diagram of the present invention, FIG. 3 is a diagram illustrating the configuration of an embodiment of the present invention, and FIG. 4 is a diagram illustrating the operation of the present invention. In the figure, 1 is a storage control 2I device, 2 is a cache memory,
2-1 is TAG memory, 2-2 is LRU memory, 3 is move-out buffer register, 4 is main memory, 5-1
．． Reference numeral 5-2 represents a selection circuit, 6 an instruction processing device, 8 a comparison circuit, and 9 a miss detection circuit and a replacement control circuit.

Claims (1)

[Claims] In a cache memory control method for controlling data transfer of a cache memory, there is provided a cache memory (2) that holds data read from a main storage device (4); (4) is equipped with a move-out buffer register (3) that temporarily holds the data to be written, and in response to an access request, if the corresponding data is not registered in the cache memory (2) and there is no free space. To,
After storing the data to be written (moved out) from the cache memory (2) to the main memory (4) in the move-out buffer register (3), the data is transferred from the main memory (4) to the cache memory (2). ) is written into the empty area (move-in), and the data is transferred to the access request source, or this moved-in data is updated, and the above-mentioned move-out buffer register (3) is written.
A cache memory control method characterized in that the data stored in the cache memory is written to the main storage device (4).