JPH01314014A - Delay circuit - Google Patents

Abstract

PURPOSE:To obtain a delay time accurately by controlling an over driving voltage of a signal applied to a comparator of an output stage to be always a constant value even if a threshold value controlling the delay time is varied. CONSTITUTION:A noninverting input terminal of a comparator 17 is connected to a connecting point A of diodes 9, 10 and a capacitor 16 is provided between the noninverting input terminal and the circuit earth. On the other hand, a voltage source 18 deciding the threshold value VB is connected to the inverting input terminal and the threshold voltage VB is controlled to decide the delay time. Moreover, a diode 14 and a voltage source 19 are connected between the inverting input terminal of the comparator 17 and the collector of a transistor-(TR) 8 and the voltage of the voltage source 19 is an optional constant voltage VO. Thus, even if the level of the threshold value VB is varied, the overdriving voltage applied to the comparator 17 is always the constant voltage VO. Thus, the delay time and the threshold level are kept in a linear relation and the accurate delay signal is obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a delay circuit.

[Conventional technology]

Generating a signal SO that rises after a time TX with respect to the phase of a basic signal (for example, a rising edge) and using this signal SO as a synchronization signal or a control signal is not frequently done in electronic circuits. It will be done.

The delay circuit discussed in this specification is a delay circuit used in such electronic circuits, and has an extremely small delay time TX.
This invention relates to a circuit that can arbitrarily obtain a signal with .

FIG. 3 shows a conventional delay circuit, and FIG. 4 shows operating waveforms of FIG. 3.

In FIG. 3, 31 and 32 are comparators (the impact resistance of the present invention also includes receivers), and 33 to 35 are resistors.

In general, a TTL or ECL level waveform (input signal Si) is applied to the comparator 31, for example, at an input terminal. On the other hand, a voltage of a threshold value Va is applied to one input terminal of the comparator 31, and the input signal Si is waveform-shaped. Therefore, a waveform as shown in FIG. 4(1) Sa is applied to the input terminal of the comparator 32. Figure 4 (
The reason why the rise (fall) of the signal Sa is oblique as shown in 1) is because the time axis (horizontal axis) is drawn in an enlarged manner (that is, a high-speed state).

A voltage of threshold 1Iivb is applied to one input terminal of the comparator 32. When this threshold voltage vb is changed, the intersection position of the signal Sa and the threshold value vb changes, so that a signal whose rising edge is delayed as shown in FIG. 4 (2) and (3) is generated from the output of the comparator 32. can get.

[Problem to be solved by the invention]

The delay circuit shown in FIG. 3 as described above has a problem in that there is no linear relationship between the value of the threshold value vb (level value) that controls the delay time and the delay time.

This will be explained with reference to FIG. In order to obtain a delayed signal using the circuit shown in FIG. 3, it is necessary for the rising slope of the signal Sa to cross the threshold value vb somewhere. Here comparator 3
The amplitude of the signal Sa output from 1 is a voltage VH, as shown in FIG. 4 (1), and this voltage VH is constant.

On the other hand, the threshold value vb of the comparator 32 is variable in order to control the delay time. As a result, when the threshold value vb is changed, the overdrive voltage varies in the circuit of FIG. The overdrive voltage is the voltage of the signal Sa applied to the comparator 32 exceeding the threshold value Vb. Fourth
To explain with a diagram, when the threshold value vb = vbl, the overdrive voltage is vl, and when vb = vb2, it is v2.
It is.

Here, the amount of propagation delay of the comparator at -m varies depending on the overdrive voltage. Figure 5 shows the relationship between the overdrive voltage of the comparator and the propagation delay time. As shown in the figure, as the overdrive voltage increases, the propagation delay time decreases, and becomes constant above 100 nV.
At voltages below 100 mV, the delay time increases rapidly. This is thought to be because the comparator operates in the linear region of the amplifier.

Therefore, the delay time of the signal obtained from the comparator 32 does not have a linear relationship with the amount of change in the threshold tIivb, making it difficult to obtain a signal having a desired delay time.

An object of the present invention is to provide a delay circuit that can accurately obtain a desired delay time.

[Means to solve the problem]

In order to solve the above problems, the present invention includes a first means (20) for converting an input signal into a square wave signal and alternately outputting currents fIiI0 and -IO in synchronization with the phase of the square wave signal; A comparator (17) to which the voltage of the capacitor (16) is applied to one input terminal and a threshold value (VB) for controlling the delay time to the other input terminal, and a current source (7) that outputs a current value of 2IO first superimposing means (8) for superimposing the output of
), a second superimposing means (11) for superimposing the output of the current source (12) that outputs the current value (-2IO) and the output of the first means that outputs the current f#(lo); A first diode (9) connected between the output terminal of the first superimposing means and the capacitor, a second diode (10) connected between the output terminal of the second superimposing means and the capacitor, and the first superimposing means One end is connected to the output terminal of fl! ! A third diode (14) to which a potential of (VB+VO) is applied to the end.

[Effect]

In the present invention, the overdrive voltage of the signal applied to the output stage comparator is controlled so that it always remains at a constant value even if the threshold value changes. Therefore, a signal having a delay time corresponding to the magnitude of the threshold voltage VB can be obtained.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an embodiment of the delay circuit according to the present invention, and FIG. 2 is a time chart of each part of the first delay circuit.

In FIG. 1, 20 surrounded by a - dotted chain line is the first means, which converts the input signal Si into a square wave signal, synchronizes with the phase of this square wave signal, and changes the current value to 10 and (Io) to 2. It outputs alternately from two output terminals.

Here, although FIG. 1 shows the currents 11 to 19 flowing through each part and their absolute values, in this specification, if the connection point between the diodes 9 and 10 is A, this point A may be used as necessary. The current flowing toward point A may be expressed as positive, and the current flowing out from point A may be expressed as negative.1For example, one output current l of the first means 20 flows in the direction shown, so current fi! ! (-Io), and since the other output current 16 heads toward point A, it is assumed to be current M Io. Further, the current of the current source 7 is assumed to be 2IO, and the current of the current source 12 is assumed to be (2IO).

The first means 20 includes a comparator 1, an inverter 2,
It is composed of a buffer 3, a switch SWI 8142, and current sources 4 and 5. A dark value pressure V^ is applied to the comparator 1, and this dark value VA is compared with the input signal S1 to convert the input signal Si into a square wave signal. The inverter 2 introduces this square wave signal and controls the switch S-1 on and off using the phase-inverted signal. buffer 3
controls the switch 5142 on and off while keeping the phase of the output square wave of the comparator 1 unchanged. Therefore, the switches SW1 and SW2 alternately perform on/off operations, and the current source 4.5 causes a current value (Io), Io, to flow in the direction shown in the figure.As a result, one output of the first means 20 A current l of (Io) flows from the terminal, and a current l of (Io) flows from the other output terminal. current flows.

Reference numeral 7 denotes a current source, which causes a current of 2IO to flow in the direction shown in the figure.

Reference numeral 8 denotes a transistor, which constitutes superimposing means for introducing the output current 11 of the first means and the output current 2I0 of the current source 7 into the emitter and outputting the superimposed current 12 from the collector. Note that a bias voltage v4 is applied to the base.

Diodes 9 and 10 are connected in series in the direction shown, and are connected between the collectors of transistors 8 and 9.

The transistor 11 constitutes a superimposing means that introduces the output current 16 of the first means 20 and the output current (2IO) of the current source 12 into its emitter, and outputs a superimposed current 17 from its collector. A bias voltage v5 is applied to the base.

17 is a comparator. This 10 input terminal is connected to the connection point A of the diode 9.10, and a capacitor 16 is provided between this 10 input terminal and circuit ground. On the other hand, a voltage source 18 that determines the dark value VB is connected to the input terminal. By controlling the fM voltage VB during this time, the delay time can be determined.

Also, one input terminal of the comparator 17 and the transistor 8
A diode 14 and a voltage source 19 are connected between the collectors of the diode 14 in the direction shown in the figure. The voltage of this voltage source 19 is vO (an arbitrary constant voltage).

Furthermore, a diode 1 is connected to the collector of the transistor 11.
5 is connected in the direction shown in the figure, and a voltage νC is applied to the other end of this diode 15.

The operation of the apparatus shown in FIG. 1 constructed as above will be explained with reference to FIG. 2.

An input signal Si as shown in FIG. 2 (1) is applied to the 10 input terminal of comparator 1, and a dark value VA at a level as shown in FIG. 2 (1) is applied to the - input terminal. There is. Therefore, the comparator 1 outputs a square wave signal as shown in FIG. 2 (2). This square wave passes through the inverter 2 and the buffer 3, and starts from the point Pl, P2 of the square wave in Fig. 2 (9), and then switches the switch S old and
2 is turned on and off alternately.

Examples of this on/off relationship are shown in FIG. 2 (3) and (4).

Now, if the switch SW1 is off and the switch 5142 is on as shown in FIG. 2, then the collector current f2 of the transistor 8 is
= 2IO, and the collector current of transistor 11 is 1
y = lo.

Here, if the cathode side of the diode 14 is set to point B, the potential at point B is (VB + VO).On the other hand, if the terminal of the capacitor 16 is set to 0 point, the voltage at this 0 point (that is, the voltage at the comparator 17 As shown in FIG. 2 (5), the input voltage (input voltage) is lower than the threshold value VB when the switch 5141 is turned off and Sn2 is turned on.

Here, when the threshold i1[1=VB1 by the voltage source 1B, the signal output from the comparator 17 will be explained.

When the switch 5141 is turned off and Sn2 is turned on, the voltage at point B is higher than the voltage at point 0, so the diode 14 is turned off and the current 1 flowing through the transistor 8 is
2 (=2IO) flows through the diode 9. Now, since the voltage VC is applied so that the diode 15 is turned off, the value of the current 15 branched and flowing to the diode 10 side at point A is to. The reason is that the collector current ft of the transistor 11 is 1o as described above.

Therefore, the value of the current 14 that branches off at point A and flows toward the capacitor 16 is lo. That is, the capacitor 16 is charged with the current fii10, and its terminal voltage (comparator 1
7) increases at a constant slope, as shown in FIG. 2 (5).

Then, the potential at point 0 is the threshold 1VB at point 03 in Figure 2 (5).
Exceeds 1. As a result, the output of the comparator 17 is inverted and becomes "IIIGH" as shown in FIG. 2 (6).

On the other hand, the potential at point 0 further increases, and finally the potential at point B<V
When the voltage reaches B+VO), the diode 14 is turned on, and the current 1a (=Io) that has been flowing for charging the capacitor 16 flows to the diode 14 side. That is, 1a=14=To.

Note that the current flowing through the diode 101111 is 1! I am
Still I. It remains as it is.

As a result, in FIG. 1, 1s=15, and the input impedance of the 10 input terminal of the comparator 17 is very high.
There is no current flowing out from the capacitor 16, so the capacitor 16 is held at the voltage at point 24 in FIG. 2(5). That is, the input terminal of the comparator 17 has (Va1
Do not apply a voltage higher than +VO).

In other words, when the threshold value is V81, the overdrive voltage is the voltage vO shown by the diagonal line in FIG. 2 (5).

Thereafter, as shown in FIG. 2 (2), the output of the comparator 1 falls, and at the time point P2, the switch y switch SWI is turned on and Sn2 is turned off, and the t current 12 flowing through the transistor 8 is 12=21°-1°=210-1°=I.

On the other hand, the t current 17 flowing through the transistor 11 is
16+1v=2IO, but since switch 3142 is off, 16=0, so Jv "2IO
It is.

Now, since the voltage VC is set so that the diode 15 is turned off, 17 = 1s = 13 + 1m -, that is, the current flows from the capacitor 16 in the direction 14' shown in Figure 1, and the capacitor 16 is discharged. However, the potential decreases as shown in FIG. 2 (5).

Then, at the 25th point, the threshold ll1vB1 of the comparator 17 is again
, the output of comparator 17 is “10!A”
In this way, the waveform shown in FIG. 2 (6) is obtained from the comparator 17.

Next, by changing the voltage of the voltage source 18, the delay time is shown in Fig. 2 (6).
In order to extract the signal (7) which is different from the signal of
Let's go to B2. The operation in this case is the same as above, the voltage at point B in FIG. Ru.

In other words, in the present invention, even if the threshold voltage VB is set to various values as shown in FIG. 2 [5], the comparator 17
The overdrive voltage applied to is always kept at vO.

As a result, if T is the time when the output of comparator 1 in FIG.
Figure 2 (6)) is obtained, and ■ When the threshold value VB = VB2, the signal with delay time t2 (
Figure 2 (7)) is obtained.

In this case, since the overdrive voltage is constant (vO), the delay time has a linear relationship with the dark value voltage VB.

In this specification, a circuit that accurately delays the rising edge of the delayed signal obtained from the comparator 17 has been described. This is because timing signals such as synchronization signals and control signals generally used in electronic circuits are triggered at the rising edge of the signal. When triggering on a falling edge, see Figure 2 (6), (
The waveform of 7) can be passed through the inverter circuit.

Further, the voltage VC applied to the diode 15 may be set to a value smaller than the minimum voltage that the threshold MVB can take. The voltage VC applied to this diode 15 defines the voltage level VC shown in FIG. 2(5).

[Effects of the present invention]

As described above, according to the present invention, even if the level of the threshold ViVB is changed, the overdrive voltage applied to the comparator 17 is always constant (voltage vO of the voltage source 19). is maintained in a linear relationship. Therefore, an accurate delayed signal can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the delay circuit according to the present invention, FIG. 2 is a time chart of each part of the first circuit, FIG. 3 is a diagram showing a conventional delay circuit, and FIG. 4 is the same as that of FIG. A diagram showing operating waveforms,
FIG. 5 is a diagram showing the relationship between overdrive voltage and propagation delay time. 7.12... Current source, 8.11... Transistor,
9,10°14,15...Diode, 16...Capacitor, 17...Comparator, 18.19...
Voltage source, 20... first means.

Claims (1)

[Claims] First means (20) for converting an input signal into a square wave signal and alternately outputting current values I_O and -I_O in synchronization with the phase of the square wave signal; one input terminal; A comparator (17) to which the voltage of the capacitor (16) is applied to and a threshold value (VB) for controlling the delay time is added to the other input terminal, and the output of the current source (7) that outputs the current value 2I_O. a first superimposing means (8) that superimposes the output of the first means that outputs the current value (-I_O), an output of the current source (12) that outputs the current value (-2I_O), and a current value (I_O); ); a first diode (9) connected between the output terminal of the first superimposing means and the capacitor; and a second superimposing means a second diode (10) connected between the output terminal of the first superimposing means and the capacitor; and a third diode (10) having one end connected to the output terminal of the first superimposing means and a potential of (VB+VO) applied to the other end.
4) A delay circuit comprising: In addition, V_O: arbitrary voltage