JPH01313777A - Detecting system for insulation failure position of printed board wiring pattern - Google Patents

Abstract

PURPOSE:To detect an insulation failure position in a short time and efficiently by setting a group of probe pins as a unit and executing a test between each representative pin, and applying a mask insulation test to the pin in which a failure has been detected. CONSTITUTION:In a device 6 for executing an insulation test by using a grating- like probe pin 1a, one piece of pins for forming a group corresponding to a wiring pattern is set as a representative pin, and by executing successively an insulation test between one piece of the representative pins of each group, and a batch pin which has lumped together the representative pins of all other groups, a failure grating point is detected. Subsequently, the group to which a failure pin belongs is masked successively, and by executing a mask insulation test of one failure pin, and a batch pin which has lumped together all failure pins escept the masked group, a relation between the failure groups is detected. In such a way, an insulation failure of the wiring pattern of the whole surface of the substrate can be detected efficiently in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for detecting the position of insulation failure in a wiring pattern of a printed circuit board.

[Prior art] Printed circuit boards used in electronic computers are large and are equipped with many high-performance IC packages, and defects such as disconnections, short circuits, or poor insulation are absolutely unacceptable in the printed wiring. Not done.

On the other hand, when the printed wiring is completed and no components are mounted, continuity and insulation tests are performed.

3(a) and 3(b) show a prober used for continuity and insulation testing of printed circuit boards. In FIG. 3(a), the prober board 1 is fixed to a suitable base, and the printed circuit board is Probe pins 1a corresponding to No. 2 wiring pattern (not shown) are implanted. The substrate is pushed down by the suppression plate 2 with the insulating plate 3 interposed therebetween, and the probe pins come into contact with the wiring pattern. Each probe pin is connected to a test device 6 via a cable 5 to perform a continuity or insulation test. There are various shapes of wiring patterns on printed circuit boards, so in order to use them commonly, the probe pins should be spaced at intervals corresponding to the size (pitch interval) of the wiring pattern, as shown in Figure (b). The probe pins are implanted corresponding to all of the grid points of α, so that one of the probe pins contacts the wiring pattern of α and α. Note that the large printed circuit boards used in electronic computers are rectangular with sides of ~500 mm, and the wiring pitch is approximately 3 mm, so the number of lattice points, and hence the number of probe pins, is extremely large, approximately 30,000 mm. It is something that reaches a book.

Next, defective wiring patterns and conventional testing methods will be explained with reference to FIGS. 4(a) to 4(e). In Figure (a), Pl-R4 shows an example of a wiring pattern, and probe pins 13 in contact with these are connected to form groups G and -G4.

Figure (b) shows a wiring pattern with a disconnection q, and Figure (C
) is the one in which a short S has occurred between the wiring patterns, and the figure (
Figure d) shows an insulation failure where wiring patterns are connected by a resistor r, and Figure (e) shows a case where three wiring patterns have insulation failure.

A continuity test is performed to detect wire breakage among the defects listed in (1) below. In the continuity test, select an appropriate representative probe pin within each group, store its address and connection information for the group corresponding to each wiring pattern in advance in memory, and use one pin as the base prefecture. Continuity tests are performed between each pin in the group. in this case,
If the number of pins is approximately 30,000, and each group has, for example, 5 pins on average, the maximum number of groups is 6,000.
In reality, it's much less than this. In the case of a continuity test, the test voltage may be a low voltage pulse with an extremely short width, and the test time for one group is completed in about 1 μs on average, so the test can be completed in a maximum of several milliseconds in total.

Next, regarding short circuits or insulation defects between groups (hereinafter collectively referred to as insulation defects), a dichotomous method has conventionally been used as an insulation test. Fig. 5 explains the dichotomy method. First, as shown in Fig. (a), all ROs on the board are targeted, and tests are performed between each group and all other groups at the same time. If a defect is detected (however, the defective group is not specified), at that point all ROs are divided into R1 and R2, and the same test as above is performed on one of them, for example, R1. Here R1
If a defect is detected in , R1 is further divided into R11 and R12 as shown by the solid line in Figure (b), and R1
If no defect is detected in R2, there must be a defect in R2. Therefore, divide R2 into R21 and R22, and perform a similar test on one of the defective ones, for example, R11 or R21, to detect the defect. Figure (c
) and then test for an additional 2 minutes. In the case of the figure, Rt
There is an insulation defect r in R11 and R11l, and the solid line indicates that these were tested. In this way, by sequentially dividing the defective surface into two parts and testing, the defective point r is tracked down and its position detected. Assuming that the number of pins is 30,000, a defect is detected for each of the 11th grid points at the minimum by performing the 2-part division 15 times.

[Problem to be Solved] However, a group has a plurality of chained lattice points, and when the chain is long, testing using the dichotomous method takes a surprisingly long time. FIG. 6 explains this. In the figure, it is assumed that the wiring pattern P on the board is a chain of many lattice points as shown in the figure. Applying the same dichotomy method as shown in Fig. 5 to this, first there is a defect in RO, and then RI R is divided into two.
11, R112..., one lattice point of the defective point is detected by the bisection method in one round, but for the defect existing in the other point which is not subject to the test, it is detected again from the beginning. It is necessary to repeat the test using the dichotomy method. For example, a wiring pattern for a power supply has a chain of several dozen lattice points, and if there is poor insulation with respect to any other pin, it is necessary to repeat the dichotomy several thousand times. On the other hand, in the case of insulation testing, tens of MΩ
In order to detect high insulation resistances up to several hundred MΩ, a test pulse with a high voltage and long duration is used.
100m5 was saved in the 2-minute exam time, and 1.58. Therefore, there is a drawback that it requires a long time of several tens of minutes compared to the above-mentioned several thousand times.

This invention was devised to solve the above-mentioned drawbacks of the dichotomy method. Whereas in the dichotomy method, defects are detected for each lattice point, each lattice point within a group is connected through a chain. Therefore, we focused on detecting insulation defects between case and r points representing each group and changing the data for each case r point, and developed a method that can efficiently detect the location of insulation defects in wiring patterns in a short time. The purpose is to provide the following.

[Means for Solving the Problems] The first method according to the present invention is to detect all of the grid points for a large number of printed wiring patterns formed according to grid points set at regular intervals on the entire surface of the board. A method for detecting insulation defect positions in wiring pattern insulation tests carried out by contacting a prober having a plurality of probe pins corresponding to each wiring pattern, in which one of the probe pins forming a group corresponding to each wiring pattern is designated as a representative pin. The location of each representative pin and the connection information of the probe pins included in each group (hereinafter referred to as 1)
1t, G (referred to as group connection information) is stored in memory in advance, and under the control of the microprocessor, the representative pins of each group are sequentially set as pins, and the representative pins of all other groups are collectively connected to each group. The insulation test between the pins is performed sequentially according to the address order of the representative pins stored in the memory above, and the group connection information stored in the memory is used for the representative pin (defective pin) with insulation failure obtained from this insulation test. , which outputs the position of the defective grid point.

The second method according to the present invention targets all defective pins detected by the insulation test of the first method, sequentially masks the group connection information to which the defective pins stored in memory belong, and Using the pin as a new reference bin, a mask insulation test is performed between the reference pin and all other defective pins excluding the masked group in sequence according to the address order of the representative pins stored in memory. It outputs relationship data between groups.

According to the first insulation defect position detection method described above, the insulation test between the reference pin of any group and the collective pins of all other groups is performed at one time, and The representative pins are sequentially used as reference pins, and one round of testing is completed for all reference pins as many times as the number of groups, that is, the number of representative pins.However, the address of the reference pin where the insulation defect was detected is known. However, since the partner's representative pin or its group is grouped together, it cannot be identified.However, since the test is performed on the representative pin of all groups, the partner's pin remains unknown and all defective pins are detected. The position of the defective lattice point is determined and output based on the group connection information stored in the memory for each of the detected defective pins.

In the above, each defective pin or defective group does not know the other pin or group that will cause insulation failure,
In other words, the relationship between the two has not been specified. To deal with this, defective pins are detected by the first method described above, and then identified by the mask insulation test of the second method of the present invention. Figure 1 (a), which explains the mask insulation test using the following diagram, shows that the defective groups on the entire surface of the board are Pa
In this case, only two of the
It is clear that the relationship with the other party is determined by this method.

Next, Figure (b) shows a case where two or more pairs of PC and Pd and Pe and Pf each have insulation defects, and P
When C is masked and tested using TePd as a standard, Pd is good because of the mask, and it is found that the other party is Pc.

The same goes for Pe and Pf or other pairs, 2
For defects between groups, the relationship between defective pins is identified by sequentially performing masking and insulation tests according to the order of group addresses.

Next, Figure (e) shows the case where Ph and PI have poor insulation with respect to Pg+.
If you mask it and use Ph as the standard, it will be good and Pg will be judged as the opponent, and if you mask Pg and use PI as the standard, it will be good and it turns out that Pg is the opponent. Relationships are identified. However, when the mask or test order is different, the correlation is not always easily determined.

For example, in Figure (d), if Pj is first masked and Pk is used as a reference, it is still defective, but the insulation resistance value changes. Next, when Pj and Pk are masked and PI is used as a reference, it is found to be good for the first time, and it is revealed that Pl has poor insulation from both Pj and Pk. In this way, when three or more are involved, the mutual relationship may not be identified depending on the person to be masked or the order of the tests. In practice, the number of insulation failure groups is often small;
Furthermore, since there are even fewer cases in which three sides are involved, the relationship between the defective groups is finally specified using changes in insulation resistance.

Estimating the time required for the test in the above case, for example, if the maximum number of groups is 6,000 as described above, and the time for one test using the high voltage method is 100 m5, even in this maximum case, the first method , l round takes less than 10 minutes. When the second masking method is then applied, it depends on the number of defective groups, but in the case of a decimal number, it can be completed in a short time.

[Example 2] FIG. 2 shows a flowchart for a test procedure in an example of the method for detecting insulation defect positions of printed circuit board wiring patterns according to the present invention. As explained with reference to FIG. 3(a), the printed circuit board is pressed against a prober wiring pattern in which probe pins are driven into lattice points, and an insulation test is performed by a testing device to which the probe pins are connected. The test equipment shall be equipped with a microprocessor to automatically perform the tests described below.

The flowchart in FIG. 2 consists of (I) for the insulation test between representative pins of each group and (II) for the mask insulation test between defective pins. In the second method, (II) is performed successively after the completion of (I). First, in ■, the connection information of each group and the location of the representative pin are set in memory, and in ■, the first representative pin is set as the reference pin, and all other representative pins are Perform an insulation test between the container and the bulk bottle. The location of the reference pin (defective pin) for which a defect has been detected is memorized in the memory in step ■, and the test is checked to see if all reference pins have been tested. As a standard, repeat the above test,
When all the reference pins are completed, a list of defective T points is created and output by referring to the group connection information for the defective pins stored in the memory in step (3). Next, proceed to the mask insulation test (II). In (2), the memory of the connection information of the defective group first detected in (I) is masked. Next, in step (3), using the representative pin of the group next to the above defective group as a reference, a mask insulation test is performed between it and a bulk bin containing all other defective pins, and the detected good or defective pins are tested. Depending on the conditions,
In (2), the relationship between the defective groups is identified and stored in the memory, and in (2), the memory of the connection information of the group to which the next defective pin belongs is masked. Check the completion of the mask test for all defective pins in [phase],
If the test is not completed, return to step (3) and repeat the same test as above using the next defective pin as a base until all defective pins are completed. After the process is completed, a list of relationships between defective groups is created and output in step (3).

According to the above flowchart (I), insulation defects in the wiring pattern are restored in units of grids.

In addition, (n) specifies the relationship between the reference group and the other group when there are multiple sets of insulation defects between the two groups. However, for insulation defects involving three or more groups, the group relationship can be identified using changes in insulation resistance due to the mask. Regarding the time required for these tests,
I have already mentioned this.

[Effects of the Invention] As is clear from the above explanation, in the method for detecting the position of the insulating stone 14 of the printed circuit board wiring pattern according to the present invention, the probe pin at the point R corresponding to the wiring pattern is connected and in a conductive state. Taking advantage of this, in the first method of insulation testing, the probe pin group is set at the 91st position, and the test is performed between each representative pin. Groups in which a defect is detected are individually identified using connection information stored in memory. lattice points are identified, and the position of insulation failure in the wiring pattern is detected based on this. Furthermore, the second method of mask insulation testing is applied to the probe pins in which a defect has been detected, and the relationship between defective groups is identified and output, which is much more effective than the conventional dichotomous method. The location of insulation defects in wiring patterns on the entire surface of a board can be efficiently detected in a short time, and this has a great effect in contributing to insulation testing of printed circuit board wiring patterns.

[Brief explanation of the drawing]

FIGS. 1(a), (b), (c), and (d) are explanatory diagrams of a method for identifying the relationship between defective groups using a masking method in the insulation defect position detection method of a printed circuit board wiring pattern according to the present invention. Figure 2 is a flowchart of an embodiment of the insulation defect position detection method for printed circuit board wiring patterns according to the present invention, and Figures 3 (a) and (b) are diagrams of the arrangement of test probers and probe pins for wiring patterns in printed circuit board testing equipment. Explanatory diagram, Figure 4 (a), (
b), (c), (d), and (e) are diagrams explaining the wiring pattern and the disconnections, short circuits, and insulation defects that occur therein. Figure 5 is a diagram explaining the insulation test of the wiring pattern using the conventional bisection method. , FIG. 6 is an explanatory diagram of problems in the insulation test using the bisection method shown in FIG. 5. 1...Blow bar, 1B...Probe pin 2...Printed circuit board, 3...Insulating plate, 4...
Pressing plate, 5... Cable, 6... Testing device, ■~■... Flowchart number.

Claims (2)

[Claims] (1). The above-mentioned wiring is performed by contacting a prober having a plurality of probe pins corresponding to all of the grid points to a large number of printed wiring patterns formed according to grid points set at regular intervals on the entire surface of the board. In pattern insulation inspection, one of the probe pins that form a group corresponding to each wiring pattern is designated as a representative pin, and the position of each representative pin and the connection information of the probe pins included in each group (hereinafter simply referred to as group) The connection information (connection information) is stored in memory in advance, and the representative pins of each group are sequentially set as reference pins under the control of a microprocessor, and insulation tests are performed between each group and the representative pins of all other groups. are performed sequentially according to the address order of the representative pins stored in the memory, and for the defective pins detected by the insulation test, the position of the defective lattice point is output based on the group connection information stored in the memory. Features a method for detecting the location of insulation defects in printed circuit board wiring patterns. (2). Targeting all the defective pins detected by the insulation tests performed sequentially above, the connection information of the group to which the defective pins stored in the memory belong is sequentially masked, and the next defective pin is set as a new reference pin. As a result, a mask insulation test between all other defective pins excluding the masked group is performed sequentially according to the address order of the representative pins stored in the memory, and test is performed between the defective pins or defective groups. 2. The method for detecting the position of an insulation defect in a printed circuit board wiring pattern according to claim 1, wherein related data is output.