CN105067992B - The method that chip retrospect is realized by test data - Google Patents
The method that chip retrospect is realized by test data Download PDFInfo
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- CN105067992B CN105067992B CN201510526376.0A CN201510526376A CN105067992B CN 105067992 B CN105067992 B CN 105067992B CN 201510526376 A CN201510526376 A CN 201510526376A CN 105067992 B CN105067992 B CN 105067992B
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Abstract
The present invention relates to a kind of methods that chip retrospect is realized by test data, include the following steps：Chip to be tested is connected by step 1 with test machine progress hardware, to test the chip to be tested；Step 2 is tested using test machine, and in the test data needed for test machine generation, include in the test data with it is each by test chip be in one-to-one unique numeric code；Test data in step 3, read test machine, and realized according to value code corresponding with test chip in test data and chip is traced.The present invention is easy to operate, quickly and effectively can accurately realize the retrospect of chip, wide adaptation range, securely and reliably.
Description
Technical field
The present invention relates to a kind of method, especially a kind of method that chip retrospect is realized by test data, specifically
It is a kind of more suitable for test dies number（Ten thousand or more）And the method for being pin-pointed to specific tube core is needed, belong to chip and chase after
It traces back the technical field of positioning.
Background technology
For ic core chip level testing process, realize that chip retrospect is a required link, otherwise can not carry out
The next step.At present, it is that the software carried by test machine is set to realize chip retrospect, is connected with reference to GPIB communication interface modules
Probe station is connect, by reference to X/Y coordinates to position specific test chip.But if there are GPIB communication mistakes in test process
Or the test machine having does not have corresponding software support that can not then realize that chip traces.
The content of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, one kind is provided and realizes that chip chases after by test data
The method traced back, it is easy to operate, it quickly and effectively can accurately realize the retrospect of chip, wide adaptation range, securely and reliably.
According to technical solution provided by the invention, a kind of method that chip retrospect is realized by test data, the chip
Retroactive method includes the following steps：
Chip to be tested is connected by step 1 with test machine progress hardware, to be surveyed to the chip to be tested
Examination；
Step 2 is tested using test machine, and in the test data needed for test machine generation, the test data
Comprising with it is each by test chip be in one-to-one unique numeric code；
Test data in step 3, read test machine, and according to value code corresponding with test chip in test data
It realizes and chip is traced.
In the step 2, when treating test chip test, first determine primary data, and pass through needing test chip
During test, accumulated counts are carried out to primary data using numerical value summation, to obtain and be in each one a pair of by test chip
The unique numeric code answered.
Advantages of the present invention：Chip to be tested is connected with tester hardware, and test data is generated in test machine, test
Include in data with it is each by test chip in one-to-one unique numeric code, can be realized pair using the value code
Chip is traced, easy to operate, quickly and effectively can accurately realize the retrospect of chip, wide adaptation range, securely and reliably.
Description of the drawings
Fig. 1 is the flow chart of fuse programming of the present invention test.
Fig. 2 carries out the verification whether correct flow chart of programming for the present invention.
Specific embodiment
With reference to specific drawings and examples, the invention will be further described.
In order to the quickly and effectively accurate retrospect for realizing chip, accommodation is improved, chip retroactive method of the present invention includes
Following steps：
Chip to be tested is connected by step 1 with test machine progress hardware, to be surveyed to the chip to be tested
Examination；
When it is implemented, the hardware of chip to be tested and test machine connect, generally refer to by the test port of test machine with
Test interface plate（Device Interface Board, DIB）Connection, test interface plate are connected with probe card, and probe card is with treating
Test chip connects, to realize test machine to the data transmission between chip to be tested and measurement.Chip and test machine to be tested
Specific hardware connection procedure is known to those skilled in the art, and details are not described herein again.
Step 2 is tested using test machine, and in the test data needed for test machine generation, the test data
Comprising with it is each by test chip be in one-to-one unique numeric code；
In the embodiment of the present invention, test chip is treated using test machine according to test request and is tested, it is specific to test
Process is known to those skilled in the art.In test, test data can be generated in test machine.
When it is implemented, when treating test chip test, first determine primary data, and pass through survey needing test chip
During examination, accumulated counts are carried out to primary data using numerical value summation, to obtain and be in each to correspond by test chip
Unique numeric code.I.e. after primary data is determined, using primary data as at first by the value code of chip testing, with
Afterwards immediately by test chip, corresponding value code adds up for the enterprising line number value of primary data.
Test data in step 3, read test machine, and according to value code corresponding with test chip in test data
It realizes and chip is traced.
Usually, test data fixed storage is in the position that test machine is specified, due to including test chip in test data
Value code, according to value code and primary data, can realize the retrospect to chip.
It is further described below with the process of fuse test come the specific implementation process to the present invention.
As depicted in figs. 1 and 2, the add up process of test and verification of fuse is：
Step 1）, fuse add up programming test before need to judge that the acupuncture treatment of all fuse pins is good, wherein fuse can be managed
It solves and selects position for address code or function.Continue in next step, to add up without fuse if acupuncture treatment is bad if acupuncture treatment is good
Programming.
Step 2）, transfer the initial data of coding file, initial data is defined as the integer more than or equal to zero, file data
It is placed in specific file, such as D:\ CZ\ XX_1SITE_V01 \ Trim\ trim.txt.
Step 3）, directly wanting to apply suitable voltage between the fuse of programming and ground wire, the electric current of generation to fuse into
Row programming, the voltage swing of application need to obtain an appropriate value, the programming voltage of the test software of this paper by debugging
For 3.6V.
Step 4）, programming can generate unique numeric code after completing, and carry out validation test to programming result.It needs first
Whether the fuse for verifying institute's programming is correct, it is necessary to all fuse PAD meet VCC 10K pull-up resistors by relay, verifies
Whether when fusing, closed pair answers position relay, measures whether fuse PAD is high level i.e. voltage value.
Step 5）, pass through unique value code and trace corresponding test chip.
Claims (1)
1. a kind of method that chip retrospect is realized by test data, it is characterized in that, the chip retroactive method includes following step
Suddenly：
Chip to be tested is connected by step 1 with test machine progress hardware, i.e., connects the test port of test machine and test interface plate
It connects, test interface plate is connected with probe card, and probe card is connected with chip to be tested, to realize test machine between chip to be tested
Data transmission and measurement, to test the chip to be tested；
Step 2 is tested using test machine, and is included in the test data needed for test machine generation, the test data
It is in one-to-one unique numeric code with each chip by test；
In the step 2, when treating test chip test, first determine primary data, and pass through test needing test chip
When, accumulated counts are carried out to primary data using numerical value summation, to obtain and be in each to correspond by the chip of test
Unique numeric code；
Test data in step 3, read test machine, and realized according to value code corresponding with test chip in test data
Chip is traced；
The add up process of test and verification of fuse is：
Step 1）, fuse add up programming test before need to judge that the acupuncture treatment of all fuse pins is good, wherein fuse programming understand
It is selected for address code；Continue if acupuncture treatment is good in next step, if having an acupuncture treatment it is bad if add up programming without fuse；
Step 2）, transfer the initial data of coding file, initial data is defined as the integer more than or equal to zero, and file data is placed on
In specific file；
Step 3）, directly wanting to apply suitable voltage between the fuse of programming and ground wire, the electric current of generation burns fuse
It writes, the voltage swing of application needs to obtain an appropriate value by debugging, and the programming voltage of test software is 3.6V；
Step 4）, programming can generate unique numeric code after completing, and carry out validation test to programming result；Firstly the need of testing
Whether the fuse of card institute programming is correct, it is necessary to all fuse PAD meet VCC 10K pull-up resistors by relay, verifies whether
During fusing, closed pair answers position relay, measures whether the corresponding PAD of the fuse is high level i.e. high-voltage value；
Step 5）, pass through unique value code and trace corresponding test chip.
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| CN201510526376.0A CN105067992B (en) | 2015-08-25 | 2015-08-25 | The method that chip retrospect is realized by test data |
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| CN201510526376.0A CN105067992B (en) | 2015-08-25 | 2015-08-25 | The method that chip retrospect is realized by test data |
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| CN105067992B true CN105067992B (en) | 2018-06-05 |
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| CN107808831B (en) * | 2017-11-10 | 2021-03-16 | 上海华岭集成电路技术股份有限公司 | Whole-course traceable semiconductor test data recording method |
| CN108490337A (en) * | 2018-03-14 | 2018-09-04 | 广州视源电子科技股份有限公司 | Board test method, system, readable storage medium storing program for executing and computer equipment |
| CN110082666B (en) * | 2019-04-10 | 2022-02-22 | 杭州微纳核芯电子科技有限公司 | Chip test analysis method, device, equipment and storage medium |
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| CN101210952A (en) * | 2006-12-27 | 2008-07-02 | 中茂电子(深圳)有限公司 | Multi-test point semiconductor test machine station automated setting method |
| KR101131560B1 (en) * | 2010-07-15 | 2012-04-04 | 주식회사 하이닉스반도체 | Non-Volitile Memory Device For Performing Wear-Leveling and Method Thereof |
| CN103165405A (en) * | 2011-01-27 | 2013-06-19 | 北京确安科技股份有限公司 | Mutli-dimensional variable code real-time generation method through general purpose interface bus (GPIB) interface |
| CN104678287B (en) * | 2015-01-30 | 2018-10-16 | 上海华岭集成电路技术股份有限公司 | Chip UID maps wiring method |
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