JPH01312661A - Multi-processor system - Google Patents

Abstract

PURPOSE:To effectively use an address area, and in addition, to independently use a processor by not connecting only a strobe line between respective bus modules directly, and connecting it through a gate to connect it selectively according to the address area. CONSTITUTION:The linkage circuit of a shared part is located between control lines 8, 9, that is, the strobe line to perform the read and the write of a memory. At the time of using a specified address, a selector 11 outputs an address select signal 12 according to the address from a multi-master system bus 7, and it is ANDed together with a signal from the control line 9 by an AND gate 13. Because the output of the AND gate 13 is outputted to the control line 8 through a buffer 14 to drive the shared part, access from the processor 2 to the processor 1 comes possible, and linkage between the processors 1, 2 can be easily performed. Besides, because the exclusive area of the processors 1, 2 can be used by the same address, the address area can be used effectively, and in addition, the processors 1, 2 can be used independently.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a multiprocessor system.

In particular, the present invention relates to a system bus suitable for mounting a plurality of bus module groups within one unit.

[Conventional technology]

Conventionally, regarding multi-mask system buses, IEE, microcomputer system bus,
Standard, 796 bus (IEEE.

MICRO CONPUTER, SYSTEM [SUS,
5TANDARD (796BUS)).

[Problem to be solved by the invention]

In the above conventional technology, when one unit has multiple bus module groups and each bus module group has a dedicated area and a common area used by the entire unit, the address area is dedicated to the first path module group on the address map. area, the second bus module group exclusive area, the seventh bus module group exclusive area, and the first to seventh bus module group common area, but since the address map has a finite depth, If each area occupied a large address range, there was a problem that it could not fit on the address map.

The purpose of the present invention is to provide a multiprocessor system in which the dedicated areas of the first to seventh bus module groups are given the same address and the address areas can be used effectively.

[Means to solve the problem]

The above purpose is to connect a plurality of bus modules to a common bus consisting of an address signal line, a data signal line, and a strobe signal line indicating that the address line or data line is valid, and each bus module has one or more bus masters and one In a multi-master bus system consisting of the above bus slaves, the strobe lines between each bus module are not directly connected, but are connected via gates that are selectively connected depending on the address.The output from the selector at a specific address is By providing a circuit in which the AND output of the bus module and the strobe signal from the bus module that does not have a common area is output to the strobe signal line of the bus module that has a common area by a buffer for driving the common area. achieved.

[Effect]

A circuit that performs linkage between multiple bus module groups, which is installed on a control line that reads and writes memory between multiple bus module groups, outputs from the selector only at a specific address and controls from the bus module group that does not have a common area. Since the signal is output to the control line of the bus module group that has a common area, the dedicated areas of multiple bus module groups can be used at the same address except at specific addresses, so the address area cannot be used effectively. and.

The bus module group can be used independently.

Further, at the time of a specific address, linkage between the bus module groups can be performed using the common area of the bus module groups.

〔Example〕

FIG. 1 is a block diagram of a multiprocessor having common parts to which the present invention is applied.

An embodiment of the present invention based on the IEEE79G bus will be shown below.
CROCONPUTIER, SYSTEM BUS, 5T
(See ANDARD) In this embodiment, there are two types of bus modules: processors 1 and 2. Each processor has a processing unit 3, 5 memory 4, 6, connected to it by a multi-master system bus 7, and a common part linkage circuit between control lines 8, 9, which are strobe lines for reading and writing the memory. The memories 4 and 6 are read and written by signals from the processing devices 3 and 5 except at specific addresses.
At the time of a specific address, the selector 11 outputs an address select signal 12 based on the address from the multi-mask system bus 7, which is ANDed with the signal from the control line 9 by an AND gate 13. By outputting the output of the AND gate 13 to the control line 8 via the buffer 14 that drives the common part, the processor 2 can access the processor 1, and the linkage between the processors 1 and 2 is established. It's easy to do. In addition, the processors 1 and 2
Since the dedicated areas of 1 and 2 can be used at the same address, the address areas can be used effectively and the processors 1 and 2 can be used independently.

FIG. 2 is an address map diagram of a multiprocessor to which the present invention is applied.

In this embodiment, in the configuration shown in FIG. 1, by providing the common part linkage circuit 10, the address area can be divided into the area dedicated to processor 1, the area dedicated to processor 2, and the area common to processors 1 and 2 on the address map. There is no need to sequentially allocate the address areas to the processors 1.2 and the dedicated areas of the processors 1.2 can have the same address, which has the effect of making it possible to use the address areas effectively.

〔Effect of the invention〕

According to the present invention, since the dedicated areas of two types of processors can be used at the same address, the address areas can be used effectively and the processors can be used independently. Furthermore, there is an effect that linkage between the processors can be easily performed.

Furthermore, since the processors can be connected without any changes to the hardware or software, a plurality of processors can be installed in one unit, which has the effect of making it more compact.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multiprocessor having common parts according to an embodiment of the present invention, and FIG. 2 is an address map diagram of the multiprocessor. 1, 2... Processor, 3, 5... Processing device, 4,
6...Memory, 7...Multi-master bus, 8,9.
...Control line, 10...Common part linkage circuit, 11
...Selector, 12...Address select signal, 1
3...AND gate, 14...Buffer that drives the common part. Figure 1 XO...θ 〆FF...F Figure country, 3 moves 1 Shu \

Claims (1)

[Claims] 1. A plurality of bus modules are connected to a common bus consisting of an address signal line, a data signal line, and a strobe signal line indicating that the address line or data line is valid, and each bus module has one or more bus masters and one or more bus A multi-processor system comprising a multi-master bus system comprising bus slaves, wherein only the strobe lines between bus modules are not directly connected, but are connected via gates that are selectively connected based on addresses.