JPH01312623A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain objective screens with comparatively easy control even if the screens of more than three are displayed in prescribed priority by outputting picture data in accordance with priority written in a control register. CONSTITUTION:If first to fourth priority circuits 10-40 are provided and a code showing that the first screen has first priority is outputted from the control register 70, for example, when there are four screens, for example, the first priority circuit 10 is designated. Picture data in the first screen is read from an element, into which picture data of the first screen in the first priority circuit 10 is written, is transmitted to a picture display/processing circuit and displayed on a television screen. When a code that the second screen has second priority is outputted from the control register 70, the second priority circuit 20 is designated and picture data in the second screen of the second priority circuit 20 is displayed on the television screen. Thus, the first screen of first priority is displayed in a front row, and then the screen of second priority is displayed at the backward of the first screen.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and more particularly to image display control for displaying a plurality of images according to priority order.

[Prior Art] For example, when displaying a first screen displaying mountains and a second screen displaying clouds and the sun,
For example, the 14th screen that displays the first screen at the frontmost side of the display screen! ! If you want to display the second screen on the back side of the first screen as the first priority, and simultaneously display it on the color cathode ray tube to obtain an image where part of the cloud and sun image is hidden by the mountain image. There is.

In the above example, one of the two screens is displayed preferentially, but there may also be cases where it is desired to display three or more screens on a color cathode ray tube with ff1ffi.

As a device for selecting screens in order of priority, a circuit as shown in FIG. 5 has conventionally been used. In FIG. 5, the image data of two screens S01 and SC2 are input to switches 101 and 102, and by turning these switches 101 and 102 on or off with a signal indicating the priority order, The image data of the other side is obtained at the output terminal 103.

[Problems to be Solved by the Invention] This conventional circuit can only prioritize two screens, and there is a problem that the control becomes complicated when displaying on three or more screens in order of priority. there were.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and provide an image processing device that can obtain a desired screen with relatively simple control even when three or more screens are displayed in a predetermined priority order.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention includes a control register in which data indicating the priority for each screen is written, and a control register corresponding to the display priority,
Each screen has an element that temporarily stores image data,
The present invention is characterized by comprising a priority circuit that outputs image data according to the priority order written in the control register.

[Operation] A code indicating each screen and a code indicating priority are written in the control register. On the other hand, as priority circuits, for example, when there are four screens, first to fourth priority circuits are provided, and each priority circuit is provided with an element for writing image data of each screen. For example, when a code indicating that the first screen has the first priority is output from the control register, the first priority circuit is designated, and the image data of the first screen in this first priority circuit is written. The image data of the first screen is read out from the elements in the screen, sent to the image display processing circuit, and displayed on the television screen. When a code indicating that the second screen has the second priority is output from the hunt roll register to ξ and others, the second priority circuit is designated and the image data of the second screen of the second priority circuit is written. Image data is output from the element, sent to a display processing circuit, and displayed on the television screen.

In this way, the first screen with the first priority is displayed on the TV screen, apparently in front of the top, and then the screen with the second priority is displayed behind the first screen on the TV screen. be done.

[Example] In the following example, as shown in FIG.
The case of displaying on the RT screen will be explained.

In FIG. 1, 1. 2. 3. 4 is a selector provided corresponding to each screen SCI to SC4, which temporarily stores the image data of each screen as data in units of dots on the CR7 display screen, and selects whether the data indicates a pixel or whether it is transparent. Selectively output the data shown.

10, 20, 30, and 40 are the first to fourth priority circuits using 3-state buffers, and each priority circuit corresponds to each screen! l? It has buffers 11-14.21-24.31-34.41-44 corresponding to C1-SC4, and the buffers 11, 21.31.41 are connected to the output terminal of the selector l, and the buffer 12 , 22.
32 and 42 are connected to the output terminal of selector 2. Other buffers 13.23, 33, 43, 14, 24.34.
44 is also connected to the output terminal of each selector 3, 4 in the same manner as above.

Reference numeral 50 denotes a display data determination unit, and determination circuits 51, 52, 53, and 54 determine whether the data is image data or transparent data.
are connected to the output terminals of the buffers 11 to 44 of each priority circuit 10, 20°30.40, respectively, and each judgment circuit 5F to
54 outputs 1 when the data output from each of the buffers 11 to 44 is image data, and outputs 0 when it is transparent data.

61 to 65 are three-state buffers, and each buffer 62 to 64 corresponds to the first to fourth priority circuits 10 to 64, respectively.
It receives the output data from each of the 40 buffers and outputs the image data in priority order according to the clock signal.

Reference numeral 70 is a screen control register, and each priority circuit to
, 20, 30.40.

The priority setting register 80 has 12 stages from DO to Dll as shown in FIG.

D4 to D3 store data indicating the presence or absence of screens SCI, SC4, and D4 to Dll store data indicating the priority order of each screen in pairs of two stages each. That is, stages D4 and D5 have the fourth priority (lowest priority), D(3, D7 have the third priority, D8, D9
corresponds to second priority, and DIO and Dll correspond to first priority (top priority).

On the other hand, codes are assigned to each screen SCI, SC2, SC3, and SC4 as follows.

0O for SC1 0I for 3C2 1O for SC3 11 for 3C4 For example, if 00 is written in stages DIO and Dll, the screen SCI will have first priority, that is, it will be displayed at the top and in the foreground on the CRT screen. Show that.

Output terminals 5Q to 8Q and IQ' to 4Q' corresponding to D4 to Dll of the control register 70 are each 2
Multiplexer 71.72 IA, IB, 2A' in pair 4
, 2B', 3A, 3B, 4A.

Connected to 4B human power, the output terminal is each priority circuit 10°20
．． 30. It is connected to the control input terminal of each buffer 11-44 of 40.

In the above configuration, when the code O1 indicating the second screen SC2 is applied to the stages DIO and Dll of the control register 70, 01 is applied to the terminals 4A and 4B.
An output is generated at the output terminal Y5 corresponding to the second screen SC2 of the multiplexer 72, and this output is applied to the buffer 12, so that the image data in the buffer 12 is read out with priority. The connections between the output terminals of the multiplexers 71 and 72 and each of the buffers 11 to 44 are shown in FIG.

The output terminals of the control register 70 corresponding to the LD3 stages without DO are connected to the selection inputs of the selectors 1 to 4.

In the apparatus having the above configuration, if the contents shown in FIG. 4 are set in the control register 70, the first priority circuit 10 will have screen SC2 display data,
The second priority circuit 20 has SC3 display data, and the third priority circuit 30 has transparent data (Do in the control register is
0", transparent data is selected.), and the SC4 display data flows into the fourth priority circuit 40.

Each display data that has passed through the priority circuit is sent to the judgment circuit 5 in Figure 1.
1 to 54 and buffers 61 to 65. Determination circuits 51 to 54 determine whether the incoming display data is color data or transparent data, and input the result to register 60.

The register 60 determines in which priority circuit the data to be displayed is located in the order of first priority, second priority, third priority, and fourth priority, and finally in the four buffers 62 to 65 in FIG.
and 61. The enabled display data is sent to the display circuit as the display data shown in FIG.

All from the 1st priority to the 4th priority are transparent data (for example, all '0' in control register DQ-D3)
is set), the buffer 61 in FIG.
is selected by the register 60, and transparent data is sent to the display circuit as display data.

Note that details of the display data determining circuit 50 shown in FIG. 1 are shown in FIG. 2.

By the above-mentioned operation, the image on the second screen SC2 is given the highest priority, that is, the image on the TV screen is displayed on the top of the screen without being hidden by other screens, and then the third screen SC3 is given the second priority. They are displayed in order, that is, immediately after the second screen S02.

[Effects of the Invention] As detailed above, according to the present invention, multiple screens can be arbitrarily prioritized according to the data input to the control register and displayed in the priority order group. The above screens can also be displayed in priority order.

Furthermore, since multiple screens can be handled independently, it is possible to create a three-dimensional effect on the screen (video).

Furthermore, since 0N10FF of drawing data is possible, images are rich in variety.

Furthermore, by simply creating a screen control register, each independent screen can be handled freely, making it easy to assign priorities.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of the display data determining section of the circuit shown in FIG. 1, and FIGS. 3 and 4 show specific examples of control registers. FIG. 5 is a diagram showing an example of a display screen, and FIG. 6 is a circuit diagram showing an example of a conventional priority circuit. 10.20, 30.40...Priority circuit 50...Display data determination unit 70...Control register Patent applicant Ricoh Co., Ltd. Agent Patent attorney: 1 person, Haka Ue, Figure 3, Figure 4 Figure 6

Claims (1)

[Claims] (1) A control register in which data indicating the priority order for each screen is written, and an element that is provided corresponding to the display priority order and temporarily stores image data for each screen; An image processing device comprising: a priority circuit that outputs image data according to a priority order.