JPH01311477A - Tape reproducing device of helical scan type - Google Patents

Abstract

PURPOSE:To set the output voltage level of a generation circuit that is the output of a second loop without depending on the detected result of relative speed in the locked state of a first control loop that is the state where a signal exists and to prevent repulsion between the first and second control loops from being generated by detecting the presence/absence of the signal obtained from a head, and lowering the gain of the second control loop when the signal exists. CONSTITUTION:The level of the signal RF from an input terminal 11 is detected at a level detection circuit 24, and a hold request signal which holds a bias voltage against a bias voltage generation circuit 21 in the state where the signal exists is generated. The title device is constituted in such a way that the output from the head lowers the gain of an APC loop 22 by the output of the circuit 21 in the state where an APC loop 16 with the presence of the signal is locked. And by lowering the gain of the APC loop 22, the bias voltage level is prevented from being affected on the APC loop, and the repulsion of the forces of the APC loops 16 and 22 can be prevented from being applied by the deviation of a reproducing data rate due to an azimuth effect, thereby, an exact data extraction clock can be generated.

Description

Detailed Description of the Invention [Purpose of the Invention (Industrial Application Field) The present invention relates to a helical scan type tape playback device such as a rotary head type digital audio recorder, etc. This invention relates to an improved device that allows good data reproduction even in the reproduction state.

(Prior Art) As is well known, in the field of audio equipment, information signals such as audio signals are processed using PCM (Pulse Code Modulation) technology in order to record and reproduce information with as high density and high fidelity as possible. Convert it to digitized data and record it on a recording medium,
Digital recording and reproducing systems that reproduce this information are becoming popular.

Among these, those that use magnetic tape as a recording medium are called digital audio tape recorders.
For example, there are fixed head types with multiple heads arranged in the width direction of the tape, and rotating head types that perform helical scanning by winding the tape around a cylindrical drum with heads installed on the circumference. There is something.

Specifically speaking, a rotating head type digital audio recorder has a cylindrical drum with a pair of heads A and B supported outward from each other with the rotation center of the drum in between. The tape is brought into contact with a certain slope over a quarter of the circumference.

Then, by rotating and running the drum and tape at a constant speed, the tape has heads A,
Tracks corresponding to B are alternately formed with a constant slope. In this case, heads A and B are supported by the drum at azimuth angles of +20' and -20', respectively, with respect to the track forming direction.

Therefore, in the tape playback state, head A.

The signal obtained by tracing the tape by Head B is obtained alternately and intermittently, and heads A and B are made less susceptible to the influence of data recorded on tracks adjacent to the track to be traced by themselves. being done.

After that, in the digital audio recorder, the signals obtained from each head A and B during tape playback are transferred to the PLL.
The signal is supplied to an APC (automatic phase control) loop having a (phase locked loop) configuration to generate a data extraction clock PLCK for extracting reproduced data, and data is reproduced based on this clock PLCK.

Here, FIG. 15 shows the data format recorded on one track of a tape in a rotary head type digital audio tape recorder. That is, 1
One track consists of 196 blocks.

Note that one block consists of 32 symbols, and one symbol consists of 8 bits. And in the center
The 128 blocks are a data area in which PCM digitized data is recorded, and both sides of this data area are control data areas.

Among these, the control data area on the left side of the data area in FIG. Amble data PA, 3 blocks of IBG data, 5 blocks of ATF data, 3 blocks of IBG data and 2
PLL data of each block is recorded.

In addition, in the control data area on the right side of the data area in FIG. 15, 11 blocks of margin data MA
RGIN, 1 block postamble data PA, 8
Block subcode data 5UB-2, 2 blocks of PLL data, 3 blocks of IBG data, 5 blocks of ATF data, and 3 blocks of IBG data are recorded, respectively.

Furthermore, digitized data is recorded in the data area after being converted from 8 bits to IO bits and NRZ (non-return to zero) modulated. Further, the subcode data 5UB-1 and 5UB-2 are address information indicating the song number, absolute time, and the like. Furthermore, the PLL data is the subcode data 5UB-1, 5UB-2.
This is an information signal for generating the data extraction clock PLCK.

In this way, in the digital audio recorder described above, address information indicating the track number, absolute time, etc. is recorded on the tape, so the tape is run at a higher speed than the normal playback speed and the desired playback speed is recorded. Even in the so-called search state, in which recorded information is searched at high speed, it is necessary to read data recorded on tape.

By the way, if only the running speed of the tape is changed while the rotational speed of the drum is held at the same constant value as during normal playback, the relative speed between the head and the tape will change.
As shown in the figure, the playback data rate begins to change. In FIG. 16, FF indicates the characteristic when the tape is fed in the forward direction, and REW indicates the characteristic when the tape is fed in the reverse direction.

Further, in the figure, R is the playback data rate, RO is the playback data rate during normal playback, ■ is the tape speed, and VO is the tape speed during normal playback.

In this case, in order to read the data recorded on the tape, in order to correspond to the change in the reproduction data rate, the frequency characteristics of the signal reproduction system such as the APC loop and waveform equalizer must be adjusted to the reproduction data rate. It is necessary to make it follow the changes in

That is, during tape playback, the first
As shown in FIG. 7(a), signals are obtained alternately and intermittently with no-signal portions in between.

Therefore, as shown in FIG. 17(b), the APC loop is in a locked state in which it oscillates in synchronization with the reproduced data rate when there is a signal, and in a free-running state when there is no signal.

In this case, the difference between the oscillation frequency in the free-running state and the playback data rate when a signal is present needs to be within the capture range of the APC loop. When the data rate changes, it becomes necessary to make the oscillation frequency of the APC loop in a free-running state during the no-signal period follow the reproduced data rate.

On the other hand, since the relative speed between the head and the tape is uniquely determined by the rotational speed of the drum and the running speed of the tape, it is necessary to It has been proposed to read data recorded on a tape in a search state without changing the frequency characteristics of the signal reproduction system by controlling one or both of the running speeds of the tape.

However, with the means for keeping the relative speed between the head and the tape constant, as shown in FIG. 18(a), due to differences in the rise characteristics of the drum rotation speed and tape running speed,
As shown in FIG. 4B, variations may occur in the reproduction data rate ratio, that is, in the relative speed between the head and the tape.

Generally, the capture range of the APC loop is a few percent, so if the relative speed varies to the extent that it exceeds this pull-in range, the APC loop will not be locked and the data extraction clock PLCK will not be generated.
This causes the inconvenience that data reproduction cannot be performed.

Therefore, conventionally, an AFC (automatic frequency control) loop that detects the relative speed between the head and the tape (equivalent to the playback data rate) and controls the free-running frequency of the APC loop based on the detection result has been added to the APC loop. It has been considered that the free-running frequency can be added to follow the playback data rate.

FIG. 19 shows a conventional APC loop to which such an AFC loop is added. That is, numeral 11 in the figure is an input terminal to which signals RF obtained from each head A and B are supplied. The signal RF supplied to this input terminal 11 is
The phase comparator 12 generates a voltage controlled oscillator (hereinafter referred to as VCO).
) 13, and its phase difference component is supplied to an LPF (low pass filter) 14.

This LPF 14 generates a voltage signal corresponding to the phase difference component, and this voltage signal is applied as a control voltage to the VCO 13 via the adder circuit 15, whereby the APC loop 16 is formed here. be done. Then, the output of vC013 is the data extraction clock P
It is taken out from the output terminal 17 as LCK.

Here, the output of the VCO 13 is supplied to a clock detection circuit 18 to detect, for example, the cycle of the data extracting clock PLCK, and the detection result is supplied to one input terminal of the comparison circuit 19. The detection result from the relative speed detection circuit 20 is supplied to the other input terminal of the comparison circuit 19.

This relative speed detection circuit 20 detects the relative speed between the head and the tape, that is, the reproduction data rate. Means for detecting this relative speed can be roughly divided into means for detecting from the rotation speed of the drum and running speed of the tape, and means for detecting from the rotation speed of the drum and the running speed of the tape, and means for detecting the reproduction frequency of a signal having a known frequency such as an ATF pilot signal recorded on the tape. There are three types of methods: means for detecting the number of envelopes of the reproduced signal RF caused by the head crossing a plurality of tracks;

In this explanation, it is assumed that the relative speed detection circuit 20 detects the reproduction cycle of the ATF pilot signal recorded on the tape, that is, the second means described above.

The comparison circuit 19 has a data extraction clock PLCK.
Compare the cycle of and the regeneration cycle of the ATF pilot signal,
The bias voltage generation circuit 21 generates a signal corresponding to the difference component.
Output to. This bias voltage generation circuit 21 generates a bias voltage corresponding to the difference component, and this bias voltage is added to the output voltage of the L P F 14 by the addition circuit 15, so that the AFC loop 22
is formed.

Therefore, in the high-speed search state, when there is no signal, V C
The free-running oscillation frequency of 013 is controlled to correspond to the relative speed, and a good data extraction clock PLCK can be obtained even if the relative speed changes.

By the way, in the digital audio chip recorder, as mentioned above, two heads A and B are installed with azimuth angles of +20' and -20°, respectively, and the tracks corresponding to each head A and B are the same. Azimuth is recorded in angle.

Here, in the high-speed search state, as shown in FIG.
For example, with respect to +azimuth tracks T+ and -azimuth tracks T-, which are alternately formed on the tape 23 running in the direction of arrow A, the +azimuth head moves in the direction of arrow B as shown by the dotted line in the figure. Trace the track and reverse azimuth track alternately. In this case, the level of each signal RF obtained from heads A and B is high when tracing the same azimuth track, and low when tracing the opposite azimuth track.
C loop 1G will be drawn into the playback data rate of the same azimuth track.

By the way, when the heads A and B cross the +azimuth track and the -azimuth track during high-speed search, as shown in FIG. A deviation occurs in the reproduction data rate, 172, when the head traces the -azimuth track.

The deviation in the reproduction data rate due to this azimuth effect is proportional to the tape running speed, as shown in FIG. 22, and is approximately ±2% when the tape is running at 200 times the normal tape running speed. Therefore, as shown in FIG. 23(a) from the azimuth and -azimuth heads, while reproduction signals are being obtained alternately and intermittently, the free-running oscillation frequency of V C013 and the reproduction data rate are A difference occurs as shown in FIG. 2(b).

Here, if the deviation that occurs in the playback data rate due to the above-mentioned azimuth effect is compensated only by the pull-in ability of the APC loop 16, this pull-in ability has a quantitative limit of about several percent as described above. , 200
The deviation of ±2% at double speed cannot be called a small value.

In particular, when absorbing this deviation depends on the pull-in ability of the APC loop, the accuracy of the circuit components of the APC loop 16,
In addition to improving various characteristics such as temperature characteristics and aging, it is necessary to improve the accuracy of the AFC loop 22 to control the free-running frequency of the VCO 13 and the drum rotation control unit to keep the reproduction data rate constant. The problem arises that it needs to be improved.

Also, the deviation of the playback data rate due to the azimuth effect is
If the relative speed becomes larger than the detection accuracy, a problem arises in that the forces acting on the AFC loop 22 and the APC loop 16 conflict with each other. That is, the AFC loop 22 is provided to make the frequency of the data extraction clock P L CK correspond to the detected value of F0 vs. speed. On the other hand, the APC loop IB functions so that the frequency of the data extraction clock PLCK follows the actually obtained reproduction data rate.

Therefore, as shown in FIG. 24(a), when there is no signal output from the head, the APC loop 1B does not operate, so the oscillation frequency of V C013 is determined based on the detection result of the relative speed detection circuit 20. controlled.

At this time, the oscillation frequency of the V CO 13, the control voltage applied to the V CO 13, and the bias voltage output from the bias voltage generation circuit 2■ are shown in FIG. 24(b),
As shown in (c) and (d), fl and V, respectively.
l, Vl'.

Then, at time TI, for example, from the +azimuth head, the second
As shown in Figure 4(a), when the reproduced signal is obtained, the AP
The operation of the C loop 16 is started. In this case, the APC loop 16 operates to lower the control voltage below vl, that is, to lower the oscillation frequency of the V CO 13 below fl, due to the playback data rate deviation due to the azimuth effect described above, and when the predetermined pull-in time t1 has elapsed. It becomes locked at time T2.

At this time, since the oscillation frequency of the AFC loop 22c and the vCO 13 has become lower than the value corresponding to the detection result of the relative speed detection circuit 20, that is, fl, the bias voltage is increased to increase the control voltage. Then, at time T3 when the level of the bias voltage becomes high enough to exceed the pull-in range of the APC loop 1G, the APC loop 16 enters an unrotter state, making data reproduction impossible.

(Problems to be Solved by the Invention) As described above, in the conventional helical scan type tape playback device, the azimuth effect causes deviations in the playback data rate of the signals obtained from each head, resulting in good data playback. The problem is that it becomes impossible to do so.

Therefore, the present invention has been made in consideration of the above circumstances, and is an extremely good helical scan method that can compensate for deviations in the playback data rate due to the azimuth effect and perform accurate data playback in high-speed tape playback conditions. The purpose of the present invention is to provide a tape playback device.

[Structure of the Invention] (Means for Solving the Problems) A helical scan type tape playback device according to the present invention winds a tape around a rotating drum in which a plurality of heads are installed with mutually different azimuth angles, and rotates the rotating drum. The object of this invention is to obtain intermittent signals by selectively bringing a plurality of heads into contact with the tear blade.

A voltage controlled oscillator, a phase comparator that compares the phases of the output signal of this voltage controlled oscillator and signals obtained from 1M heads, and a phase comparator that converts the output of this phase comparator into a voltage level and converts it to a voltage controlled oscillator. It has a conversion circuit that supplies
A first control loop that uses the output signal of the voltage controlled oscillator as a clock for extracting reproduced data; a first detector that detects the period of the output signal of the voltage controlled oscillator; and a first detector that detects the period of the output signal of the voltage controlled oscillator; A second detector for detecting, a comparator for comparing each detection output of the first and second detectors, a generation circuit for generating a voltage level corresponding to the comparison result of the comparator, and a generation circuit for generating the voltage level corresponding to the comparison result of the comparator. a second control loop having an addition circuit that adds the output voltage to the output voltage of the conversion circuit; and a gain control circuit that detects the presence or absence of a signal obtained from the head and reduces the gain of the second control loop when the signal is present. It is prepared.

In addition to the above configuration, in the detection output of the second detector,
comprising an offset adding means for giving an offset corresponding to a deviation of the playback data rate with respect to the tape speed multiplier,
The oscillation frequency of the voltage controlled oscillator is configured to correspond to the output of the offset adding means when there is no reproduction signal obtained from the head.

(Function) According to the above configuration, the presence or absence of a signal obtained from the head is detected and the gain of the second control loop is lowered when the signal is present, so that the gain of the second control loop is reduced when the signal is present, that is, the first control loop. In the locked state, the output of the second control loop, that is, the output voltage level of the generation circuit, is no longer dependent on the relative speed detection result, so the forces acting on the first control loop and the second control loop conflict with each other. This makes it possible to generate accurate data extraction clocks and perform good data reproduction.

In addition, an offset corresponding to the deviation of the playback data ray 1 from the tape speed multiplier is added to the relative speed detection result, so the voltage Since the oscillation frequency of the controlled oscillator can be made to correspond to the signal state, it is possible to generate an accurate data extraction clock using only the first control loop without compensating for deviations in the reproduction data rate due to the azimuth effect. , and good data reproduction can be performed.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, the same parts as in FIG. 19 are shown with the same symbols, and only the different parts will be described here.

The signal RF from the head supplied to the input terminal 1■ is supplied to the level detection circuit 24. This level detection circuit 24 detects the level of the manually input signal RF and determines whether it is in a no-signal state or a signal-present state. When the signal is present, a hold request signal is generated so as to hold the bias voltage output to the bias voltage generation circuit 21.

$1 like this. According to J.J., when the output from the head is in a signal state, that is, when the APC loop 16 is locked, the output bias voltage level of the bias voltage generation circuit 21 is fixed, and the AFC loop 2
Since the gain of 2 is lowered and no longer acts on the APC loop 16, it is possible to prevent the forces acting on the APC loop 16 and the AFC loop 22 from contradicting each other due to deviations in the playback data rate due to the azimuth effect, thereby ensuring accurate data. A sampling clock PLCK can be generated.

Here, FIG. 2 shows FIG. 1 more specifically. That is, the signal RF supplied to the input terminal 11
As described above, is supplied to the phase comparator 12 and the level detection circuit 24, as well as to the relative speed detection circuit 20.

This relative speed detection circuit 20 detects A included in the signal RF.
By extracting a TF (auto track finding) pilot signal and counting the cycle of one wave of this ATF pilot signal using the measurement clock CKI (9,408 MHz) supplied to the clock input terminal 25, the head and tape are connected. It detects the relative speed of

The reproduction frequency of the ATF pilot signal during normal reproduction is 130.7 kHz (-9,408MHz
/72). Even during high-speed playback, if the relative speed between the head and tape is the same as during normal playback, the playback frequency of the ATF pilot signal is 130.7 as above.
It becomes kHz.

On the other hand, if the relative speed between the head and tape changes, the AT
The reproduction frequency of the F pilot signal will change in proportion to the relative speed. Then, the count value obtained by counting the period of one wave of the ATF pilot signal using the measurement clock CKI is averaged to absorb changes in the reproduction data rate due to detection errors and azimuth effects, and then the count value is calculated by the relative speed detection circuit 20. The detection result is output to one input terminal of the comparison circuit 19.

Furthermore, the measurement clock CKI supplied to the clock input terminal 25 is also supplied to the clock detection circuit 18. This clock detection circuit 18 divides the frequency of the data extraction clock PLCK output from the VCO 13 by 72 and counts the period of one wave of the signal using the measurement clock CKI, thereby detecting the data extraction clock PLCK.
It detects the period of .

The playback data rate during normal playback is 9.408.
Since it is MHz, by dividing this frequency by 72, the count value of the clock detection circuit 18 is normalized to the detection result of the relative speed. The output count value of the clock detection circuit 18 is then supplied to the other input terminal of the comparison circuit 19.

The comparison circuit 19 compares the count value that is the target firing speed detection result with the count value that is the period detection result of the data sampling clock PLCK, and uses the comparison result as a U/D (up/down) signal. Output to U/D counter 26. In this case, the U/D signal output from the comparator circuit 19 is determined when the count value that is the result of the detection of the speed versus speed is larger than the count value that is the result of the cycle detection of the data extraction clock PLCK Assume that the D counter 26 is instructed to count up.

The U/D counter 26 receives the U/D output from the comparison circuit 19 in a state where no hold request signal is generated from the level detection circuit 24, that is, in a no-signal state.
The counter clock CK2 supplied to the clock input terminal 27 is counted up or down based on the signal.

Further, the U/D counter 2B has a level detection circuit 24.
The count value is held in a state in which a hold request signal is generated from , that is, in a signal presence state. and,
The output count value of this U/D counter 26 is supplied to a shift register 28. This shift register 28 is
In synchronization with the pulse signal RC output from the counter 29, the output count value of the U/D counter 2B is latched and output to one input terminal of the coincidence detection circuit 3o.

Here, the counter 29 counts the counter clock CK3 supplied to the clock input terminal 31 cyclically at a constant frequency, and outputs the count value to the other input terminal of the coincidence detection circuit 30. Further, the counter 29 generates the pulse signal RC when its count value reaches the maximum.

The coincidence detection circuit 30 includes a shift register 28
The reset-set-flip-flop circuit (hereinafter referred to as R3-FF circuit) detects that the count value output from the counter 29 matches the output count value of the counter 29.
A set signal is output to the set input terminal S of 32. Further, the reset input terminal R of the R3-FF circuit 32 is supplied with the pulse signal RC output from the counter 29. Here, the output of the R3-FF circuit 32 is LPF3
3 to the adder circuit 15.

The operation of the above configuration will be described below. First, when the signal RF is in a non-signal state, the U/D counter 26
Consider the case where the output count value of is changing as shown in FIG. 3(a). At this time, if the output count value of the counter 29 is circulated as shown in a stepwise manner in FIG. ) A pulse signal RC is generated as shown in FIG.

Then, in synchronization with this pulse signal RC, the shift register 28 latches the output count value of the U/D counter 26, so that the output count value of the shift register 28 changes as shown in FIG. 3(b). do. Here, when the coincidence detection circuit 30 detects a coincidence between the output count value of the shift register 28 and the output count value of the counter 29, it generates a set signal S as shown in FIG. 3(e).

Therefore, the 5R-FF circuit 32 is set in synchronization with the rise of the set signal S, and is reset in synchronization with the rise of the pulse signal RC. As shown in figure (f), comparison circuit 1
A PWM (pulse width modulation) signal corresponding to the comparison result of No. 9 is generated. And this PWM signal is L P F 3
3, a bias voltage corresponding to the comparison result of the comparison circuit 19 is generated here.

According to the above configuration, as shown in FIG. 4(a), when there is no signal output from the head, the APC loop 16
is not operating and the U/D counter 26 is in operation, the oscillation frequency of the VCO 13 is different from that of the relative speed detection circuit 20.
control based on the detection results. Therefore, if the relative speed is the same as during normal playback, the frequency of the data extraction clock PLCK is 9.408 MHz.
A bias voltage is output from the LPF 33. Note that if the relative speed changes, the data extraction clock PL
Of course, the bias voltage is controlled so that the frequency of CK corresponds to changes in relative speed.

The oscillation frequency of the V CO 13, the control voltage applied to the V CO 13, and the bias voltage output from the LPF 33 at this time are shown in FIGS. 4(b) and 4(c).

Each is shown in (d). In addition, the level detection circuit 2
As shown in FIG. 4(e), the output of No. 4 is at the L (low) level indicating a no-signal state.

Then, at time T11, when a reproduced signal is obtained from, for example, the +azimuth head as shown in FIG. 4(a), the AP
The operation of the C loop 16 is started. In this case, the APC loop 1B operates to lower the control voltage, that is, lower the oscillation frequency of the VCO 13, due to the playback data rate deviation due to the azimuth effect described above.
At time TI2 when a predetermined pull-in time tll has elapsed, the lock state is reached.

On the other hand, at time Tll when the reproduced signal is obtained, the output of the level detection circuit 24 becomes H (high) level indicating a signal presence state, as shown in FIG. 4(e), and at this time U/
The D counter 26 is placed in a hold state. For this reason,
The bias voltage output from the LPF 33 is shown in Figure 4 (d
), it is held at the level immediately before time Tit.

Then, when the no-signal state occurs again at time T13, the output of the level detection circuit 24 becomes L level indicating the no-signal state, as shown in FIG. 4(e). Therefore, the U/D counter 2G starts counting, the APC loop 16 becomes inactive, and the oscillation frequency of v co ta, control voltage, and bias voltage correspond to the detection results of the relative speed detection circuit 20. and become controlled.

Next, FIG. 5 shows a modification of FIG. 2.

That is, in place of the level detection circuit 24,
An ATF area detection circuit 34 is provided.

This ATF area detection circuit 34 detects ATF data in the signal RF obtained from the head and outputs it to the U/D counter 2.
It acts to hold 6.

The data that needs to be read in the high-speed reproduction state are the aforementioned subcode data 5UB-1 and 5UB-2 and the PCM digitized data of the data area, and there is no need to read the ATF data. Therefore, by placing the U/D counter 26 in a hold state while the head is dosing the ATF data area, substantially the same effect as in the above embodiment can be obtained.

Note that the ATF data area can be easily detected using the PG pulse for knowing the rotational position of the drum and the FG pulse for knowing the rotational speed of the drum.

FIG. 6 shows still another modification of FIG. 2. That is, the detection output of the level detection circuit 24 is
Instead of the counter 26, the clock is supplied to the clock detection circuit 18. In this case, when the output signal corresponding to the signal presence state is generated from the level detection circuit 24, the clock detection circuit 18 improves the detection accuracy to the extent that it is not possible to detect at least a deviation in the reproduced data rate due to the azimuth effect. It acts to lower it.

For example, if the detection accuracy is to be reduced to 1/2, this can be achieved by truncating the lower 1 bit of the detection result of the clock detection circuit 18, that is, setting it to "0".

By doing this, even if the U/D counter 26 is always active, as long as the change in the reproduction data rate is within the detection accuracy, the bias voltage output from the LPF 33 will not change. The control gain will be lowered. However, if the reproduction data rate changes due to disturbance or the like by more than the deviation of the reproduction data rate due to the azimuth effect, the bias voltage changes and the frequency of the data extraction clock PLCK is controlled to be close to the reproduction data rate.

Therefore, in the no-signal state, the frequency of the data extraction clock PLCK is controlled with high precision so that it is close to the reproduction data rate, and in the signal state, the frequency of the data extraction clock PLCK is controlled to be close to the reproduction data rate. Changes in the frequency of the sampling clock PLCK are allowed, but if such changes occur, the frequency is controlled to be close to the reproduced data rate.

As described above, the data extraction clock PLCK can be generated satisfactorily in the high-speed reproduction state.

Moreover, FIG. 7 shows still another modification of the above-mentioned FIG. 2. That is, the up pulse UP and down pulse DP are selectively generated according to the comparison result between the relative speed detection output and the clock detection output from the comparison circuit 19, and the up pulse UP and down pulse DP are transferred to the buffer circuit 35a, Three-value output buffer circuit 3 consisting of 35b
5 and an integrating circuit 36, the signal is supplied to the adding circuit 15.

In this case, the up pulse U output from the comparison circuit 19
The pulse widths of P and down pulse Dr correspond to the comparison results. Also, a buffer circuit 35a.

35b outputs the input pulses UP and DP as they are when the up pulses UP and down pulses DP are input, but when the hold request signal corresponding to the signal state is output from the level detection circuit 24, ,
The output is forced into a high impedance state.

According to the configuration shown in FIG. 7, from the head and level detection circuit 24, as shown in FIGS. 8(a) and 8(b),
The reproduction signal RF and the hold request signal are respectively output from the comparator circuit 19 in the same figure (C).

As shown in (d), it is assumed that an up pulse UP and a down pulse DP are respectively output.

Note that in FIG. 8, the dotted line indicates a high impedance state.

Then, the output of the ternary output buffer circuit 35 is as shown in FIG.
This output is supplied to the integrating circuit 36 to generate a bias voltage as shown in (f) of the same figure.

Moreover, FIG. 9 shows a modification of FIG. 7.

That is, the adder circuit 15 is placed before the LPF 14, and the output of the phase comparator 12 and the output of the ternary output buffer circuit 35 are added together, and the LPF 14 converts the sum into a voltage level. The integration circuit 3B is omitted to simplify the configuration.

Next, FIG. 10 shows another embodiment of the present invention. In addition, in FIG. 10, the bias voltage generation circuit 2
1, a voltage generation circuit 21a, and this voltage generation circuit 21a.
An S/H (sample/hold) circuit 21b is shown separately for holding the bias voltage output from the level detection circuit 24 using the detection output of the level detection circuit 24. Also,
The relative speed detection circuit 20 receives A supplied to the input terminal 37.
The relative speed is assumed to be detected based on the TF pilot signal.

Then, the detection output of the relative speed detection circuit 20 and the output of the deviation calculation circuit 38 are added by an addition circuit 39 and the result is supplied to the comparison circuit 19. This deviation calculation circuit 3
A head identification signal indicating whether the head currently tracing the tape is a +azimuth head or a -azimuth head is supplied to B via an input terminal 40, and whether the tape is running in the forward or reverse direction. A tape running direction identification signal indicating whether the tape running direction
2.

Then, this deviation calculation circuit 38 calculates the tape running speed based on the FG pulse, and based on the calculated tape running speed, the head identification signal and the tape running direction identification signal, first perform the process shown in FIG. A value corresponding to the playback data rate deviation with respect to the indicated tape speed multiplier is calculated.

In such a configuration, for example, if the tape running direction is the opposite direction and the tape running speed is 200 times that of normal playback,
Let's explain its operation. That is, FIG. 11(a) shows a head identification signal, and its L level and H level states correspond to the +azimuth head and the −azimuth head, respectively, as shown in FIG. 11(b). And A
As shown in FIG. 11(d), the PC loop 1G is in a free running state when there is no signal, and is in a locked state when there is a signal.

Here, as described above, the relative speed detection circuit 20 outputs a detection output obtained by sufficiently averaging the count values corresponding to the reproduction frequency of the ATF pilot signal, that is, as shown in FIG.
) The average playback data rate (equivalent to relative speed) is output.

On the other hand, under the above conditions, the playback data rate deviation due to the azimuth effect is +2% for the +azimuth head and =2% for the -azimuth head with respect to the average playback data rate, as is clear from Figure 22. be. Then, the deviation calculation circuit 38 outputs a value corresponding to 12% of the reproduction data rate when the head identification signal is in the L level state so as to cancel out this reproduction data rate deviation of ±296, and also outputs a value corresponding to 12% of the reproduction data rate when the head identification signal In the H level state, a value corresponding to +2% of the reproduction data rate is output.

Therefore, as shown in FIG. 11(C), the playback data rate output from the adder circuit 37 becomes a value 2% lower than the average playback data rate when the head identification signal is at the L level. In the H level state, the value is 2% higher than the average playback data rate. , Then, in a no-signal state, that is, in a free-running state in which the APC loop 16 is not activated, by the action of the AFC loop 22, V
After the oscillation frequency of the CO 13 is controlled to correspond to the output of the adder circuit 39, the APC loop 16 is switched from the free running state to the locked state.

Therefore, according to the embodiment shown in FIG. 10, when the APC loop 1B is free-running, the V CO 13 is controlled so that the frequency corresponds to the reproduced data rate of the signal RF to be obtained next by the action of the AFC loop 22. Since the oscillation frequency of the APC loop 16 is controlled, when a signal is present, the APC loop 16
can be quickly locked.

As described above, it is possible to compensate for deviations in the reproduction data rate due to the azimuth effect and generate an accurate data extraction clock PLCK without increasing the accuracy of the APC loop 16, thereby achieving good data reproduction. .

Further, the deviation calculation circuit 38 can calculate - by the head identification signal and tape running direction identification signal without supplying the FG pulse, that is, regardless of the tape running speed.
Alternatively, a signal for compensating for a deviation of ±1% may be generated. According to such a configuration, when there is no signal RF shown in FIG. 12(a), that is, the V C shown in FIG. 12(c)
In the free-running state of O13, its oscillation frequency is ±1 from the value corresponding to the average playback data rate, as shown in Figure (b).
% changes, and after entering the signal state, APC loop 1
With the pulling action of 6, it can change up to ±2%.

Even with such a configuration, it is possible to generate a good data extraction clock PLCK without adding a large burden to the pull-in action of the APC loop 16.

Next, FIG. 13 shows still another embodiment of the present invention. That is, the signal RF supplied to the input terminal 11
are supplied to data rate detection circuits 43 and 44, respectively. These data rate detection circuits 43 and 44 detect the head A by a head identification signal supplied to an input terminal 45.
, B detect the reproduction data rate of the signal RF obtained by tracing the tape.

Therefore, for example, the data rate detection circuit 43 detects only the reproduction data rate of the reproduction signal RF by the +azimuth head, and the data rate detection circuit 44 detects only the reproduction data rate of the reproduction signal RF by the -azimuth head. . Here, each data rate detection circuit 43.
The reproduction data rate detected at 44 naturally includes a deviation in the reproduction data rate due to the azimuth effect.

Then, the playback data rate detected by each data rate detection circuit 43, 44 is selectively selected by the comparison circuit 4B by the selection circuit 4B driven based on the head identification signal.
Guided by 9. That is, if the reproduction signal RF shown in FIG. 14(b) is obtained for the head identification signal shown in FIG. 14(a), the data rate detection circuits 43 and 44
As shown in FIG. 4(c), the detection operation is performed during the L level and H level periods of the head identification signal.

Therefore, the playback data rate output from the data rate detection circuit 43 changes at the timing shown in FIG. 14(d), and the playback data rate output from the data rate detection circuit 44 changes at the timing shown in FIG. 14(e). The reproduction data rate detected by each data rate detection circuit 43, 44 is outputted from the selection circuit 46 at the timing shown in FIG. 4(f).

As described above, by supplying the detection result including the deviation in the reproduction data rate due to the azimuth effect to the comparison circuit 19, there is no need to calculate the deviation in the reproduction data rate due to the azimuth effect, and the configuration is simplified. be able to. Furthermore, in this embodiment, the data rate detection circuit 4
Although two 3.44s are provided, it goes without saying that one may be used in a time-sharing manner.

It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, an extremely good helical scan can be achieved that can compensate for deviations in the reproduction data rate due to the azimuth effect and perform accurate data reproduction in high-speed tape reproduction conditions. It is possible to provide a tape playback device of this type.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of a helical scan type tape playback device according to the present invention, FIG. 2 is a block diagram showing the same embodiment in more detail, and FIGS. 3 and 4 are timing diagrams for explaining the operation of the same embodiment, FIGS. 5 and 6 are block diagrams showing modified examples of the same embodiment, and FIGS. 7 to 9 are further diagrams of the same embodiment, respectively. Block configuration diagram, timing diagram, and block configuration diagram for explaining other modified examples, Part 1
0 and 11 are block diagrams showing a second embodiment of the present invention and timing diagrams for explaining its operation, and FIG. 12 explains the operation of a modified example of the second embodiment. 13 and 14 are respectively a block diagram showing the third embodiment of the present invention and a timing diagram for explaining its operation. FIG. 15 is a timing diagram for explaining the operation of the third embodiment of the present invention. A diagram showing the data format. Figure 16 is a characteristic curve diagram showing changes in the playback data rate when the drum rotation speed is kept constant and the tape running speed is varied. Figure 17 is a playback signal and the operating state of the APC loop. A diagram showing the relationship between
Fig. 18 is a characteristic diagram showing the drum rotation speed, tape speed multiplier, and reproduction data rate ratio, Fig. 19 is a block diagram showing a conventional tape playback device, and Fig. 20 is a diagram showing the relationship between tracks and heads during high-speed playback. Figure 21 is a diagram showing the deviation of the reproduction data rate due to the azimuth effect, Figure 22 is a characteristic diagram showing the deviation of the reproduction data rate with respect to the tape speed, and Figure 23 is a diagram showing the reproduction signal and reproduction data. FIG. 24, which is a diagram showing the relationship with the rate, is a timing diagram for explaining the problems of the conventional device. 11...Input terminal, 12...Phase comparator, 13...
・VCO1I4...LPF, 15...Addition circuit, 1
B...APC loop, 17...Output terminal, 18...
・Clock detection circuit, 19... Comparison circuit, 20...
Relative speed detection circuit, 21... bias voltage generation circuit,
22...AFC loop, 23...tape, 24...
・Level detection circuit, 25...clock input terminal, 2B
...U/D counter, 27...clock input terminal,
28...Shift register, 29...Counter, 30
... Coincidence detection circuit, 31 ... Clock input terminal, 3
2...R5-FF circuit, 33...LPF, 34...
・ATF area detection circuit, 35... Three-value output buffer circuit, 36... Integrating circuit, 37... Input terminal, 38...
... Deviation calculation circuit, 39... Addition circuit, 40-42.
...Input terminal, 43.44...Data rate detection circuit, 45...Input terminal, 46...Selection circuit. Applicant's Representative Patent Attorney Takehiko Suzue Figure 2 Figure 5 Figure 6 Figure 7 (c) -D1---rL-,,---fl---(
d) --LJ----LJ----1---
-LJ---(・)-Plate-LJ---------
--------Bite-LJ----Tape Liao Li' (V/V
o) Figure 16 Figure 17 Figure 19 Figure 20 Figure 8

Claims (6)

[Claims] (1) A tape is wound around a rotating drum on which a plurality of heads are installed at different azimuth angles, and the rotating drum is rotated to selectively bring the plurality of heads into contact with the tape, thereby generating an intermittent signal. A helical scan type tape playback device to obtain, a voltage controlled oscillator, a phase comparator that compares the phases of an output signal of the voltage controlled oscillator and signals obtained from the plurality of heads;
a first control loop comprising a conversion circuit that converts the output of the phase comparator into a voltage level and supplies the voltage level to the voltage controlled oscillator, and uses the output signal of the voltage controlled oscillator as a clock for extracting reproduced data; a first detector that detects the period of the output signal of the voltage controlled oscillator; a second detector that detects the relative speed between the tape and the head; and each detection output of the first and second detectors. A second control comprising: a comparator that compares the , a generation circuit that generates a voltage level corresponding to the comparison result of the comparator, and an addition circuit that adds the output voltage of the generation circuit to the output voltage of the conversion circuit. What is claimed is: 1. A helical scan type tape reproducing device comprising: a loop; and a gain control circuit that detects the presence or absence of a signal obtained from the head and reduces the gain of the second control loop when the signal is present. (2) The helical according to claim 1, further comprising an offset adding means for adding an offset to the detection output of the second detector corresponding to a deviation of the playback data rate with respect to the speed multiplier of the tape. Scan-type tape playback device. (3) The offset addition means includes an arithmetic circuit that calculates a deviation of the playback data rate from the tape speed multiplier based on the tape running speed detection signal, the running direction identification signal, and the head identification signal. , an adder for adding the output of the arithmetic circuit to the output of the second detector, the oscillation frequency of the voltage controlled oscillator is adjusted to 3. The helical scan type tape reproducing apparatus according to claim 2, wherein the helical scan type tape reproducing apparatus is configured to correspond to the output of the adder. (4) The offset adding means includes a deviation output circuit that outputs a fixed amount of deviation of the playback data rate with respect to the speed multiplier of the tape based on the identification signal of the running direction of the tape and the identification signal of the head; an adder that adds the output of the arithmetic circuit to the output of the second detector,
3. The helical according to claim 2, wherein the oscillation frequency of the voltage controlled oscillator is made to correspond to the output of the adder when the reproduced signal obtained from the head is in the absence of signal. Scan-type tape playback device. (5) The second detector includes a data rate detection circuit that detects a reproduction data rate obtained by each of the plurality of heads tracing a track corresponding to its own azimuth angle, and 2. A selection circuit that selectively supplies a plurality of output playback data rates to the comparator in accordance with timings at which the plurality of heads selectively trace the tape. 1. The helical scan type tape playback device according to 1. (6) The generation circuit includes an up/down counter that counts up or down depending on the comparison result of the comparator, a reference counter that performs a cyclic counting operation at a constant cycle, and a count value of this reference counter and the up/down counter. a coincidence detector that detects coincidence with the count value of the counter; a bistable circuit whose state is inverted according to the detection signal of the coincidence detector and the signal output from the reference counter every cycle counting period; 6. The helical scan tape reproducing apparatus according to claim 1, further comprising a voltage conversion circuit that converts the output of the bistable circuit into a voltage level.