JPH01311348A - Channel interface circuit - Google Patents

Abstract

PURPOSE:To improve a time-out monitoring function by providing the title device with a setting means for setting up timers to respective devices and setting up the time-out setting values of the timers. CONSTITUTION:A time base 14 interrupts a CPU 11 at a fixed interval and the CPU 11 counts u the number of times of interruption to control the passage of time, and when the count value coincides with the time-out set value, recognizes time-out. When an I/O bus I/OB is not used, the CPU 11 decides that the detected device generates a time-out and transmits time-out status to a host computer. When the I/OB is used, the CPU 11 detects a device occupying the I/OB at present and compares the device with a time-out detecting device. When both the devices coincide with each other, that the time-out detecting device generates the time-out while occupying the I/OB is decided, and at the time of discrepancy, said operation is returned without executing the time-out processing.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a channel interface circuit that connects to a host computer via a channel bus and connects multiple devices via an input/output bus. This adds a function to correctly identify the device where the problem occurred.

<Prior Art> FIG. 5 shows a system configuration using a channel interface circuit that connects a plurality of saw devices and a host computer.

In this 1, ■ is a channel interface circuit, and the host terminal '!'! is connected via the channel bus CB. ′
It is connected to L machine 2, and connected to devices 3 and 32 such as disks and tape devices via input/output bus I and OB, and is involved in exchanging commands and data between host computer 2 and devices 31 and 32. do.

Here, as the input/output bus 110B, SCSI (Sl
all Co+aputer 5ysten+ In
It is assumed that the following is used.

Typically, devices 31. connected to input/output bus l10B.
In consideration of the occurrence of a malfunction in the 32, a timer is provided for each device, and the malfunction is discovered by detecting a device that has timed out.

At this time, a short timeout value is set for the fast operating speed device 31, and a long timeout value is set for the slow operating speed device 32.

<Problem to be solved by the invention> Device 32 that has a long timeout setting value
Or, if a problem occurs while occupying the input/output bus 110B and the other device 3 cannot access the input/output bus 12/'OB, the timeout output is sent from device 31 before device 32. There is something to be done.

For this reason, the host computer 'A:lfm2 detects the timeout of device 3 first even though device 32 is at fault, misrecognizes the device where the fault has occurred, and is unable to correctly analyze the cause of the fault. There was a problem.

The present invention solves these problems and aims to improve the timeout monitoring function of the channel interface circuit.

Means for Solving the Problems> The present invention, which has solved the above problems, provides a channel interface circuit that connects to a host computer via a channel bus and connects multiple devices via an input/output bus. In this method, a timer is set for each device, and a setting means is provided to set the timeout setting value, and when a timeout is detected, the device corresponding to the timer is compared with the device currently occupying the input/output bus. ,
If the input/output bus is not in use, it is determined that the device has timed out, and if they match, it is determined that the device has timed out while occupying the input/output bus, and if there is no mosquitoes, wait for completion processing. A channel interface characterized in that it is provided with a determination processing means for performing l=I l? It is fj.

Function> When the channel interface circuit of the present invention detects a device that has timed out, it also detects a device occupying the input/output bus, and when there is no device occupying the input/output bus, it sets this device to timeout. ,
If it matches the input/output bus occupancy device or the device that has timed out, the device is timed out, and if it does not match, it waits for completion processing.

<Embodiment> Part 1 is a block diagram of a channel interface circuit according to the present invention, with the present invention shown in solid lines.

In this part 1, 11 is a C P LJ that controls the operation of the entire channel interface circuit, 12 is an input/output bus control unit that controls the protocol of the input/output bus l/Ot3, and 13 is a controller that controls the protocol of the channel bus CB. A channel bus control unit controls: AB is an address bus, DB is a data bus, and CL is a control line. 14 is always C, Pl, ! at fixed time intervals. It is a time base that multiplies 2 by 'S11 input.

FIG. 2 shows a flowchart representing the operation of the channel interface circuit of the present invention.

Further, the interrupt processing operation from the time base 14 in the circuit of the present invention is shown in the flowchart of FIG.

The time base 14 interrupts the CPU II at regular intervals, and the CPLJ II manages the passage of time by counting the number of interrupts, and recognizes a timeout when the count fa matches the timeout setting value. C.P.
In tJll, timer numbers O to n, timeout settings, and number of cuts (counts) are set in a table format for each connected device.

Returning to FIG. 2, the operation of the circuit of the present invention will be explained.

First, when a device access request is received from the upper host computer 2, the request is received and the corresponding device is selected.

At this point, allocate a timer to each device and set the timeout settings.

Next, send a command to the selected device, receive the status from this device after data transfer processing,
This status is sent to the host calculation fi2 and one process is completed. At this point, reset the evening time.

In the following process, timeout monitoring is performed while waiting for access request reception processing to be completed, command transmission processing to be completed, data transfer processing to be completed, and status transmission processing to be completed.Timeout monitoring is based on the timer count value and timeout setting value. This process calculates the ratio and times out when they match.

FIG. 4 shows this timeout processing.

If a device that has timed out is found, check the usage status of the input/output bus I/OH.

(a) If the input/output bus I/OES is not in use, it is determined that the discovered device has generated a timeout signal, and a timeout status is sent to the host computer. In this case, the device corresponding to this timer disconnects (opens the bus) the input/output bus l10B and does not reconnect.

If the input/output bus 110B is being used, the device currently occupying the input/output bus 110B is detected and compared with the device for which timeout has been detected.

(b) If they match, it is determined that the timeout occurred while the device that detected the timeout was still occupying the input/output bus l10B.

(c) If there is no match, return without performing timeout processing. At this time, the current input/output bus 1/Ot
Waits for the device occupying 3 to finish processing. After the processing of the device currently designated to occupy the input/output bus is completed, a state is reached in which either of the conditions (a) and (b) above are detected.

In this manner, the present invention determines whether the device has timed out or is occupying the input/output bus and performs a
Since a timeout status is now sent to the device, even if a problem occurs on a device with a long timeout value and a timeout occurs on another device first, the device with the long timeout value can be identified. be able to.

<Effects of the Invention> As described above, according to the present invention, it is possible to identify a device in which a malfunction has occurred in a channel interface circuit that operates multiple devices in parallel, and it is possible to perform a thorough analysis of the cause of the malfunction. , the functionality of the channel interface circuit can be improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a channel interface circuit implementing the present invention, Fig. 2 is a flowchart showing the operation of the circuit of the present invention, and Fig. 3 is a block diagram showing the operation of the circuit of the present invention.
FIG. 4 is a diagram showing the time-out processing of the circuit of the present invention, and FIG. 5 is a diagram showing the configuration 1 of a system using the channel interface circuit tnt. ■...Channel interface circuit, 11...
CP LJ, 12...I/O bus control unit,
13... Channel bus control unit, 14... Time base, AB... Address bus, CL... Control line, DI-3... Data bus, 2... Host computer, 31.32...
Device, l10EI...Person output bus, CB...Channel bus. −> Figure 5

Claims (1)

[Claims] (1) Connect to the host computer via the channel bus,
In a channel interface circuit that connects multiple devices via an input/output bus, a setting means is provided to set a timer for each device and its timeout setting value, and to respond to the timer when a timeout is detected. Compare the device with the device currently occupying the input/output bus, and if the input/output bus is not in use, determine that the device has timed out, and if they match, the device has occupied the input/output bus. A channel interface circuit characterized in that it is provided with a determination processing means that determines that a timeout has occurred in a state and performs termination wait processing if they do not match.