JPH0754487B2 - Channel interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Field of Application> The present invention relates to a channel interface circuit that connects to a host computer via a channel bus and connects a plurality of devices via an input / output bus. The function to correctly identify the device that occurred is added.

<Prior art> A channel that connects multiple devices to a host computer.
A system configuration using the interface circuit is shown in FIG.

In this figure, reference numeral 1 is a channel interface circuit, which is connected to a host computer 2 via a channel bus CB and connected to devices 31 and 32 such as disks and tape devices via an input / output bus I / OB. It is involved in the exchange of commands and data between the host computer 2 and the devices 31 and 32.

Here, SCSI (Smail Computer) is used as the input / output bus I / OB.
System Interface) is assumed.

Usually, considering that a failure may occur in the devices 31 and 32 connected to the I / O bus I / OB, a timer is provided for each device, and the device that times out is detected and the failure is discovered. is doing.

At this time, a short timeout value is set for the device 31 having a high operation speed, and a long timeout value is set for the device 32 having a low operation speed.

<Problems to be Solved by the Invention> A problem occurs while the device 32 with a long timeout setting value occupies the I / O bus I / OB, and other devices 31 cannot access the I / OB bus. In such a case, the device 31 may output a timeout before the device 32.

Therefore, although the host computer 2 has a problem with the device 32, there is a problem that the timeout of the device 31 is first detected, the device having the problem is erroneously recognized, and the correct analysis of the cause of the problem is impossible. there were.

The present invention solves such a problem, and an object of the present invention is to improve the timeout monitoring function of the channel interface circuit.

<Means for Solving the Problems> The present invention, which has solved the above problems, provides a channel interface circuit that connects to a host computer via a channel bus and connects a plurality of devices via an input / output bus. Setting a timer for each device and setting the time-out setting value, when a time-out is detected, the device corresponding to the timer is compared with the device currently occupying the I / O bus, If the bus is not used, it is determined that the device has timed out.If they match, it is determined that the device has timed out while occupying the I / O bus. If they do not match, the end wait process is performed. It is a channel interface circuit characterized in that means are provided.

<Operation> When the channel interface circuit of the present invention detects a device that has timed out, it detects the device occupying the I / O bus at this time, and if there is no I / O bus occupying device, this device times out. If the device occupied by the I / O bus matches the device that timed out, the device is timed out, and if they do not match, the end wait process is performed.

<Embodiment> FIG. 1 is a block diagram of a channel interface circuit of the present invention in which the present invention is implemented.

In this figure, 11 is a CPU that controls the operation of the entire channel interface circuit, 12 is an input / output bus control unit that controls the protocol of the input / output bus I / OB, and 13 is a channel that controls the protocol of the channel bus CB. -Bus controller, AB is an address bus, DB is a data bus, and CL is a control line. 14 is a time base that constantly interrupts the CPU 11 at fixed time intervals.

FIG. 2 is a flow chart showing the operation of the channel interface circuit of the present invention.

The operation of interrupt processing from the time base 14 in the circuit of the present invention is shown in the flowchart of FIG.

Timebase 14 interrupts CPU 11 at regular intervals
The PU 11 manages the passage of time by counting the number of interrupts, and recognizes the timeout when the count value matches the timeout setting value. The CPU 11 sets the timer numbers 0 to n, the timeout setting value, and the interrupt count value (count) in a table format corresponding to each connected device.

Returning to FIG. 2, the operation of the circuit of the present invention will be described.

First, when there is a device access request from the host computer 2 of a higher level, the request reception process is performed and the corresponding device selection process is performed.

At this point, assign a timer to each device and set the timeout setting value.

Next, send a command to the selected device, receive the status from this device after the data transfer process,
This status is transmitted to the host computer 2 and one process is ended. At this point the timer is reset.

In the above processing, waiting for the completion of the access request reception processing,
Waiting for command transmission processing completion, data transfer processing completion,
Timeout monitoring is performed while waiting for the status transmission process to end. The time-out monitoring is a process of comparing the count value of the timer with the time-out setting value and setting a time-out when they match.

This time-out process is shown in FIG.

If a device that times out is found, check the usage status of the I / O bus I / OB.

(B) If the I / O bus I / OB is not used, it is determined that the discovered device has timed out, and the time-out status is transmitted to the host computer. In this case, the device corresponding to this timer is the I / O bus I / OB.
This is the case when the bus was disconnected and was not reconnected.

When the I / O bus I / OB is used, the device currently occupying the I / O bus I / OB is detected and compared with the device that detected the timeout.

(B) If they match, it is determined that the device that has detected the timeout has timed out while occupying the I / OB bus.

(C) If they do not match, the process returns without performing timeout processing. At this time, the device currently occupying the I / O bus waits for the end of processing. Then, after the processing of the device currently occupying the input / output bus is completed, the condition for detecting one of the conditions (a) and (b) is entered.

As described above, according to the present invention, the time-out status is transmitted to the host computer by checking whether the time-out device occupies the I / O bus.
A device with a long timeout value has failed,
Even if a timeout occurs in another device first, it is possible to identify the device in which the malfunction has a long timeout value.

<Effects of the Invention> As described above, according to the present invention, it is possible to identify a device in which a failure has occurred in a channel interface circuit for operating a plurality of devices in parallel, and it is possible to correctly analyze the failure factor. The function of the channel interface circuit can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a channel interface circuit embodying the present invention, FIG. 2 is a flow chart showing the operation of the circuit of the present invention, and FIG. 3 is a time chart of a CPU 11 in the circuit of the present invention. FIG. 4 is a diagram showing a base 14 interrupt process, FIG. 4 is a diagram showing a time-out process of the circuit of the present invention, and FIG. 5 is a configuration diagram of a system using a channel interface circuit. 1 ... Channel interface circuit, 11 ... CPU, 12 ... Input / output bus control unit, 13 ... Channel bus control unit, 14 ... Time base, AB ... Address bus, CL ... Control line, DB ... Data bus, 2 ... Host computer, 31,32 ... Device, I / OB ... I / O bus, CB ... Channel bus.

Claims (1)

[Claims] 1. A channel interface circuit which connects to a host computer via a channel bus and connects a plurality of devices via an input / output bus, sets a timer for each device and sets a timeout setting value thereof. When a time-out is detected, the device corresponding to the timer is compared with the device currently occupying the I / O bus. If the I / O bus is not used, the device timed out. The channel interface circuit is provided with a determination processing unit that determines that the device has timed out while occupying the input / output bus if the two match, and waits for termination if the devices do not match.