JPH01310589A - Front-rear continuity structure of laminated board - Google Patents

Front-rear continuity structure of laminated board

Info

Publication number
JPH01310589A
JPH01310589A JP14116288A JP14116288A JPH01310589A JP H01310589 A JPH01310589 A JP H01310589A JP 14116288 A JP14116288 A JP 14116288A JP 14116288 A JP14116288 A JP 14116288A JP H01310589 A JPH01310589 A JP H01310589A
Authority
JP
Japan
Prior art keywords
hole
board
pattern
wire lead
hard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14116288A
Other languages
Japanese (ja)
Inventor
Mikio Miyahara
宮原　幹雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP14116288A priority Critical patent/JPH01310589A/en
Publication of JPH01310589A publication Critical patent/JPH01310589A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4691—Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers

Landscapes

  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To simplify a connection so as to decrease a through-hole in space by a method wherein a conductive pattern formed on the front side of a thin board and another pattern formed on the rear side are electrically connected with each other through a wire lead which is inserted into a hole that penetrates the laminated structure. CONSTITUTION:A hard board 1 and a flexible printed board 2 laminated on the board 1 are bonded to each other, a hole 5 is provided to a specified place of both the boards 1 and 2 penetrating them, and an IC4 is connected with a pattern 11 on the rear side through the hole 5. Therefore, a J-shaped wire lead 51 whose tip is bent back is inserted into the through-hole 5 and the bent part of the lead 51 is joined to the rear pattern 11 as it is hooked up to the pattern 11, and the upper part of the J-shaped wire lead 51 is joined to a connecting pattern 21 at the upper part of the through-hole 5. By these processes, the interconnection can be realized through a small diameter hole of a large aspect ratio without using a through-hole which needs a plating process, so that a laminated board can be miniaturized and densified.

Description

【発明の詳細な説明】 ［産業上の利用分野１ この発明は電子機器の回路基板の高密度実装に関し、詳
しくは厚みの異なる複数枚の配線基板を積重した構造の
表と裏の電極の接続方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field 1] This invention relates to high-density mounting of circuit boards of electronic devices, and more specifically, to the mounting of front and back electrodes of a structure in which a plurality of wiring boards of different thicknesses are stacked. This relates to the connection method.

［発明の概要］ この発明は、硬質の多層印刷配線基板（以下硬質板と略
す）と、薄い可撓性印刷配線基板（フレキシブルプリン
ト基板）、（以下ＦＰＣと略す）を張り合せ、かつこの
ＦＰＣの表面には複数個の集積回路素子（以下ＩＣと略
す）を実装したいわゆるチップオンボーと称される構造
で、高密度を実現するに際し、硬質板とＦＰＣの間の相
互の接続手段を簡素化するとともに、従来のスルホール
手段に寄因するスペースの必要性及び回路パターンの制
約から解放されることを目的とするもので、そのために
ＦＰＣと硬質基板を積重した状態において両者を貫通す
る穴を設け、この穴にワイヤリードを挿通して両者の導
通パターン同士の接続を行うものである。[Summary of the Invention] The present invention involves laminating a hard multilayer printed wiring board (hereinafter referred to as a hard board) and a thin flexible printed wiring board (hereinafter referred to as an FPC), and This is a so-called chip-on-board structure in which multiple integrated circuit elements (hereinafter abbreviated as IC) are mounted on the surface of the board, and in order to achieve high density, the mutual connection method between the hard board and FPC is simplified. At the same time, the purpose is to be free from the space requirements and circuit pattern constraints caused by conventional through-hole means, and for this purpose, when an FPC and a hard board are stacked, a hole that passes through them is created. A wire lead is inserted into the hole to connect the two conductive patterns.

［従来の技術］ 従来の技術で、本発明の提唱する高密度実装の構造を実
現すれば、第２図に示す断面構造となる。この実施の好
例として、ドツトマトリックスの液晶パネルをＸ−Ｙ方
向に走査する駆動回路のＩＣを、液晶表示部の周辺に設
けたものを引用する０図示の硬質基板１は表示パネル全
体の基台となるもので、外部との接続、表示部との接続
などの機能を備え、これに接着剤３で積重して固着され
たＦＰＣ２は、その表面にＩＣ４やその他の電子部品を
搭載し、能動基板としての機能をはたしている。[Prior Art] If the high-density mounting structure proposed by the present invention is realized using the conventional technology, the cross-sectional structure shown in FIG. 2 will be obtained. As a good example of this implementation, an IC for a drive circuit that scans a dot matrix liquid crystal panel in the X-Y direction is provided around the liquid crystal display section.The hard substrate 1 shown in the figure is the base of the entire display panel. The FPC 2 has functions such as external connection and display connection, and is stacked and fixed with adhesive 3. The FPC 2 has an IC 4 and other electronic components mounted on its surface. It functions as an active substrate.

このような構造で課題となる要点を述べると、ＩＣ４の
パッド４１から、硬質基板１の裏面のパターン１１への
接続に際し、パッド４１からボンデングワイヤ４２でＦ
ＰＣ２の接続パターン２１に接続し、次にこの接続パタ
ーン２１から硬質基板１の表パターン１２との間を接続
＆’１１２２をはんだ付等で接続し、硬質基板１のスル
ホール１３により裏パターン１１に至っている。このよ
うな構造は硬質板１とＦＰＣ２は、その機能故に別個の
工程で製造され、積重された後に接続処理されるためで
、今後とも避けられない手順である。そこでこの構造と
手順のために多くの問題をもっていた。その一つは硬質
基板ｌは機械的な基台としての機能のためと複雑な配線
処理のため多層構造で硬い厚板となる。この厚板にスル
ホール１３を施すにはその深さＨと穴径りの比（Ｈ／Ｄ
　ニアスペクト比）を一定に保つため、その板厚に沿っ
た穴径となり、平面的スペースが必要で小型化、高密度
化ができなかった。次に第二点として、ＦＰＣ２はパッ
ド４１を多数持ったＩＣ４の端子を硬質基板１の表パタ
ーン１２に導くため接続パターン２１を備えているが、
この接続パッド２３の位置はＦＰＣの周辺２４に限られ
ている。そのため配線は長く浮遊容量は大きくなり、か
つ周辺を確保するため小型化できず問題であった。To explain the key points that arise in such a structure, when connecting the pad 41 of the IC 4 to the pattern 11 on the back surface of the hard substrate 1, the bonding wire 42 connects the pad 41 to the F.
Connect to the connection pattern 21 of PC2, then connect &'1122 from this connection pattern 21 to the front pattern 12 of the hard board 1 by soldering, etc., and connect it to the back pattern 11 through the through hole 13 of the hard board 1. It has been reached. This structure is because the hard board 1 and the FPC 2 are manufactured in separate processes due to their functions, and are connected after being stacked, a procedure that will continue to be unavoidable. There were many problems due to this structure and procedure. One of them is that the hard substrate l has a multilayer structure and is a hard thick plate because of its function as a mechanical base and because of complicated wiring processing. To make a through hole 13 in this thick plate, the ratio of the depth H to the hole diameter (H/D
In order to keep the near aspect ratio (near aspect ratio) constant, the hole diameter follows the thickness of the plate, requiring a planar space and making it impossible to downsize or increase density. Next, as a second point, the FPC 2 is equipped with a connection pattern 21 to guide the terminal of the IC 4 having a large number of pads 41 to the front pattern 12 of the hard substrate 1.
The location of this connection pad 23 is limited to the periphery 24 of the FPC. As a result, the wiring was long and the stray capacitance was large, and it was difficult to downsize the device due to securing the surrounding area, which was a problem.

［発明が解決しようとする課題］ 本発明は上述した問題点を解決するため、ＩＣ４のパッ
ド４１から硬質基板１の裏面のパターン１１への接続を
行うに際し、スルホール１３及び接続パッド２３と接続
！８２２の各部材を用いることなく接続するものである
。[Problems to be Solved by the Invention] In order to solve the above-mentioned problems, the present invention provides a connection between the through-hole 13 and the connection pad 23 when connecting the pad 41 of the IC 4 to the pattern 11 on the back surface of the hard substrate 1! This connection is made without using any of the 822 members.

［課題を解決するための手段］ 本発明は上述した問題となる部材を用いることなく硬質
基板１とそれに積重されたＦＰＣ２の両者が接着された
状態において、所定の位置で両者を貫通する穴を設け、
この穴を使ってＩＣ４と裏面のパターン１１を接続する
ものである。[Means for Solving the Problems] The present invention provides a method for forming a hole that penetrates a hard substrate 1 and an FPC 2 stacked thereon at a predetermined position in a state in which both are bonded to each other without using the problematic members described above. established,
This hole is used to connect the IC 4 and the pattern 11 on the back side.

［イ乍用１ 本発明は上記した貫通穴の中を、先端が折り返えされた
５字状のワイヤリードを挿通し、折り返久した部分が裏
パターンに引っかけられた状態で接合され、Ｊ字状ワイ
ヤリードの上方は貫通穴の上部の接続パターンに接合さ
れる。[Use 1] The present invention includes inserting a 5-shaped wire lead whose tip is folded back through the above-mentioned through hole, and joining the wire lead with the folded back part hooked to the back pattern, The upper part of the J-shaped wire lead is joined to the connection pattern on the upper part of the through hole.

［実施例］ 第１図は、本発明による接続を施す回路基板の断面図で
、第２図と共通する部材は同じ符番となっている。硬質
基板１とＦＰＣ２は表面にＩＣ４を搭載して接着剤３で
積重されている。ここで硬質基板１の表パターン１２と
裏パターン１１を接続するスルホール１３、硬質基板１
の表パターン１２とＦＰＣの接続パッド２３とを接続す
る接続線２２は従来の構造と同じである。このような構
造の回路基板に対し、本発明の特徴はＦＰＣ２の周辺部
２４とＩＣ４との間の領域にキリ穴による貫通穴５を設
け、この貫通穴の開口部の上面は接続パターン２１のラ
ンド部２５があり、下面は裏面のパターン１１の裏ラン
ド１４がある。これら位置の確保は設計的に定められる
ものであり、貫通穴５の穴径はスルホール１３より小径
でたりる。次に本発明の別の特徴は、上記貫通穴５を挿
通して上下面のパッドを導通するワイヤリード５１にあ
る。第３図Ａ、Ｂ、Ｃはこのワイヤリード５１を接合す
る工程の概略を示す断面図で、ワイヤリード５１はその
先端を図示してない整形機により略Ｊ字型に折曲され、
同図Ａに示すようにガイド穴６１から矢示ａの方向に挿
通される。次に同図Ｂに示す矢示すのように上方に引張
るとワイヤリードの先端のあご部５２が裏ランド１４に
引っかかり位置を定める。このとき下面溶接ヘッド６１
がワイヤリード５１を裏ランド１４に圧接しながら通電
６２により両者を接合する。次に同図Ｃに示すようにガ
イド６０が矢示Ｃの方向に移動しワイヤリード５１とラ
ンド部２５の位置が定まる。この状態で上面溶接ヘッド
６３で両者を圧接し通電６４により接合する。そして図
示していないがワイヤリード５１は接合部をランド部２
５に残して切断され、第１図に示すワイヤリード５１の
状態になる。なお接合の手段について、ここでは加熱ヘ
ッド方式で説明したがこの他の抵抗溶接、パラレルギャ
ップなどでもよい。[Example] FIG. 1 is a cross-sectional view of a circuit board to which a connection according to the present invention is applied, and parts common to those in FIG. 2 have the same reference numbers. A hard substrate 1 and an FPC 2 have an IC 4 mounted on their surfaces and are stacked together with an adhesive 3. Here, through holes 13 connecting the front pattern 12 and back pattern 11 of the hard substrate 1, the hard substrate 1
The connection line 22 connecting the front pattern 12 and the connection pad 23 of the FPC has the same structure as the conventional structure. For a circuit board having such a structure, a feature of the present invention is that a through hole 5 is provided in the area between the peripheral part 24 of the FPC 2 and the IC 4, and the upper surface of the opening of this through hole is connected to the connection pattern 21. There is a land portion 25, and the back land 14 of the pattern 11 on the back surface is located on the lower surface. Securing these positions is determined by design, and the diameter of the through hole 5 is smaller than that of the through hole 13. Another feature of the present invention is the wire lead 51 that passes through the through hole 5 and connects the pads on the upper and lower surfaces. 3A, B, and C are cross-sectional views showing the outline of the process of joining this wire lead 51, in which the tip of the wire lead 51 is bent into a substantially J shape by a shaping machine (not shown).
As shown in FIG. 5A, it is inserted through the guide hole 61 in the direction of arrow a. Next, when the wire lead is pulled upward as indicated by the arrow shown in FIG. At this time, the lower surface welding head 61
While pressing the wire lead 51 against the back land 14, the two are connected by applying electricity 62. Next, as shown in Figure C, the guide 60 moves in the direction of arrow C, and the positions of the wire lead 51 and the land portion 25 are determined. In this state, the upper surface welding head 63 presses them together and they are joined by applying electricity 64. Although not shown, the wire lead 51 connects the bonded portion to the land portion 2.
5, the wire lead 51 is cut as shown in FIG. As for the means of joining, although the heating head method has been described here, other methods such as resistance welding, parallel gap, etc. may be used.

［発明の効果］ 以上述べたように、本発明によればＩＣを搭載したＦＰ
Ｃの表面と、それと積重した硬質基板の裏面を貫通穴を
介してワイヤリードで導通することにより、 （１）、メツキ工程を要するスルホールを使うことなく
、アスペクト比の大きな小径穴で実現でき小型高密度化
が実現できる。[Effects of the Invention] As described above, according to the present invention, an FP equipped with an IC
By connecting the surface of C and the back surface of the hard substrate stacked on it with a wire lead through a through hole, (1) it can be realized with a small diameter hole with a large aspect ratio without using a through hole that requires a plating process. Small size and high density can be achieved.

（２）、上、下面を接合する位置が限定されることなく
自由度があり設計が容易になる。(2) The position where the upper and lower surfaces are joined is not limited and there is a degree of freedom, which facilitates the design.

（３）、ワイヤリードによる上下面の接合で自動化がで
きる。(3) Automation is possible by joining the upper and lower surfaces using wire leads.

などチップオンボードと硬質機能基板を積重する構造の
高密度化に大きな効果を有するものである。This has a great effect on increasing the density of structures in which chip-on-boards and rigid functional boards are stacked.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明の主要部を示す断面図。 第２図は、従来の機能基板を示す断面図。 第３図Ａ、Ｂ、Ｃは、本発明のワイヤリードの接合の工
程を示す断面図。 ■・・・硬質基板 ２・・・ＦＰＣ ３・・・接着剤 ４・・・ＩＣチップ ５・・・貫通穴 １１・・・裏パターン １４・・・裏ランド ２１・・・接続パターン ２５・・・ランド部 ５１・・・ワイヤリード ５２・・・あご部 ６０・・・ガイド ６１・・・下面溶接ヘッド 以上 出願人　セイコー電子工業株式会社 代理人　弁理士　　林　　　敬　之　肋本４注日月り導
通を示１節面四］ Ｙ）２図 △挿通　　　　　　　ＢＴｊ妾合　　　　　　Ｃ上蒋令
本゛迦明の接合工程６示オ前面図 第３図FIG. 1 is a sectional view showing the main parts of the present invention. FIG. 2 is a sectional view showing a conventional functional board. FIGS. 3A, B, and C are cross-sectional views showing the process of bonding wire leads of the present invention. ■...Hard board 2...FPC 3...Adhesive 4...IC chip 5...Through hole 11...Back pattern 14...Back land 21...Connection pattern 25...・Land part 51...Wire lead 52...Jaw part 60...Guide 61...Bottom welding head and above Applicant Seiko Electronics Co., Ltd. Agent Patent attorney Takayuki Hayashi Subscript 4 notes Date and month continuity Figure 3 shows front view of joining process 6 of Jiang Lingben ゛迦明.

Claims (1)

【特許請求の範囲】[Claims] 半導体集積素子を搭載した薄い回路基板と、該薄い回路
基板を接着で積重した比較的厚味のある硬質基板よりな
る積重構造の基板において、前記薄い回路基板の表面の
導電パターンと、前記硬質基板の裏面の導電パターンと
を、前記積重構造を貫通した穴に挿通したワイヤリード
により導通したことを特徴とする積重基板の表裏導通構
造。A board having a stacked structure consisting of a thin circuit board on which a semiconductor integrated element is mounted, and a relatively thick hard board made by stacking the thin circuit boards with adhesive, the conductive pattern on the surface of the thin circuit board; 1. A front-back conductive structure for a stacked board, characterized in that the conductive pattern on the back side of the hard board is electrically connected to the conductive pattern on the back side of the hard board by a wire lead inserted through a hole penetrating the stacked board.
JP14116288A 1988-06-08 1988-06-08 Front-rear continuity structure of laminated board Pending JPH01310589A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14116288A JPH01310589A (en) 1988-06-08 1988-06-08 Front-rear continuity structure of laminated board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14116288A JPH01310589A (en) 1988-06-08 1988-06-08 Front-rear continuity structure of laminated board

Publications (1)

Publication Number Publication Date
JPH01310589A true JPH01310589A (en) 1989-12-14

Family

ID=15285576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14116288A Pending JPH01310589A (en) 1988-06-08 1988-06-08 Front-rear continuity structure of laminated board

Country Status (1)

Country Link
JP (1) JPH01310589A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001059829A2 (en) * 2000-02-10 2001-08-16 Bull S.A. Method for mounting integrated circuits on a conductor support and resulting support
JP2007157771A (en) * 2005-11-30 2007-06-21 Matsushita Electric Ind Co Ltd Printed wiring board and method of forming its continuity
JP2008536311A (en) * 2005-04-08 2008-09-04 マイクロン テクノロジー， インク． Semiconductor component manufacturing method and system by through wire interconnection
US9013044B2 (en) 2005-12-07 2015-04-21 Micron Technology, Inc. Through wire interconnect (TWI) for semiconductor components having wire in via and bonded connection with substrate contact
US9018751B2 (en) 2006-04-24 2015-04-28 Micron Technology, Inc. Semiconductor module system having encapsulated through wire interconnect (TWI)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001059829A2 (en) * 2000-02-10 2001-08-16 Bull S.A. Method for mounting integrated circuits on a conductor support and resulting support
FR2805083A1 (en) * 2000-02-10 2001-08-17 Bull Sa METHOD FOR MOUNTING AND MANUFACTURING INTEGRATED CIRCUITS ON A SUPPORT AND SUPPORT THEREFOR
WO2001059829A3 (en) * 2000-02-10 2002-03-28 Bull Sa Method for mounting integrated circuits on a conductor support and resulting support
JP2008536311A (en) * 2005-04-08 2008-09-04 マイクロン テクノロジー， インク． Semiconductor component manufacturing method and system by through wire interconnection
JP4936078B2 (en) * 2005-04-08 2012-05-23 マイクロン テクノロジー， インク． Semiconductor component manufacturing method and system by through wire interconnection
JP2007157771A (en) * 2005-11-30 2007-06-21 Matsushita Electric Ind Co Ltd Printed wiring board and method of forming its continuity
US9013044B2 (en) 2005-12-07 2015-04-21 Micron Technology, Inc. Through wire interconnect (TWI) for semiconductor components having wire in via and bonded connection with substrate contact
US9018751B2 (en) 2006-04-24 2015-04-28 Micron Technology, Inc. Semiconductor module system having encapsulated through wire interconnect (TWI)

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