JPH01309597A - Television standards converter - Google Patents

Abstract

PURPOSE:To smoothly correct even a picture to move in parallel and another picture having a wide moving picture area by detecting a dynamic vector at the side of a luminous signal, correcting the positions of the luminance signal and a color difference signal according to the detected dynamic vector, and after that executing a field interpolation. CONSTITUTION:A second detecting means 13 detects the dynamic vector for every mXn block for the output signal, which is separated for one field, of a first selecting means 12, and deciding means 15 decides the effectiveness of the detected dynamic vector and outputs the dynamic vector only when it is decided that the dynamic vector is effective. A converting means 16 converts the decided dynamic vector for every block into another dynamic vector corresponding to a scanning line, and a correcting means 17 changes a reading address for the value of the product of the line-converted dynamic vector and a field interpolation ratio, outputs the contents of a memory at the side of a Y signal and the contents of another memory at the side of a C signal, corrects the positions of the luminance signal and the chrominance signal, executes the field interpolation, and obtains the Y signal and the C signal. Thus, the picture can be smoothly corrected even if the picture is the one to move in parallel or the one having the wide animation area.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a television standard format conversion device for converting one television signal into the other television signal in two television formats having different scanning formats. In particular, it relates to field interpolation using motion vectors.

(Prior art) Television standard format conversion requires converting the number of scanning lines and converting the number of fields, and these conversions generally involve digitizing the television signal and storing it in a memory with a capacity of two or more fields. This is done by controlling the address counter at the time of reading.

FIG. 16 is a block diagram showing a configuration example of a television standard format conversion device (hereinafter referred to as TV format conversion device) that manually converts digitized component signals, that is, a luminance signal Y and color difference signals R-Y and B-Y. It is a diagram. T in the same figure
The V system conversion device includes a multiplex circuit 21, memories 22a, 22
b, line interpolation circuits 23a to 23d, and field interpolation circuits 24a and 24b.

The digitized Y signal is input to a memory 22a having a capacity of 2 fields, and the color difference signals, RY and BY, are input to a multiplex circuit 21. The multiplex circuit 21 includes R-Y,
B-Y is time-division multiplexed, and its output is sequentially written into a memory 22b having a capacity of two fields. below,
This multiplexed color difference signal is referred to as a C signal. memory 22
In a, signals of two fields are read out at the same time. When reading from the memory 22a, an address counter (not shown) is controlled to increase or decrease the number of scanning lines. The output signals of the memory 22a are input to line interpolation circuits 23a and 23b, respectively. Here, image distortion caused by an increase or decrease in the number of scanning lines is corrected using signals from several adjacent lines within the same field. Thereafter, the field interpolation circuit 24a corrects the discontinuity of the moving image caused by the increase or decrease in the number of fields by linear interpolation between fields. The operation for the C signal is almost the same as for the Y signal. Line interpolation processing methods in the line interpolation circuits 23a to 23d include linear interpolation using signals from two adjacent lines within the same field, and digital interpolation using signals from several adjacent lines within the same field. There are also filter methods. Although resolution deterioration is less when using a digital filter, a method for further reducing resolution deterioration is to use adjacent signals between fields. However, when using signals between fields, good correction can be made for still images because the correlation between signals within a field and the correlation between signals between fields is large, but for moving images , the signal correlation between fields becomes small, and when interpolation processing is performed using signals between fields, distortion occurs in the image. Therefore, when using line interpolation processing between fields, it is necessary to apply this only to still images, and to perform line interpolation processing within fields for moving images. For this purpose, a new motion detection function is required.

FIG. 17 is a block diagram showing an example of the configuration of a TV system converter having this motion detection circuit and using an inter-field/intra-field adaptive line interpolation method. In the figure, the same reference numerals as in FIG. 16 indicate the same components, and the delay circuits 25, 27a, 27a,
27b, motion detection circuit 26, memory 29, line interpolation circuits 30a, 30b, delay circuit 31a.

31b, and switching circuits 32a and 32b are added. Motion detection is performed using the Y signal. The delay circuit 25 is constructed using a FIFO memory with a capacity of 1 frame or a normal memory for motion detection. The motion detection circuit 26 performs motion detection using signals separated by one frame obtained by the manual input and output of the delay circuit 25. For example, after calculating the difference between one frame for each pixel, A two-dimensional low-pass filter removes noise components, and if the output level of this low-pass filter is greater than a threshold, it is determined that there is movement. A 1-bit motion detection signal indicating the presence or absence of motion detected in this manner is stored in a memory 29 having a two-field capacity. On the other hand, the Y signal and the C signal are delayed by the time required for motion detection by delay circuits 27a and 27b, and then sent to the memory 2.
2a and 22b, respectively. memory 22a,
As shown in the figure, the output of 22b is manually inputted to line interpolation circuits 23a to 23d within the same field, and line interpolation circuits 30a and 30b that perform line interpolation processing between fields, and is input to line interpolation circuit 238. The signal subjected to line interpolation within the field at ~23d is sent to the field interpolation circuit 24.
After the moving images are corrected (field interpolation processing) in a and 24b, they are manually inputted to switching circuits 32a and 32b. Line interpolation circuit 30a.

The signal subjected to the interfield line interpolation process in step 30b is used only for still images, so there is no need for motion correction. For this purpose, the field interpolation circuit 24a.

24b and is inputted to switching circuits 32a and 32b via delay circuits 31a and 31b. The motion detection signals of each field read out in parallel from the memory 29 are sent to an OR circuit 31.
After the logical OR is taken, the signals are manually input to the switching circuits 32a and 32b. As a result, when the motion detection signal of any field indicates the presence of motion ("1'") (during a moving image), the switching circuits 32a and 32b switch the field interpolation circuit 24a.
, 24b are selected and output. On the other hand, there is no movement in the motion detection signal of the field "o".
) (at the time of a still image), the delay circuits 31a, 3
The output signal 1b (that is, the signal subjected to line interpolation processing between fields) is selected by the switching circuits 32a and 32b and output.

(Problem to be Solved by the Invention) However, in the TV system converter having the above configuration, image distortion caused by an increase or decrease in the number of scanning lines can be corrected with little deterioration in resolution, but the distortion caused by an increase or decrease in the number of fields can be corrected. Discontinuities cannot be completely corrected by linear interpolation processing using signals between fields, and this lack of smoothness of movement becomes especially noticeable for images that move in parallel or signals that cover a wide video area. There is a problem that

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a TV format conversion device that can smoothly correct even images that move in parallel or images that have a wide moving image area.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a first memory having a capacity of two or more fields and storing a digitized luminance signal, and a first memory having a capacity of two or more fields. a second memory for storing digitized and quantified color difference signals; a first line interpolation means for performing line interpolation on the output signal of the first memory using line information in the same field; a second line interpolation means that performs line interpolation using line information between two fields; and a second line interpolation means that performs line interpolation using line information within the same field on the output signal of the second memory. a fourth line interpolation means for performing line interpolation using line information between two fields interlaced with respect to the output signal of the second memory; and a first detection means. a first selection means for selecting one of the output signals of the first and second line interpolation means based on the detection result; and outputs of the third and fourth line interpolation means based on the detection result. and a second selection means for selecting one of the signals, the output signals of the first selection means separated by one field are divided into m pixels×n pixels.
a second detection means that divides into blocks of lines (m, n; integer) and detects a motion vector for each block; and determines whether the motion vector detected by the second detection means is valid or invalid; determining means for outputting the motion vector when determining validity; converting means for converting the output signal of the determining means into a motion vector corresponding to a scanning line; and converting the output signal of the first selecting means for each field. third and fourth memories each having a capacity of two L (n or more) lines for storing, and two fL (n or more) lines for storing the output signal of the second selection means corresponding to each field. The contents of the third to sixth memories are output by changing the read address by the product of the motion vector from the converting means and the field interpolation ratio of the fifth and sixth memories each having a capacity of one line. a first field interpolation means for performing field interpolation on the output signals of the third and fourth memories; and a second field interpolation means for performing field interpolation on the output signals of the fifth and sixth memories. A field interpolation means is provided.

(Operation) The present invention operates as follows. The first selection means (for example, a switching circuit described later) on the luminance signal (Y signal) side selects the first and second line interpolation means based on the detection result of the first detection means (for example, a motion detection circuit, etc.). The second selection means on the side of the multiplexed color difference signal (C signal) operates to adaptively select and output one of the output signals, and the second selection means on the side of the multiplexed color difference signal (C signal) similarly selects and outputs one of the output signals from the third and fourth line interpolation means. It works to adaptively select and output one of the signals. The second detection means (for example, a motion vector detection circuit to be described later) uses the output signals of the first selection means separated by one field to detect a motion vector for each mxn block. The motion vector determination circuit (motion vector determination circuit) determines whether the detected motion vector is valid or invalid, and outputs the motion vector only when it is determined to be valid.The conversion means (for example, a memory described later) converts the determined motion vector for each block. to a motion vector corresponding to a scanning line (line).The correction means (for example, a correction circuit in a field interpolation circuit described later) converts the value of the product of the line-converted motion vector and the field interpolation ratio. Change the read address by Y
It functions to output the contents of the third and fourth memories on the signal side and the contents of the fifth and sixth memories on the C signal side.

As a result, position correction is performed on the signals (video lines) from the first and second selection means, and the signals are corrected by the conventional first and second field interpolation means (for example, the calculation field interpolation is performed by the circuit) to obtain the output component signals (Y signal, C signal) of the desired scan formation. In this way, since the position of the moving image is corrected according to the detected motion vector, the problems of the prior art described above can be solved.

(Margin below) (Embodiment) FIG. 1 is a block diagram of a TV format conversion apparatus showing a first embodiment of the present invention. In the figure, la.

lb and lc are input terminals for inputting input component signals, 2a and 2b are output terminals for outputting converted output component signals, and 3 is a human input signal from input terminal 1a (
4 is a detection circuit (corresponding to the above-mentioned first detection means) that detects motion using the input/output signal of delay circuit 3; 5a and 5b are motion detection circuits; Delay circuit that delays the human input signal by time, 6 is input terminal lb
, a multiplexing circuit that time-division multiplexes the color difference signals R-Y and B-Y from the lc; 7 is a memory having a capacity of 2 fields and stores a motion detection signal indicating the presence or absence of movement; 8a and 8b are 2 fields; memory (the above-mentioned first and second
9 is an OR circuit that calculates the logical sum of the output signals of each field of the memory 7, and 10a to 10d are output signals of the memories 8a and 8b to select any line using the line information in the same field. A line interpolation circuit that performs line interpolation at an interpolation ratio (corresponding to the above-mentioned first and third line interpolation means), lla and llb are memories 8a and 8
A line interpolation circuit that performs line interpolation at an arbitrary line interpolation ratio using line information between two fields interlaced with respect to the output signal of
(equivalent to line interpolation means), 12a and 12b are OR
A line interpolation circuit 10a based on the output signal of the circuit 9,
A switching circuit (corresponding to the above-mentioned first selection means) 12c that selects and outputs one of the output signals of Job and the line interpolation circuit 11a.

12d is line interpolation 1 based on the output signal of OR circuit 9.
A switching circuit 12e selects and outputs one of the output signals of 0c, 10d and the output signal of the line interpolation circuit 11b (corresponding to the above-mentioned second selection means), and 12e selects and outputs one of the output signals of the line interpolation circuit 11b, and the switching circuit 12e selects and outputs one of the output signals of the line interpolation circuit 11b. 13 is a motion vector detection circuit that detects motion vectors in block units of m pixels x n lines (m and n are integers) from the output signal of the switching circuit 12e; 14 is a motion vector detection circuit that detects the detected motion vectors; A motion vector averaging circuit 15 determines whether the averaged motion vector is valid or invalid based on the output signal of the switching circuit 12e, and outputs "0" when the motion vector is determined to be valid and "0" when determined to be invalid. A motion vector determination circuit, 16 a memory for converting a motion vector in units of blocks into a motion vector corresponding to a scanning line (corresponding to the above-mentioned conversion means), 17a an output of the switching circuits 12a and 12b based on the output signal of the memory 16; A field interpolation circuit 17b performs position correction and field interpolation on the signal, and switching circuits 12c and 12b are based on the output signal of the memory 16.
This is a field interpolation circuit that performs position correction and field interpolation on the output signal of d.

Note that in this embodiment, the memories 7.8a and 8b.

Control means such as 16 are omitted to simplify the explanation. Further, it is assumed that switching signals for the switching circuit 12e and the like are given by a control section (not shown) that controls the entire device.

The operation of the TV system changing device configured as above will be explained.

Digitized component signal Y.

Of the R-Y and B-Y, the color difference signals R-Y and B-Y input manually from the input terminals 1b and lc are time-division multiplexed by a multiplexing circuit 6. Sampling frequency of Y signal and color difference signal is 2:
1, the multiplex circuit 6 has R-Y, B-Y, and R-Y for each pixel based on the Y signal. This multiplexed color difference signal (C signal) and Y
The signals are sent to the memory 8a via delay circuits 5a and 5b, respectively.
, 8b. These memories 8a.

When reading out the data 8b, the number of scanning lines and the number of fields are converted by controlling the read address of the memory using an address counter (not shown). That is,
The number of scanning lines is converted by thinning out and repeatedly inserting scanning lines (lines), and the number of fields is also converted by thinning out and repeatedly inserting fields. However, the conversion of the number of fields is actually performed by controlling the field interpolation ratio of the field interpolation circuit.

On the other hand, the Y signal manually inputted from the input terminal 1a is directly inputted to the motion detection circuit 4, and is also inputted after being delayed by one frame by the delay circuit 3. In the motion detection circuit 4, for example, a frame difference is calculated for each pixel, noise components are removed from the value using a two-dimensional low-pass filter, and the number of pixels for which the output value of the filter exceeds a threshold value α is equal to or greater than a threshold value α2. If so, the surrounding α3 pixel area centered on that pixel is determined to be in motion. However, αl, α2. α3 has a variable setting and is set to a fixed value, and the optimum value is determined based on the image signal.

However, in order to reduce line interpolation distortion, detection is made to be sensitive to moving images.

A motion detection signal indicating the presence or absence of motion is written into the memory 9. Writing and reading control of this memory 9 is exactly the same as that of the field conversion memories 8a and 8b. memory 9
The output signals for each field are inputted to the OR circuit 10 and the logical sum is taken.

As a result, if the motion detection signal of either field indicates that there is movement (1"), "1" means a moving image.
is output, and when the motion detection signals of both fields indicate "0" (no motion), "0" indicating a still image is output.

Two fields of signals are read out from the memories 8a and 8b at the same time. Y of each field read from memory 8a
The signals are input to line interpolation circuits 10a and 10b to undergo line interpolation within a field, and are input to line interpolation circuit 11a to undergo line interpolation between fields. Similarly, the C signal of each field read from the memory 8b is subjected to line interpolation within the field by line interpolation circuits 10c and 10d, and line interpolation between fields is performed by the line interpolation circuit 11b. . As mentioned above, the line interpolation processing of the line interpolation circuits 10a to 10c is performed by linear interpolation using signals from two adjacent lines in the same field, or by performing linear interpolation using signals from several adjacent lines in the same field. However, whichever interpolation method is used, an interlace interpolation processing function is also required.

Originally, TV format converters have an independent synchronization method for the input side and conversion output side, and since the television signal is an interlaced signal, a memory with a capacity of 2 fields is used to convert field by field. The field conversion performed by the conversion device is: ■ Odd field f'' (1st) → Odd field (1st), ■ Even field (2nd) -
+ Even field (2nd), ■ Odd field (1s
There are four cases: t)→even field (2ncl), and (2) even field (2nd)→odd field (1st). Typically, for homogeneous field transformations (■.

In the case (2), the center of gravity of the image before and after conversion does not change, but in the case of heterogeneous conversion (cases (2) and (2)), the center of gravity of the image before and after conversion moves up or down by one line. For example, from 60 fields to 5
In the case of 0 field (or vice versa) conversion, we convert from 6 fields to 5 fields (or vice versa), so
The center of gravity shifts every 6 fields (or every 5 fields).

Interlace interpolation processing moves this center of gravity by moving the center of gravity forward by advancing the signal within the field by one line in heterogeneous field conversion,
It also delays the signal, and at the same time uses the signal within the field to correct it. Therefore, the line interpolation circuits 10a to 10d output signals are signals that have undergone not only line interpolation processing but also interlace interpolation processing, and the centers of gravity of the images of the two line interpolation circuit output signals 21 and 22 are corrected to match. (For details, see Utility Model Publication No. 60-2519.
(Disclosed in Publication No. 0). An example of line interpolation processing between fields including this interlace interpolation processing is shown in FIGS. 2 and 3. FIG. 2 is an enlarged view of the diagonal line pattern in the original signal. In the same figure, white circles indicate odd fields (1
st), the white square mark is an even field (2nd) signal. FIG. 3 shows the line number conversion and line interpolation processing when the output side is an even field in the 525→625 format. In the same figure, white circles indicate the case of ■ above (1
s, t → 1st), the white square mark is ■ (2nd → 1st)
The black circles and black squares indicate one-line (IH) delayed signals, respectively. Also, the line interpolation ratio (128=100!) in the same figure is shown corresponding to the line number,
H indicates the line interpolation ratio of the signal, and IH indicates the line interpolation ratio of the signal delayed by one line. The broken lines in the figure indicate the memory 8a,
8b is a signal that is line-converted during reading, and the solid line is a signal obtained by line interpolation. In this case, the signal of the same line is inserted every 5 lines by line conversion, and the position of the repeatedly inserted line is as follows:
In order to reduce distortion in this discontinuous portion and for interlace interpolation, three lines are changed for each field. Although the figure shows an interpolation method using two adjacent lines, which is easy to explain, the method is basically the same when a digital filter is used.

The line interpolation process between fields of the line interpolation circuits 11a and 11b performs interpolation using two adjacent lines between fields. An example of this case is shown in FIG.
As shown in the figure, even in the case of line interpolation between fields, line interpolation processing is performed in consideration of interlace interpolation. Furthermore, the centroids of the images for intra-field line interpolation and inter-field line interpolation are corrected so that they are the same, as shown in FIGS. 3 and 4.

As shown in FIG. Then, the switching circuits 12a and 12b are manually operated. Similarly, on the C signal side, line interpolation circuits 10c and 1
The output signal of 0d and the output signal of the line interpolation circuit 11b are input to switching circuits 12c and 12d. Note that in this embodiment, unlike the case shown in FIG. 17, as shown in FIG.
, Ilb are output to field interpolation circuits 17a and 17b via switching circuits 12a to 12d.
Since the same signal is input to each field interpolation circuit, the result is the same as when field interpolation processing is not performed.

In the switching circuits 12a to 12d, when the output signal of the OR circuit 9 indicates a moving image (“1'°), the line interpolation circuits 10a to 12d
The line interpolation circuit 11a selects and outputs the output signal of 10d to indicate a still image (°0'').

11b is selected and output.

In this way, the output signal of the intra-field or inter-field line interpolation circuit is adaptively switched by the switching circuit based on the output signal of the OR circuit 9, and the output signal of the switching circuits 12a and 12b on the Y signal side is Field interpolation circuit 17
a and the switching circuit 12e, and the switching circuit 1 on the C signal side
The output signals of 2c and 12d are input to a field interpolation circuit +7b.

The switching circuit +2e rearranges the human input signals from the switching circuits 12a and 12b into temporally earlier fields based on the switching signal from the control section (not shown), and uses the temporally earlier signals as the current field signal. , the signal one field before that is defined as the previous field signal. The output signal of this switching circuit 12e is inputted to a motion vector detection circuit 13 and a motion vector determination circuit 15.

The motion vector detection circuit 13 is one from the switching circuit 12e.
A motion vector is detected for each block of m pixels x n lines (m, n: integer) using signals from two fields separated by fields. Here, a block of 8 pixels x 8 lines with m-n=8 is used as a reference block, and a motion vector is detected over the entire screen for each block. The block matching method and the iterative gradient method are well-known methods for detecting motion vectors that can be processed in real time, but it is especially important for method conversion devices that use field interpolation to accurately detect motion. Since it is desirable to have a smaller circuit scale, we use the iterative gradient method. The details are disclosed in Japanese Patent Application Laid-Open No. 158786/1986.

FIG. 5 shows a motion vector detection circuit 13 using the iterative gradient method.
FIG. 2 is a block diagram showing a configuration example. In the same figure, 51
52 is a selection circuit that selects a motion vector as an initial deviation vector from the motion vectors; 53 is a gradient using a signal between fields whose position is shifted by the initial deviation vector; an arithmetic circuit for calculating the modulus, 54 an adder that adds the arithmetic result of the arithmetic circuit 53 and the initial deviation vector of the output of the selection circuit 52;
56 is an arithmetic circuit that performs a gradient method calculation using a signal between fields deviated by the value of the output of the adder 54, and 56 is a motion vector that adds the arithmetic result of the arithmetic circuit 55 and the deviation amount. This is an adder that outputs.

Motion vectors are detected as one block of 8 pixels x 8 lines, but in calculations using the iterative gradient method, signals within a block of 20 pixels x 16 lines are used because calculation accuracy is improved with a wider block. However, in this case, 20 pixels x
Since using all the pixels in 16 lines would increase the size of the calculation circuit, every other pixel and every other line (total number of pixels: 800 pixels, 10 pixels x 8 lines) is used for the iterative gradient method calculation.

FIG. 6(a) shows the positional relationship between the motion vector detection block size and the calculation block of the iterative gradient method, and FIG. 6(b) shows candidate vectors for the initial deviation vector.

The memory 51 stores previously detected motion vectors, and the selection circuit 52 selects an initial deviation vector from the stored motion vectors. Candidate vectors for the initial deviation vector are the following six types of motion vectors.

In FIG. 6(b), the block where the motion vector is detected is indicated by a diagonal line, and the motion vector detected in this block is indicated by B. -(■X(0).

■, (01), and the already detected motion vectors of surrounding blocks based on this block are 01
- Indicated by C19. The six types of motion vectors are: ■ Motion vector of the block directly above the detected block in the current field: C
I ■Motion vector of the block directly above and to the left of the detected block in the current field: 02 ■Motion vector of the block to the left of the detected block in the current field 203 ■Motion vector detected in the previous field directly below the detected block 2011 ■Previous field Average vector of: ■ Acceleration vector of previous field: Therefore, the capacity of the memory memory 51 is such that these motion vectors can be read out from the memory.

The selection circuit 52 selects the motion vector closest to the true motion from the six types of motion vectors described above as the initial deviation vector. The selection method is to select between the signal of the previous field and the detected block of the current field and the block whose block coordinates are shifted by the amount of each motion vector.
The field difference value for each pixel is calculated, the block where the sum of the absolute values is the minimum is detected, and the motion vector giving that block is set as the initial deviation vector.

FIG. 7 is a block diagram showing an example of the internal configuration of the selection circuit 52;
The selection circuit 52 in the figure includes a memory 521 that stores the current field signal, and six memories 522a to 522f that store the previous field signal corresponding to six types of motion vectors.
, 6 subtractors 523a to 523f, 6 absolute value circuits 524a to 524f, 6 accumulators 525a
525f, five comparators 526a to 526e, four switching circuits 527a to 527d, and a motion vector selection circuit 528.

Among the output signals of the switching circuit 12e, the current field signal is manually input to the memory 521. This memory 521 extracts the signal for each scanning line of the switching circuit 12e as a block-by-block signal, and its storage capacity needs to be 16 lines or more when the calculation block size is 20 pixels x 16 lines. becomes. p with 9 pixels per line
FIG. 8 is an explanatory diagram of the operation of the memory 521 when converting a line human input signal into a block of 8 pixels x 8 lines. Since the calculation block of the iterative gradient method is 10 pixels x 8 lines, every other pixel and every other line, in this case, the output of the memory +51 is a signal for every other pixel and every other line.

Six signals of the previous field are sent from the switching circuit 12e to the memory 5.
22a to 522f are manually operated. These memories 522
The other human power of a to 522f contains six types of motion vectors (candidate vectors) CI', C2, C3, C4, τ read out from the memory 51 as shown in FIG.

C' are respectively input. These memories 522a~
The function of the memory 522f is basically the same as that of the memory 521, but it also has the function of shifting the read address by -a human motion vector when reading. Therefore, signals for each block shifted by the input motion vector from each memory (522a to 522f) are inputted to the corresponding six subtraction circuits 523a to 523f. Each subtraction circuit (523
a to 523f), each block has memories 521 to 8
0 pixels and 8 from memories 522a to 522f
00 pixel difference (field difference in this case) is calculated. The outputs of these subtraction circuits 523a to 523f are converted into absolute values by corresponding absolute value circuits 524a to 524f, and then input to corresponding accumulators 525a to 525f.
Accumulation of pixels other than 0 pixels is performed. Accumulators 525a, 525
The cumulative result of b is input to the comparison circuit 526a, and
The switching circuit 527a is manually operated. An output signal indicating the comparison result of the comparison circuit 526a is outputted to the motion vector selection circuit 528 as a control signal for the switching circuit 527a to select the one with the smaller accumulated result among the output signals of the accumulators 525a and 525b. The output signal of the selected switching circuit 527a is input to a comparator 526b, where it is compared with the output signal of an accumulator 525c. According to this comparison result, the smaller accumulated result is selected by the switching circuit 527b and inputted to the comparator 526c. In this way, the output signals of accumulators 525d, 525e, and 525f are sequentially compared by comparison circuit 526c and switching circuit 527c, comparator 526d and switching circuit 527d, and comparator 526e.

The motion vector selection circuit 528 receives six types of motion vectors C, , C2, C3, C4, C, and C' and the output signals of five comparison circuits 526a to 526e, and six types of accumulation circuits 525a to 525e. The motion vector with the smallest cumulative result in 525f is selected. This selected signal becomes the initial deviation vector, which is applied to the arithmetic circuit 53 and the adder 5.
4 will be done manually.

The calculation circuit 53 of the gradient method calculates the deviation vectors V1) and vy0+ using the following equations (1) to (4).

However, SGNΔX is the sign of ΔX, SGNΔy is the sign of Δy, and DFD is the inter-field difference value, a, b.

c, d are adjacent pixels in the current field of the reference pixel e. Their positional relationship is shown in FIG. 9(a).

FIG. 1O is a block diagram showing an example of the internal configuration of the arithmetic circuit 53 (55). The arithmetic circuit 53 in the figure is the shift circuit 5
31.532, three subtraction circuits 533a, 533b,
533c, four memories 534a to 534d, and two absolute value circuits 535a.

535b, four accumulation circuits 536a to 536d, two sign calculation circuits 537a, 537b, two fractional circuits 53
8a, 538b, and two multiplication circuits 539a, 539
Consists of b.

Among the output signals of the switching circuit 12e, the current field signal is sent to a 2-bit delayed shift circuit 531 and a subtraction circuit 533a.
, a two-line delay shift circuit 532, and a subtraction circuit 532b.
, and are manually stored in the memory 534e. On the other hand, the previous field signal is input to the memory 534d.

The subtraction circuit 533a subtracts the output signal of the shift circuit 531 from the human input signal of the current field, thereby achieving the above (3).
This is to obtain ΔX and SGNΔX of the equation, and the subtraction circuit 5
33b is a shift circuit 532 from the human input signal of the current field.
Δy and SGNΔy in equation (4) are obtained by subtracting the output signals of . These subtraction circuits 53
The output signals of 3a and 533b are sent to the memories 534a and 534a, respectively.
534b is manually operated. The operations of the memories 534a to 534c are the same as the operations of the memory 521 of the selection circuit 52. The block unit output signals of the memories 534a and 534b are converted into absolute values by absolute value circuits 535a and 535b, and then 80 pixels are accumulated for each block in accumulation circuits 536a and 536b. The memory 534d operates in the same manner as the memories 522a to 522f of the selection circuit 52, that is, the read address is shifted by a motion vector (in this case, the initial shift vector). The output signals of the memory 534c and the memory 534d are manually subtracted by a subtraction circuit 533c, and the output is converted to SGNΔ× by sign calculation circuits 537a and 537b.
- DFD, SGNΔy-DFD calculations are performed. Sign calculation circuit 5. ] The outputs of 7a and 537b are the accumulation circuit 536.
c, 536d, where 80 pixels are accumulated for each block. These accumulation circuits 536c, 536
The output signal of d is expressed as ΣSGNΔ in the equation (]) and (2) above.
×・DFD, ΣSGNΔy・DFD, and the accumulation circuit 5
The output signals of 36a and 536b are respectively Σ1Δx1. Σ
1Δy1. These accumulation circuits 536a, 536b
The corresponding fractional circuits 538a, 538 for the output signals of
After calculating 1/Σ1Δx1 and 1/Σ1Δy1 using b, multiplier circuits 539a and 539b multiply the output signals of the fractional circuit 538a and the accumulation circuit 536C, and the output signals of the fractional circuit 538b and the accumulation circuit 536d, respectively. The deviation vectors vX+11 and ■y+11 are calculated and output.

In this way, the adder 54 adds the initial deviation vector to the deviation vector calculated by the calculation circuit 53, and uses this as the initial deviation vector in the calculation circuit 55 for the next gradient method, where the deviation vector VX(21, l/y+21 is calculated by a calculation circuit 55 similar to the calculation circuit 53.The calculation circuit 55 of the gradient method has the same basic operation as the calculation circuit 53, and the first
The initial deviation vector is stored in the memory 534d of Figure O instead of V.
O, l = (V, +01 +V, + I l
, vyI(1) +vノ1ゝ) manually. The rest is the same as the arithmetic circuit 53. The deviation vector vX(21, ■, (21 and the initial deviation pect 7L/BO=(VX ''' +y, +01) obtained by this arithmetic circuit 55
) and the displacement vectors y+), y, il+ are added in an adder 56 to form motion vectors V, , VY. That is, the motion vectors Vx and VY are: ■8=■X(0)+VX(1)+VX(2)...
(5) V, = V, ('l+V, +1++V, (2) ・
...(6). The motion vectors Vx and VY thus obtained are stored in the memory 51 and simultaneously output to the next motion vector averaging circuit 14.

Note that a smoothing circuit that performs smoothing may be inserted between the output of the switching circuit 12e and the calculation circuits 52 and 54 in order to reduce calculation errors in the gradient method due to noise. This smoothing circuit applies the reference pixel a. The following calculation is performed on pixels a1 to a4 adjacent to , and a smoothing output Ao is output. Pixel aO+
aI"' The positional relationship of a4 is shown in FIG. 9(b).

Furthermore, instead of this smoothing circuit, a two-dimensional low-pass filter with a large number of taps may be used.

The motion vector averaging circuit 14 averages the motion vectors from the motion detection circuit 13 in order to eliminate motion vector errors. As an example of averaging, several blocks in the horizontal direction and several blocks in the vertical direction around the current block are used as motion vectors, and the averaged vector is output to the motion vector determination circuit 15 as a motion vector.

The motion vector determination circuit 15 determines the motion vector obtained from the motion vector detection circuit 13 via the motion vector averaging circuit 14. An example of this determination is to calculate the absolute value of the difference in signals between fields whose position has been corrected by the detected motion vector, and to accumulate this value (referred to as γ1) over 32 pixels of 8 pixels x 4 lines. Calculate the absolute value of the inter-field difference without motion correction, compare it with the value accumulated for 32 pixels (referred to as γ2) in the same way as above,
If γ1>γ2, the motion vector is invalid and °“0
In addition, in the case of γ1 and γ2, the motion vector is considered valid and the motion vector is output.

FIG. 11 is a block diagram showing an example of the internal configuration of the motion vector determination circuit 15. Motion vector determination circuit 15 in the same figure
3 memories 151aN151C12 subtraction circuits 152a, 152b, correction circuit 153, absolute value circuit 1
54. It is composed of two accumulation circuits 155a, 155b, a comparison circuit 156, and a selection circuit 157. Switching circuit 1
Among the output signals of 2e, the current field signal is input to the memory 151a and the subtraction circuit 152b, and the previous field signal is input to the memory 151b and the subtraction circuit 152b. The operation of the memories 151a and 151b is shown in FIG.
The operation is similar to 22a to 522f. However, here, the other human power is not a motion vector itself, but a motion vector of a value multiplied by a field interpolation ratio in a motion vector correction circuit 153, as shown in FIG. FIG. 12 shows how this motion vector correction is performed. In the figure, β, 1-β is a field interpolation ratio, 121 is a block to be blocked (reference block) on the interpolation field, and 122 is a movement “0°” on the previous field.

, 123 is a motion "'0" block on the current field, 124 is a motion correction block on the previous field, 125 is a motion correction block on the current field, 126
is the detected motion vector (B), and 127 is the field interpolation correction motion vector of the current field (B" = - (1
-β)B), 128 is the field interpolation correction motion vector (B-=βB) of the previous field. Subtraction circuit 152
In b, the field difference is calculated between the pixels of the current field and the previous field, and the output thereof is input to the memory 151C. The operation of this memory is similar to that of the memory 521 in FIG. For the output signals of the memories 151a and 151b, a subtraction circuit 152a calculates the difference between the motion-compensated current field signal and the motion-compensated previous field signal, and the output is converted into an absolute value by an absolute value circuit 154. Thereafter, the signal converted into an absolute value is subjected to accumulation of 32 pixels in an accumulation circuit 155, and then input to a comparison circuit 156. Further, the output signal of the memory 151c is subjected to accumulation of 32 pixels in an accumulation circuit 155b, and the result is input to a comparison circuit +56. The comparison circuit 156 compares the sum of the absolute values of inter-field differences subjected to motion compensation and the sum of the absolute values of inter-field differences without motion correction. If the inter-field differences without motion are smaller, The motion vector output from the motion vector selection circuit 157 is set to "0°". On the other hand, if the motion-compensated inter-field difference is smaller, the selection circuit 157 outputs the motion vector.

Since the motion vector determined in this manner is in block units, it is necessary to make it correspond to a scanning line.

The memory 16 has this conversion function and performs an operation opposite to that of the memory 521 in the selection circuit 52 of FIG.

That is, a signal for each block from the motion vector determination circuit 15 is converted into a signal for each scanning line by controlling the memory address, and FIG. 13 shows this in a diagram.

Since the detected motion vectors are output for each block, they are output as B, , B2 . B, then the temporal length of B1 is 8 pixels x 4 lines (32 pixels) or more (motion vector detection is 8 pixels x 8 lines, but the motion vector judgment block is 8 pixels x 4 lines, so the field The motion vector during interpolation is 8 pixels x 4 lines)
. The memory 16 converts the array, and as shown in FIG. 13, blocks B1 (8 pixels), block B
2 (8 pixels).

FIG. 14 is a block diagram showing an example of the internal configuration of field interpolation circuits 17a and 17b. The field interpolation circuits 17a and 17b in the same figure have a capacity of μ (n or more) lines.
It is composed of two memories 171a and 171b, a correction circuit 172 that corrects motion vectors, and an arithmetic circuit 173 that performs field interpolation calculations. Memory 171a, 1
71b has a function of delaying the output signal of the line interpolation circuit by the time required to detect the motion vector, and a correction circuit 17.
There is a function of moving the position of the read signal by controlling the read address according to the motion vector corrected by multiplying the motion vector by the field interpolation ratio in step 2. The motion vector correction circuit 172 multiplies the manually input motion vector by a field interpolation ratio, and the relationship between the corrected motion vectors is not shown in FIG. 12 and is B+.

Same as B-. However, in Figure 14, memory 1
The human power signals 71a and 171b are the switching circuit 12a in FIG.
, 12b or 12c, 12d, and the switching -
It is not the output signal of circuit 12e. Therefore, the memory 171a
, 171b, there is no distinction between the current field and the previous field.
The sign of the motion vector corrected by the manual field interpolation ratio of 1b is also controlled depending on which signal is earlier in time.

That is, in the figure, the field interpolation ratios β and 1-β are switched by the same switching signal inputted to the switching circuit 12e, and the memory 171a storing the current field signal is switched.
(or 17.1b) to control the readout address, and send the motion vector corrected by β to the memory 171b (or 171a) storing the previous field signal.
- Send the motion vector corrected by β for read address control. The arithmetic circuit 173 is composed of two multipliers and an adder that adds the outputs of these multipliers.
This correction is performed using linear interpolation, which is used in system conversion devices. Therefore, the switching circuits 12a, 1 on the Y signal side
2b to the corresponding memory 1 of the field interpolation circuit 17a.
Y signals are stored in 71a and 171b, and these signals are read out by changing the readout address by the corrected motion vector from the correction circuit 172, so that the position is corrected, and then field interpolation is performed in the arithmetic circuit 173. is performed and output. Similarly, on the C signal side, the switching circuit 12c,
12d to field interpolation circuit] After the C signals are stored in the corresponding memories 171a and 171b of 7b, position correction is performed when reading these signals, and then field interpolation is performed in the arithmetic circuit 173 and output. Ru.

The input component signal Y is obtained as described above.

This means that RY and B-Y have been converted into output component signals Y and C.

Note that when a digital encoder is used, the signal after field interpolation is input to the digital encoder circuit as a digital signal, but when an analog encoder is used, it is converted back to an analog signal by a D/A conversion circuit and then input to the encoder. Manpower.

Encoder is NTSG, P8, SEC8M to P to LM
etc., and the encoder is selected according to the output side method.

FIG. 15 is a block diagram of a TV format conversion device showing a second embodiment. The difference from the first embodiment is that, as shown in the figure, the memory for converting the number of scanning lines is a memory 18 with a capacity of 3 fields, and the signals of each field read out in parallel from this memory 18 are Switcher 1 to sort in order of earliest
9 is provided, and a motion detection circuit 4 is provided to perform motion detection from the signal of this switch 19 that is one frame apart.

Therefore, the delay circuits 5a and 5b on the input side shown in FIG. 1 become unnecessary.

In the embodiment described above, the interpolation processing of the Y signal and the C signal constitutes the same processing method, but even if the processing of the C signal is slightly simplified compared to the Y signal, the difference in image quality is small. ,
Considering miniaturization and cost reduction of the device, it is desirable to simplify the processing of the C signal system.

Examples of this method include (1) a line interpolation processing method in which the Y signal is line interpolated within the field using a digital filter, and the C signal is linear interpolation between two adjacent lines between fields; ) A motion-adaptive line interpolation method may be used only for the Y signal system, and only linear interpolation between two adjacent lines within the field may be used for the C signal system.

Furthermore, the motion vector averaging circuit 14 may be deleted.

Furthermore, in this embodiment, a field interpolation circuit 17a.

A correction circuit 172 was provided inside the memory 17b, but it is provided as a common correction circuit for the output of the memory 16, and the motion vector corrected by the field interpolation ratio is transmitted from this correction circuit into the fields of the Y signal side and the C signal side. It may also be sent to the memory of the plug-in circuit.

(Effects of the Invention) As described above in detail, according to the present invention, a motion vector is detected on the luminance signal side, and position correction is performed for a moving image of a luminance signal and a color difference signal according to the detected motion vector. Since the configuration is configured such that field interpolation is performed after performing this, it is possible to smoothly correct images that move in parallel or images that have a wide moving image area.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a block diagram of a TV format conversion device showing a first embodiment of the present invention, Fig. 2 is an enlarged view of a diagonal line pattern, and Fig. 3 is a diagram of line interpolation within a field. 4 is an explanatory diagram of line interpolation between fields, FIG. 5 is a diagram of the main part of a motion vector detection circuit, and FIGS. 6(a) and (b) are explanatory diagrams of blocks and candidate vectors. FIG. 7 is an internal configuration diagram of the selection circuit, FIG. 8 is an explanatory diagram of memory operation, and FIGS. 9(a), (
b) is a diagram of the positional relationship between the reference pixel and adjacent pixels, FIG. 1O is an internal configuration diagram of the calculation circuit, FIG. 11 is an internal configuration diagram of the motion vector determination circuit, FIG. Figure 13 is an explanatory diagram of the operation of the memory for line conversion, the first
FIG. 4 is an internal configuration diagram of a field interpolation circuit, and FIG. 15 is a configuration diagram of a TV system conversion device showing a second embodiment of the present invention.
FIG. 16 is a block diagram of a conventional TV format converter, and FIG. 17 is a block diagram of a conventional TV format converter having a motion detection circuit. la, lb, lc - input terminal, 2a, 2b - output terminal, 3.5a, 5b - delay circuit, 4 - motion detection circuit, 6 - multiplex circuit, 7.8a, 8b, 16.18,5], 151a-15
1cJ71a, 171b, 521°522a ~522
f, 534a to 534d - memory, 9... OR circuit, 10a N10d, lla, Ilb - line interpolation circuit, 12a to 12e, 527a to 527d - switching circuit, 13... motion vector detection circuit, 14 ...Motion vector averaging circuit, 15...Motion vector determination circuit, 17a, 17b...Field interpolation circuit, 19...
Switching device, 52,157...Selection circuit, 53.55,1
73-- Arithmetic circuit, 54.56... Adder, 152
a, 152b, 523a ~ 523f, 533a ~ 5
33cm subtractor, 154.524a ~ 524f, 53
5a, 53'5b==Absolute value circuit, 155a, 155b
, 525a to 525f, 536a to 536d - accumulation circuit, 156.526a to 526e... comparison circuit,
537a, 537b - sign calculation circuit, 538a, 53
8b - fractional circuit, 539a, 539b - multiplication circuit, 15
3.172--Correction circuit.

Claims (1)

[Claims] A first memory having a capacity of two or more fields and storing a digitized luminance signal, and a first memory having a capacity of two or more fields and storing a digitized and multiplied color difference signal. a first detection means for detecting the presence or absence of movement from the inter-frame difference of each pixel from one of the input signal and output signal of the first memory; a first line interpolation unit that performs line interpolation using line information within the field; and a first line interpolation unit that performs line interpolation using line information between two fields interlaced with respect to the output signal of the first memory. a second line interpolation means; a third line interpolation means for performing line interpolation on the output signal of the second memory using line information in the same field; fourth line interpolation means that performs line interpolation using line information between two interlaced fields; and first and second line interpolation means based on the detection result of the first detection means. and a second selection means for selecting one of the output signals of the third and fourth line interpolation means based on the detection result. In the television standard format conversion device, the output signal of the first selection means separated by one field is divided into blocks of m pixels x n lines (m, n: integer), and a motion vector is detected for each block. a second detection means; validity of the motion vector detected by the second detection means;
determining means for determining invalidity and outputting the motion vector when determining validity; converting means for converting the output signal of the determining means into a motion vector corresponding to a scanning line; A third line with a capacity of two l (more than n) lines to store corresponding to the field.
and a fifth memory having a capacity of two l (n or more) lines for storing the output signal of the second selection means corresponding to each field.
and a sixth memory; changing the read address by the value of the product of the motion vector from the conversion means and the field interpolation ratio;
a first field interpolation means for performing field interpolation on the output signals of the third and fourth memories; and a first field interpolation means for performing field interpolation on the output signals of the fifth and sixth memories; 1. A television standard format conversion device comprising: second field interpolation means for performing interpolation.