JP4092778B2 - Image signal system converter and television receiver - Google Patents

Description

【００５２】
（式１）で、Ｓ２（ｘ，ｙ）は算出領域内の現フレームの画素の信号、Ｓ３（ＶＮ）は動きベクトルＶＮで位置を移動させた前フレームの画素の信号、ａｂｓ｛ ｝は絶対値、Σは算出領域内の画素の総和、ＶＮｘは動きベクトルＶＮのｘ成分、ＶＮｙはｙ成分である。
【００５３】
画素動きベクトル設定部１８は、図１９の第２ステップの閾値未満および第３ステップの信号処理を行う。則ち、制御信号ＰＣ２が閾値未満を示す場合は、現ブロックの動きベクトルＶ０を画素単位動きベクトルＰＶに出力する。一方、閾値以上を示す場合は、動き補正誤差ＥＲ０、ＥＲ１、…、ＥＲＮの内で最少値をとる動きベクトルを、各ミニブロック内の画素の動きベクトルＰＶとして出力する。
【００５４】
また、動き検出信号ＭＩ２が０の画素を示す時は、制御信号ＰＣ２が画素単位動きベクトルＰＶに強制的に０を出力させる。
【００５５】
図５は、画素単位動きベクトル生成部の第２の構成例を示す図である。そして、図２１（ａ）、図２１（ｂ）に示す信号処理で画素単位の動きベクトルを生成する。
【００５６】
補正誤差算出部１４は、図４に示したものと同じで、図２１（ａ）に示す第１ステップの処理を行い、ブロック単位の動き補正誤差の値が閾値ＴＨ未満の場合は信号ＰＭに０、閾値ＴＨ以上の場合は１を出力する。
【００５７】
制御部１５は、信号ＰＭと動き検出信号ＭＩ２を基に、図２１（ａ）に示す第２、第３ステップの信号処理に必要な制御信号ＰＣ３、ＰＣ２を生成する。
【００５８】
再探索第１処理部１９、再探索第２処理部２０、再探索第３処理部２１は、図２１（ａ）の第２ステップの信号処理を行う。則ち、制御信号ＰＣ３が閾値以上を示す時には、動きベクトルの再探索処理を行う。まず、再探索第１処理部１９では、図２１（ｂ）に示すように、ブロックサイズが水平、垂直とも１／２のサイズに縮小したサブブロックＳＢ１毎に、動きベクトルＢＶを参照ベクトルとしてブロックマッチング処理を行い、再探索したＳＢ１単位の動きベクトルＰＶ１を出力する。次に、再探索第２処理部２０では、サブブロックＳＢ１を水平、垂直ともに１／２に縮小したサブブロックＳＢ２毎に、動きベクトルＰＶ１を参照ベクトルとしてブロックマッチング処理を行い、再探索したＳＢ２単位の動きベクトルＰＶ２を出力する。再探索第３処理部２１は、サブブロックＳＢ２を水平、垂直ともに１／ｎに縮小したミニブロックサイズのサブブロックＳＢＮ毎に、動きベクトルＰＶ２を参照ベクトルとしてブロックマッチング処理を行い、再探索したＳＢＮ単位の動きベクトル、則ち、ミニブロック単位の動きベクトルＰＶ３を出力する。一方、制御信号ＰＣ３が閾値未満を示す時は、再探索第１処理部１９、再探索第２処理部２０、再探索第３処理部２１は、再探索処理の動作を中止し、動きベクトルＰＶ３に現ブロックの動きベクトルＢＶを出力する。
【００５９】
画素動きベクトル設定部２２は、図２１（ａ）の第３ステップの信号処理を行う。則ち、動き検出信号ＭＩ２が０の画素を示す時は、制御信号ＰＣ２が画素単位動きベクトルＰＶに強制的に０を出力させる。一方、動き検出信号ＭＩ２が１の画素を示す時は、制御信号ＰＣ２が画素単位動きベクトルＰＶにＰＶ３を出力させる。
【００６０】
図６は、画素単位動きベクトル生成部の第３の構成例を示す図である。これは、前述した図２２に従った信号処理を行うに好適なもので、図４の構成に再探索処理部２３を追加することで実現する。
【００６１】
再探索処理部２３は、制御信号ＰＣ４が閾値以上を示す場合は、ブロックサイズを水平、垂直ともに１／２に縮小したサブブロックＳＢ１毎に、現ブロックの動きベクトルＢＶを参照ベクトルとしたブロックマッチング処理を行い、再探索したＳＢ１単位の動きベクトルＰＶ１を出力する。一方、ＰＣ４が閾値未満を示す場合は、再探索動作を中止して、現ブロックの動きベクトルＢＶを出力する。そして、図２２の第２ステップの閾値以上の信号処理で参照ベクトルとして使用するサブブロックＳＢ１単位の動きベクトルＰＶ１を生成する。
【００６２】
以降の動作は、図４に示したものと同様であるので、説明は省略する。
【００６３】
図７は、画素単位動きベクトル生成部の第４の構成例を示す図で、図２３（ａ）、図２３（ｂ）に示す信号処理で画素単位の動きベクトルを生成する。
【００６４】
補正誤差算出部１４は、図４に示したものと同じで、図２３（ａ）に示す第１ステップの処理を行い、ブロック単位の動き補正誤差の値が閾値ＴＨ未満の場合は信号ＰＭに０、閾値ＴＨ以上の場合は１を出力する。
【００６５】
制御部１５は、信号ＰＭと動き検出信号ＭＩ２を基に、図２３（ａ）に示す第２、第３ステップの信号処理に必要な制御信号ＰＣ５、ＰＣ２を生成する。
【００６６】
再探索第１処理部２４、再探索第２処理部２５、再探索第３処理部２６は、図２３（ａ）の第２ステップの信号処理を行う。則ち、制御信号ＰＣ５が閾値以上を示す時には、動きベクトルの再探索処理を行う。まず、再探索第１処理部２４は、図２３（ｂ）に示すように、ブロックサイズを水平、垂直とも１／２のサイズに縮小したサブブロックＳＢ１毎に、動きベクトルＢＶを参照ベクトルとしてブロックマッチング処理を行い、再探索したＳＢ１単位の動きベクトルＰＶ１を出力する。次に、再探索第２処理部２５は、ブロックサイズを水平、垂直ともに１／４に縮小したサブブロックＳＢ２毎に、動きベクトルＢＶを参照ベクトルとしてブロックマッチング処理を行い、再探索したＳＢ２単位の動きベクトルＰＶ２を出力する。再探索第３処理部２６は、ブロックサイズを水平、垂直ともに１／ｎに縮小したミニブロックサイズのサブブロックＳＢＮ毎に、動きベクトルＢＶを参照ベクトルとしてブロックマッチング処理を行い、再探索したＳＢＮ単位の動きベクトル、則ち、ミニブロック単位の動きベクトルＰＶ３を出力する。一方、制御信号ＰＣ５が閾値未満を示す時は、再探索第１処理部２４、再探索第２処理部２５、再探索第３処理部２６は、再探索処理の動作を中止し、ＰＶ１、ＰＶ２、ＰＶ３に現ブロックの動きベクトルＢＶを出力する。
【００６７】
画素動きベクトル設定部２７は、図２３（ａ）の第２ステップの閾値未満および第３ステップの信号処理を行う。則ち、制御信号ＰＣ２が閾値未満を示す場合は、現ブロックの動きベクトルＰＶ１を画素単位動きベクトルＰＶに出力する。一方、閾値以上を示す場合は、ＰＶ１、ＰＶ２、ＰＶ３の内で動き補正誤差が最少値をとる動きベクトルを各ミニブロック内の画素の動きベクトルとして出力する。
【００６８】
また、動き検出信号ＭＩ２が０の画素を示す時は、制御信号ＰＣ２が画素単位動きベクトルＰＶに強制的に０を出力させる。
【００６９】
図８は、動き補正内挿フレーム生成部７の第１の構成例を示す図、図９（ａ）〜図９（ｃ）はその動作を説明するための図である。
【００７０】
フレーム順制御部２８は、画素単位動きベクトルＰＶより動き補正処理に必要な補正補間動きベクトルＶｃｔとＶｐｒを生成する。この動作概略を、フレーム周波数５０Ｈｚの信号をフレーム周波数が６０Ｈｚの信号にフレーム数変換を行う場合を例に、図９（ａ）、図９（ｂ）に示す。フレーム周波数５０Ｈｚの順次走査の信号は、フレーム順の１から５の信号に対し、同図に示す様に動きベクトルＰＶを基に補正型の信号処理で内挿フレームを生成し、フレーム順１から６のフレーム周波数が６０Ｈｚの順次走査の信号に変換する。この際、補正補間動きベクトルは、内挿するフレーム位置と合致させる必要がある。そこで、同図に示す様に、動きベクトル信号ＰＶに係数加重する係数値ｋａ，ｋｂを変化させ、（式２）に示す演算で補正補間動きベクトルＶｐｒ、Ｖｃｔを生成する。
【００７１】
【数２】

【００７２】
則ち、フレーム順が２の内挿フレームは、Ｖｐｒ＝ＰＶ＊５／６，Ｖｃｔ＝−ＰＶ＊１／６（ｋａ＝５，ｋｂ＝１）、３のものは、Ｖｐｒ＝ＰＶ＊４／６，Ｖｃｔ＝−ＰＶ＊２／６（ｋａ＝４，ｋｂ＝２）…の如く、係数値ｋａ，ｋｂを発生させ、時間方向での位置ずれのない補正補間動きベクトルを生成する。この結果、時間方向での揺らぎのないフレーム数変換を実現する。
【００７３】
動き補正信号生成部２９では、現フレームの信号Ｓ２と補正補間動きベクトルＶｃｔで動き補正信号Ｓｃｔを生成する。また、動き補正信号生成部３０は、前フレームの信号Ｓ３と補正補間動きベクトルＶｐｒで動き補正信号Ｓｐｒを生成する。この動作概略を図９（ｃ）に示す。内挿フレームの点Ａ（ｘ，ｙ）の信号は、前フレームの信号Ｓ３では、点Ａ（ｘ，ｙ）を補正補間動きベクトルＶｐｒ（水平方向成分Ｖｐｒｘ，垂直方向成分Ｖｐｒｙ）で移動させた点Ａ’（ｘ１，ｙ１）＝（ｘ＋Ｖｐｒｘ，ｙ＋Ｖｐｒｙ）の位置の信号、現フレームの信号Ｓ２では点Ａ（ｘ，ｙ）を補正補間動きベクトルＶｃｔ（水平方向成分Ｖｃｔｘ，垂直方向成分Ｖｃｔｙ）で移動させた点Ａ”（ｘ２，ｙ２）＝（ｘ−Ｖｃｔｘ，ｙ−Ｖｃｔｙ）の位置の信号に対応する。従って、動き補正信号ＳｐｒとＳｃｔは、以下の（式３）で生成される。
【００７４】
【数３】

【００７５】
この信号処理は、動き補正信号生成部に内蔵のメモリ回路の読み出し動作を制御することで実現できる。則ち、読み出しのためのアドレスを補正補間動きベクトルＶｐｒ，Ｖｃｔの位置だけずらせたアドレスを生成し、このアドレスで点Ａ’，Ａ”に対応した画素の信号を読み出す。
【００７６】
加算部３１は、両者の動き補正信号ＳｐｒとＳｃｔとの加算平均を行い、その出力に動き補正のフレーム数変換でフレーム周波数をアップした順次走査の画像信号Ｓ４を得る。
【００７７】
図１０は、動き補正内挿フレーム生成部の第２の構成例を示す図である。これは、モーションジャダー妨害が目立ちやすい速度の動き、あるいは水平パンや上下パンや文字スクロールなどの特殊な動きの場合のみ、動き補正のフレーム内挿処理を行うものである。
【００７８】
同図のフレーム順制御部２８、動き補正信号生成部２９，３０、加算部３１は、図８と同じ動作を行い、加算部３１の出力に動き補正のフレーム内挿処理した信号Ｓｍｃを得る。
【００７９】
動き速度検出部３２は、画素単位動きベクトルＰＶを基に、モーションジャダー妨害が目立ちやすい速度の動き、あるいは水平パンや上下パンや文字スクロールなどの特殊な動きを検出する。
【００８０】
例えば、モーションジャダー妨害は、１秒／画面幅、１秒／画面高程度までの視線が追従できる動きの場合に特に目立ち易いという性質が知られている。従って、動き速度検出部では、１秒／画面幅、１秒／画面高程度に相当する速度を閾値とする動きベクトルＰＶの速度成分の判定を行い、閾値未満の速度では１、以上では０の信号ＳＬを出力する第１の動作で、この検出ができる。
【００８１】
また、水平パンや上下パンでは画面全体が一様な速度で動く。従って、動き速度検出部では、画素単位動きベクトルＰＶ≠０のものの大きさと方向を全画面領域にわたり計測し、これがほぼ同じ値をとる場合のみ、全ての画面領域で１を信号ＳＬに出力する第２の動作で、この検出ができる。
【００８２】
一方、文字スクロールなどでは、動き領域の形状が帯状で、かつ、この領域での動きベクトルはほぼ同じ値になる。従って、動き速度検出部では、画素単位動きベクトルＰＶ≠０のものの大きさと方向がほぼ同一となる帯状の領域を検出し、この領域のみ１を信号ＳＬに出力する第３の動作で、この検出ができる。
【００８３】
なお、動き速度検出部は、第１、第２、第３のいずれか１つの動作、もしくはこれらを組み合わせた動作など、種々の動作形態のもので実現できる。
【００８４】
スイッチ部３３は、信号ＳＬが１の時は、現フレームの信号Ｓ２を選択し、信号ＳＬが０の時は、信号Ｓｍｃを選択する。そして、この出力に、モーションジャダー妨害が目立ちやすい速度の動き、あるいは水平パンや上下パンや文字スクロールなどの特殊な動きの領域のみを動き補正のフレーム内挿処理した順次走査の画像信号Ｓ４を得る。
【００８５】
以上に述べた如く、本実施例によれば、動きベクトルの探索、生成に要する演算量が少なく、かつ、高画質な画像信号の方式変換装置が実現できる。そして、低コスト化に顕著な効果が得られる。
【００８６】
次に、本発明の第２の実施例について、図１１のブロック構成図を用いて説明する。本実施例は、シーンチェンジの領域では動き補正処理の信号処理を中止する動作を行うに好適なものである。
【００８７】
同図のＩＰ変換部１、１フレーム遅延部３、動き検出部４、ブロック単位動きベクトル探索部５、画素単位動きベクトル生成部６は、図１に示したものと同一のものである。
【００８８】
シーンチェンジ検出部３４は、１フレーム期間でのフレーム間差分信号成分の発生形態を基にシーンチェンジの発生した領域を検出する動作を行う。この一構成例を図１２に示す。減算部８は、現フレームの信号Ｓ２と、前フレームの信号Ｓ３の輝度信号成分に対して減算演算を行い、１フレーム間の差分成分ＦＤを抽出する。一般に、シーンチェンジの領域では、画像の内容が切り替わるため、差分成分ＦＤの信号レベルは比較的大きな値を持つ。そこで、２値量子化部３６は比較的高いレベルの閾値±Ｔｈｂで信号ＦＤを画素毎に２値量子化する。そして、閾値±Ｔｈｂ未満の画素は０、閾値を越える画素は１を信号ＱＳに出力する。１フレーム累積部３７は、１フレーム期間で信号ＱＳが１のものの画素の数を計測し、１フレーム期間での累積値ＡＱを出力する。判定部３８は、画面全体が一様な速度で動く水平パンや上下パンの動きを誤ってシーンチェンジと検出する誤動作を避けるため、累積値ＡＱの値が全画面の半分以上の画素数で、かつ、その発生が１フレーム期間に限られる場合をシーンチェンジ領域と判定し、信号ＳＣに１フレームの期間にわたり１を出力する。これ以外の場合は０を出力する。
【００８９】
ブロック単位動きベクトル探索部５、画素単位動きベクトル生成部６は、信号ＳＣが１の期間のみ、優先的に、動きベクトルの探索や生成の動作を中止する。そして、信号ＳＣが０の場合は、図１と同じ動作を行う。
【００９０】
また、動き補正内挿フレーム生成部３５は、信号ＳＣが１の期間は、優先的に、現フレームの信号Ｓ２を選択してＳ４に出力する。また、信号ＳＣが０の場合は、図１の動き補正内挿フレーム生成部７と同じ動作を行う。
【００９１】
以上に述べた如く、本実施例によれば、シーンチェンジ領域における動きベクトル探索や生成のための膨大な演算量の発生を回避することができる。そして、より演算量が少なく、かつ、高画質な画像信号の方式変換装置を実現し、低コスト化に顕著な効果が得られる。
【００９２】
次に、本発明の第３の実施例について、図１３に示すブロック構成図で説明する。本実施例は、動き補正のフレームレート変換の処理と画像信号の走査線数の縮小変換とを併せて行うに好適なものである。
【００９３】
飛び越し走査の入力画像信号Ｓ１（輝度信号成分と色差信号成分）は、ＩＰ変換部１に入力し、飛び越し−順次の走査変換を行う。例えば、輝度信号成分は動き適応型の補間処理、色差信号はライン間の補間処理で補間走査線の信号を生成し、出力に順次走査の信号系列Ｓ２（輝度信号成分と色差信号成分）を得る。なお、入力画像信号がテレシネ画像信号（映画などのフィルム画像を２−３プルダウン処理でテレビ信号のフォーマットに変換した信号）の場合は、フィルムモードの補間処理（同一フィルムフレームに属す飛び越し走査の信号で補間走査線の信号を生成）で、フィルム画像の形態の順次走査の信号系列を生成する。
【００９４】
スケーリング処理部３９は、直線補間特性の垂直Ｍ−Ｎ変換処理（Ｍ＞Ｎ）による垂直圧縮の信号処理で、走査線数のＮ／Ｍ倍の縮小変換処理を行う。例えば、ＰＡＬ方式の走査線数６２５本の信号をＮＴＳＣ方式の走査線数５２５本の信号に変換する。そして、走査線数を縮小した順次走査の画像信号Ｓ１０を出力する。なお、この構成は、従来技術で容易に実現することができるため、具体的な構成例などの説明は省略する。
【００９５】
動き補正フレーム数変換部２は、構成、動作が図１に示したものと全く同一である。そして、現フレームの信号Ｓ１０と、１フレーム遅延部３で１フレーム期間遅延させた前フレームの信号Ｓ１１とを使用して、動き補正のフレーム内挿の信号処理を行い、出力にフレームレート変換と走査線縮小変換を行った順次走査の画像信号Ｓ４を得る。
【００９６】
以上に述べた如く、本実施例によれば、動き補正のフレームレート変換の処理と画像信号の走査線数の縮小変換とを併せて行う画像信号の方式変換装置、例えば、ＰＡＬ方式のテレビジョン信号をＮＴＳＣ方式の順次走査の画像信号に変換する装置を、極めて低コストで実現できる。
【００９７】
次に、本発明の第４の実施例について、図１４に示すブロック構成図で説明する。本実施例も、動き補正のフレームレート変換の処理と画像信号の走査線数の縮小変換とを併せて行うに好適なものである。本実施例では、図１３に示す実施例と同様、ＩＰ変換部１では、飛び越し−順次の走査変換を行い、スケーリング処理部３９では、垂直圧縮の信号処理で走査線数のＮ／Ｍ倍の縮小変換処理を行う。
【００９８】
動き補正フレーム数変換部２は、構成、動作が図１１に示したものと全く同一である。そして、現フレームの信号Ｓ１０と、１フレーム遅延部３で１フレーム期間遅延させた前フレームの信号Ｓ１１とを使用して、動き補正のフレーム内挿の信号処理を行い、出力にフレームレート変換と走査線縮小変換を行った順次走査の画像信号Ｓ４を得る。
【００９９】
以上に述べた如く、本実施例によれば、動き補正のフレームレート変換の処理と画像信号の走査線数の縮小変換とを併せて行う画像信号の方式変換装置、例えば、ＰＡＬ方式のテレビジョン信号をＮＴＳＣ方式の順次走査の画像信号に変換する装置を、極めて低コストで実現できる。
【０１００】
次に、本発明の第５の実施例について、図１５に示すブロック構成図で説明する。本実施例は、動き補正のフレームレート変換の処理と画像信号の走査線数の拡大変換とを併せて行うに好適なものである。同図において、ＩＰ変換部１と動き補正フレーム数変換部２は、構成および動作が図１に示したものと全く同一である。
【０１０１】
動き補正のフレーム数変換した順次走査の画像信号Ｓ４は、スケーリング処理部３９で、直線補間特性の垂直Ｍ−Ｎ変換処理（Ｍ＜Ｎ）による垂直拡大の信号処理で、走査線数のＮ／Ｍ倍の拡大変換処理を行う。例えば、ＮＴＳＣ方式の走査線数５２５本の信号をパソコンのＳＶＧＡに相当する走査線数７２０本の信号に変換する。そして、走査線数を拡大した順次走査の画像信号Ｓ５を出力する。なお、この構成は、従来技術で容易に実現することができるため、具体的な構成例などの説明は省略する。
【０１０２】
以上に述べた如く、本実施例によれば、動き補正のフレームレート変換の処理と画像信号の走査線数の拡大変換とを併せて行う画像信号の方式変換装置、例えば、ＮＴＳＣ方式のテレビジョン信号をパソコンのＳＶＧＡに相当する走査線数の順次走査の画像信号に変換する装置を、極めて低コストで実現できる。
【０１０３】
次に、本発明の第６の実施例について、図１６に示すブロック構成図で説明する。本実施例は、動き補正のフレームレート変換の処理と画像信号の走査線数の拡大変換とを併せて行うに好適なものである。
【０１０４】
同図において、ＩＰ変換部１と動き補正フレーム数変換部２は、構成、動作が図１１に示したものと全く同一である。
【０１０５】
動き補正のフレーム数変換した順次走査の画像信号Ｓ４は、スケーリング処理部３９で、直線補間特性の垂直Ｍ−Ｎ変換処理（Ｍ＜Ｎ）による垂直拡大の信号処理で、走査線数のＮ／Ｍ倍の拡大変換処理を行う。例えば、ＮＴＳＣ方式の走査線数５２５本の信号をパソコンのＳＶＧＡに相当する走査線数７２０本の信号に変換する。そして、走査線数を拡大した順次走査の画像信号Ｓ５を出力する。なお、この構成は、従来技術で容易に実現することができるため、具体的な構成例などの説明は省略する。
【０１０６】
以上に述べた本発明の技術的手段で、テレビジョン受像機に内蔵可能な、回路規模が小さく低コスト、かつ、高画質な動き補正のフレーム数変換を実現し、マルチソ−ス対応、マルチディスプレイ対応、マルチウィンドウ表示対応の機能を有するテレビジョン受像機が実現できる。
【０１０７】
図２４は、本発明の他の実施例によるテレビジョン受像機を示す全体ブロック構成図である。本実施例は、表示部が走査線数６２５本、フレーム周波数６０Ｈｚ、順次走査、あるいは、走査線数１０８０本（１１２５本）、フィールド周波数６０Ｈｚ、飛び越し走査の形態のＣＲＴ、ＰＤＰ、ＬＣＤに好適なものである。
【０１０８】
放送波ＴＶ１、ＴＶ２、…、ＴＶＮ（例えば、現行ＴＶ方式のＮＴＳＣ信号、ＰＡＬ信号）は、ＴＶ復調部５１−１、…、５１−Ｎで所定の復調処理を行い、輝度信号成分と色差信号成分に復調する。
【０１０９】
デジタル放送波ＴＶＤは、ＩＲＤ５２で所定のデジタル復調、復号化処理を行い、ＳＤ（現行ＴＶ方式と同じ画像フォーマットの信号）、又は、ＨＤ（ＨＤＴＶ相当の画像フォーマットの信号）の輝度信号成分と色差信号成分に復調する。
パソコンの画像信号（例えば、ＲＧＢ３原色信号）は、色変換部５３で色空間変換の信号処理を行い、輝度信号成分と色差信号成分に変換する。
【０１１０】
以上の入力系の信号は、信号バス５９を介して、画像フォーマット変換部６０−１、…、６０−Ｍに入力する。そして、ＩＰ変換部１は、飛び越し走査の信号を、例えば動き適応の走査線補間の信号処理で順次走査の信号に変換する。動き補正フレーム数変換部２は、フレーム周波数が６０Ｈｚ未満（例えばＰＡＬ方式の５０Ｈｚ、あるいはフィルム画像の２４Ｈｚ）の信号を、動き補正のフレーム内挿処理でフレーム周波数が６０Ｈｚの信号に変換する。また、スケーリング処理部３９は、走査線数の変換（表示部が走査線数６２５本であれば、ＮＴＳＣ方式の走査線数５２５本の信号を走査線数の５−６変換処理で６２５本の信号に変換）や、マルチウィンドウ、２画面動画、ＰＩＰ（Picture in picture）、ＰＯＰ（Picture out picture）などの各種表示形態に応じた画像サイズの拡大、縮小の処理を行う。
【０１１１】
画質改善部６１−１〜６１−Ｍは、輝度階調補正や、表示部の色空間特性に合致した色空間変換や逆ガンマ補正（表示部がＰＤＰやＬＣＤなどのリニア特性の場合）などの信号処理を行う。
【０１１２】
ＭＰＸ部６２は信号を多重化する多重化部で、各画質改善部からの出力信号を統合、合成して所定の表示形態の画像信号を生成する。そして、表示部５５に画像を再生する。
【０１１３】
視聴者が選択指定する表示形態の情報は、リモコン５６、リモコン制御信号受信部５７を介して、制御部５８に入力される。そして、制御部５８では、この情報に応じて、各部の動作に必要な制御信号類を生成し、被制御部５４に出力する。
【０１１４】
本ブロック構成図において、本発明の主眼である画像フォーマット変換部６０−１〜６０−Ｍは、ＩＰ変換部１、動き補正フレーム数変換部２、及びスケーリング処理部３９を具備しており、これらは前述の実施例のものを使用することができる。また、これらを除いた各ブロックは、従来の技術で容易に構成することが出来るので、ここでの説明は省略する。
【０１１５】
本実施例によれば、動き補正のフレームレート変換を行うに必要な動きベクトルの探索、生成に要する演算量を、従来の方法に較べて数十分の一程度に低減でき、回路規模も極めて小さく出来る。このため、この動き補正のフレームレート変換の機能を内蔵したテレビジョン受像機を比較的低コストで実現できる。そして、テレビ画像の高画質化、高機能化に顕著な効果が得られる。
【０１１６】
次に、本発明の他の実施例によるテレビジョン受像機について図２５に示す全体ブロック構成図で説明する。本実施例は、表示部が走査線数５２５本、フレーム周波数６０Ｈｚ、順次走査の形態のＣＲＴ、ＰＤＰ、ＬＣＤに好適なものである。なお、図２４に示した実施例との相違は、画像フォーマット変換部での信号処理におけるスケーリング処理と動き補正フレーム数変換の処理の順序を逆にした点にある。従って、以下ではこの動き補正フレーム数変換について説明する。
【０１１７】
画像フォーマット変換部６２−１、…、６２−Ｍでは、始めに、ＩＰ変換部１で飛び越し走査の信号を、順次走査の信号に変換する。則ち、飛び越し走査の画像信号（輝度信号成分と色差信号成分）の輝度信号成分は動き適応型の補間処理、色差信号成分はライン間の補間処理で補間走査線の信号を生成し、順次走査の信号系列（輝度信号成分と色差信号成分）に変換する。また、入力画像信号がテレシネ画像信号（映画などのフィルム画像を２２−３プルダウン処理でテレビジョン信号のフォーマットに変換した信号）の場合は、フィルムモードの補間処理（同一フィルムフレームに属す飛び越し走査の信号で補間走査線の信号を生成）で、フィルム画像の形態の順次走査の信号系列を生成する。
【０１１８】
次に、スケーリング処理部３９では、走査線数の縮小変換、及び画像サイズの拡大、縮小の処理を行う。例えば、走査線数６２５本のＰＡＬ方式の信号は、走査線数の６−５変換処理を行い、ＮＴＳＣ方式の走査線数５２５本の信号に変換する。また、マルチウィンドウ、２画面動画、ＰＩＰ（Picture in picture）、ＰＯＰ（Picture out picture）などの各種表示形態に応じた画像サイズの拡大、縮小の処理を行う。
【０１１９】
動き補正フレーム数変換部２は、フレーム周波数が６０Ｈｚ未満（例えばＰＡＬ方式の５０Ｈｚ、あるいはフィルム画像の２４Ｈｚ）の信号を、動き補正のフレーム内挿処理でフレーム周波数が６０Ｈｚの信号に変換する。この際、前段のスケーリング処理で、ＰＡＬ方式の走査線数６２５本の信号は、走査線数を５／６に縮小した走査線数５２５本の信号に変換されている。従って、動き補正のフレーム数変換に必要な動きベクトルの探索のための演算量は、走査線数６２５本の場合の５／６に軽減できる。なお、動き補正フレーム数変換部２の具体的な構成は前述の実施例と同様であり、説明は省略する。
【０１２０】
以上に述べた如く、本実施例によれば、動き補正のフレームレート変換を行うに必要な動きベクトルの探索、生成に要する演算量を、従来の方法に較べて数十分の一程度に低減でき、回路規模も極めて小さく出来る。このため、この動き補正のフレームレート変換の機能を内蔵したテレビジョン受像機を比較的低コストで実現できる。そして、テレビ画像の高画質化、高機能化に顕著な効果が得られる。
【０１２１】
次に、本発明の他の実施例によるテレビジョン受像機について、図２６に示す全体ブロック構成図で説明する。本実施例は、図２４の実施例に信号混合部であるＭＩＸ部６３−１〜６３−Ｋを追加し、より少ない個数の画像フォーマット変換部６０−１〜６０−Ｍ’で実現して、更なるコスト低減を図るに好適なものである。
【０１２２】
ＭＩＸ部６３−１、…、６３−Ｋは、ＴＶ復調部５１−１、…、５１−Ｎで復調した画像信号のうち、同一方式の２チャネルのＴＶ信号が入力される。そして、表示形態が同一方式のＴＶ信号による２画面動画あるいはＰＩＰの場合には、２チャネルのＴＶ信号の合成処理を行う。例えば２画面動画では、画面の左半分の位置に一方のチャネルの信号、画面の右半分の位置に他のチャネルの信号を配列させる動作の信号処理を行い、出力する。また、ＰＩＰでは、一方のチャネルの信号を主画面の位置、他方のチャネルの信号を子画面の位置に配列させる動作の信号処理を行い、出力する。一方、上記以外の表示形態では、表示に使用するいずれか一方のチャネルの信号を出力する。
【０１２３】
画像フォーマット変換部６０−１、…、６０−Ｍ’では、図２４と同様の処理を行う。ただ、同一方式のＴＶ信号による２画面動画あるいはＰＩＰの表示形態の場合は、既にＭＩＸ部６３−１〜６３−Ｋの出力で必要な信号形態への変換がなされているため、スケーリング処理部での拡大、縮小の信号処理は行わない。
以上に述べた如く、本実施例では２画面動画やＰＩＰの表示形態では、画像フォーマット変換部の前段に設けたＭＩＸ部で変換処理を行う。このため、使用する画像フォーマット変換部の個数を減らすことが可能になり、より低コストなテレビジョン受像機が実現できる。
【０１２４】
次に、本発明の他の実施例によるテレビジョン受像機について、図２７に示す全体ブロック構成図を用いて説明する。本実施例は、図２５の実施例にＭＩＸ部６３−１〜６３−Ｋを追加し、画像フォーマット変換部６２−１〜６２−Ｍ’の個数の削減を図り、更なるコスト低減を図るに好適なものである。なお、ＭＩＸ部６３−１〜６３−Ｋの動作は図２６に示したものと同一である。また、その他については構成、動作は図２５と同一であるので、説明は省略する。
【０１２５】
以上のとおり、これらの実施例によれば、テレビ画像の高画質化や高機能化に顕著な効果を得ることができるとともに、動き補正の信号処理での動きベクトルの探索や生成に要する演算量を従来方法に較べ大幅に低減し、かつ、回路規模も大幅に小さく出来る。このため、マルチソース対応、マルチディスプレイ対応、マルチウィンドウ表示対応の機能を備えた、高画質かつ、低コストのテレビジョン受像機を実現することができる。
【０１２６】
ここで、動き補正の信号処理における動きベクトルの探索や生成に要する演算量の削減率を求めてみる。
【０１２７】
まず、ブロック単位の動きベクトル探索処理の演算量削減率は次のようにして求めることができる。
【０１２８】
探索領域を水平方向±ＤＸ画素、垂直方向±ＤＹラインとした場合、全探索法では、ブロック当りのブロックマッチング処理は（２ＤＸ＋１）（２ＤＹ＋１）回が必要になる。一方、動画ブロック当りのブロックマッチング処理は、第２ステップで（ＤＸ／２＋１）（ＤＹ／２＋１）回、第３ステップで（ＤＸ／４＋１）（ＤＹ／４＋１）回となる。ここで、動画ブロックの発生確率をＭｂ（０≦Ｍｂ≦１）、ＤＸ＝１６、ＤＹ＝１６とし、ブロック探索の演算量削減率をＫｂとするば、Ｋｂは（式４）で与えられる。
【０１２９】
【数４】

【０１３０】
したがって、ブロック単位の探索では、１画面が全て動画ブロックの最悪の場合（Ｍｂ＝１）でも、全探索法に比べ１０％程度の演算量で探索を行うことができる。
【０１３１】
次に、画素単位の動きベクトル探索処理の演算量削減率は次のようにして求めることができる。
【０１３２】
一般には、現ブロックの動きベクトルＢＶを参照ベクトルとし、画素単位に、探索領域を縮小した水平±ＤＸ／４画素、垂直方向±ＤＹ／４ライン程度の範囲で再探索を行い、最終的な動きベクトルを生成する手法が採られる。ブロックサイズを水平ＢＸ画素、垂直ＢＹラインとすると、この場合に必要な再探索処理は（ＤＸ／２＋１）（ＤＹ／２＋１）・ＢＸ・ＢＹ回の探索処理が必要となる。一方、閾値ＴＨ以上のブロックに対し、（参照ベクトルの個数９）・（輝度１系統と色差２系統の３種類）・（ＢＸ／２）・（ＢＹ／２）回の再探索を行う。ここで、閾値ＴＨ以上のブロックの発生確率をＭｐ（０≦Ｍｐ≦１）、ＤＸ＝ＤＹ＝１６、ＢＸ＝ＢＹ＝１６とし、画素探索の演算量削減率をＫｐとするば、Ｋｐは（式５）で与えられる。
【０１３３】
【数５】

【０１３４】
したがって、１画面の全てが動画ブロックとなる最悪ケース（Ｍｐ＝１）でも、全画素探索法に比べ８％程度の演算量で探索を行うことができる。
【０１３５】
そして、動きベクトルの生成は、前述のブロック単位の探索と、画素単位の再探索の２段階で行うので、全体としての演算量削減率をＫｍｖとすれば、Ｋｍｖは（式６）で表すことができる。
【０１３６】
【数６】

【０１３７】
したがって、最悪ケース（Ｍｂ＝Ｍｐ＝１）の場合でも、動きベクトルの探索、生成に要する演算量は、全体で２桁以上削減することができる。これにより、動き補正の信号処理を行う回路の規模を極めて小さくすることができる。
【０１３８】
上記実施例によれば、高画質でしかも回路規模の小さい画像信号の方式変換装置を得ることができる。また、この方式変換装置を用いることにより、マルチソース対応の高画質かつ低コストのテレビジョン受像機を実現することができる。
【０１３９】
図２８は、本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。本実施例は、ＰＡＬ方式のテレビジョン（以下ＴＶと略称）信号をＮＴＳＣ方式の順次走査のＴＶ信号に変換するものである。
【０１４０】
ＰＡＬ方式ＴＶ信号の復調信号Ｓ７１（輝度信号成分と色差信号成分）は、ＩＰ変換部７１に入力し、飛び越し走査の信号を順次の走査の信号に変換（以下、飛び越し→順次走査変換と略称）する。すなわち、輝度信号成分は動き適応型の補間処理、色差信号はライン間の補間処理で補間走査線の信号を生成し、出力にフレーム周波数５０Ｈｚの順次走査の信号系列Ｓ２を得る。
【０１４１】
垂直６−５変換部７２は、６−５変換処理の走査線数変換を行い、ＮＴＳＣ方式のＴＶ信号と等価な走査線数の信号系列Ｓ７３（但し、フレーム周波数は５０Ｈｚ）を生成する。すなわち、図２９に示す様に、６本の走査線ａ，ｂ，ｃ，ｄ，ｅ，ｆの組を単位に、入出力特性が２点直線補間の特性で演算を行い、５本の走査線ｖ，ｗ，ｘ，ｙ，ｚの信号を生成する。ＩＰ変換部７１及び垂直６−５変換部７２はフレーム周波数が変換される画像信号の画像信号発生部を構成し、従来知られている技術が使用できる。
【０１４２】
信号Ｓ７３及びフレームメモリ７３で１フレーム期間遅延させた信号Ｓ７４（以下前フレームの信号と呼ぶ）は、動き検出部７４と、動きベクトル検出部７５と、動き補正処理部７６に入力される。
【０１４３】
動き検出部７４は、信号Ｓ７３とＳ７４の輝度信号成分に対し、減算演算で１フレーム間の差分信号成分を画素毎に抽出し、２値化、平滑化の処理を行い、動き検出信号ＦＤ（動き無し“０”、動き有り“１”の２値信号）を出力する。なお、動き検出部７４の具体的な構成については後述する。
【０１４４】
動きベクトル検出部７５は、ブロックマッチング処理でブロック単位（例えば１６画素×１６ラインあるいは８画素×８ライン）の動きベクトルを検出する。すなわち、ブロック内の全ての画素の動き検出信号ＦＤが“０”のブロックは静止と判定し、動きベクトル信号Ｖに０を出力する。一方、動き検出信号ＦＤに“１”の画素を含むブロックは動画と判定し、信号Ｓ７３とＳ７４の輝度信号成分に対して、ブロックマッチング処理で誤差最小となるブロック対の探索を行い、この結果を動きベクトル信号Ｖとして出力する。動きベクトル検出部７５の具体的な構成についても後述する。
【０１４５】
動き補正処理部７６は、動き検出信号ＦＤが“１”の画素に対しては、動き補正型の信号処理を行う。すなわち、動きベクトルＶで補正補間動きベクトルを作り、現フレームの信号Ｓ７３と前フレームの信号Ｓ７４の画像の位置をこの補正補間動きベクトルで移動させた信号で、内挿フレームの信号を生成する。一方、動き検出信号ＦＤが“０”の画素に対しては、現フレームと前フレームの信号の平均値、あるいは現フレームの信号で、内挿フレームの信号を生成する。この出力に動き補正型のフレーム数変換処理したフレーム周波数が６０ＨｚのＮＴＳＣ方式の順次走査の信号Ｓ７５を得る。動き補正処理部７６の構成については後述する。
【０１４６】
以下、本実施形態における主要ブロック部の構成及び動作について説明する。
図３０は、動き検出部７４の一構成例図である。減算部７７は、順次走査の現フレームの信号Ｓ７３と前フレームの信号Ｓ７４の輝度信号成分の減算演算を行い、１フレーム間の差分信号成分を画素毎に得る。２値化部７８は、差分信号成分の信号レベルが設定値±Ｔｈ未満の場合は静止領域と判定して“０”、±Ｔｈ以上の場合は動画領域と判定して“１”、の２値信号を出力する。平滑部７９は、水平・垂直空間領域での積分操作等の平滑化処理を行う。そして、孤立点の除去や不連続点の補充を行った動き検出信号ＦＤを得る。
【０１４７】
図３１は、動きベクトル検出部７５の第１の構成例図である。静止ブロック検出部８１は、ブロック単位（例えば１６画素×１６ラインあるいは８画素×８ライン）毎に、動き検出信号ＦＤの“１”の有無を検出する。そして、信号ＦＤがブロック内の全て画素について“０”の場合のみ信号ＢＭに“０”、それ以外の場合は“１”を出力する。ブロックマッチング処理部８０は、信号ＢＭが“１”の場合のみ、順次走査の現フレームの信号Ｓ７３と前フレームの信号Ｓ７４の輝度信号成分を用いて、ブロックマッチング処理で誤差最小のブロック対の探索を行い、得られたブロック対での動きベクトルＶａを出力する。この結果、信号ＢＭが“１”の場合のみ、動きベクトルＶａの探索を行うので、ブロックマッチング処理による動きベクトルの探索は動画ブロックに限定でき、探索に要する信号処理の演算量が大幅に低減できる。選択部８２は、信号ＢＭが“０”の静止ブロックは０の動きベクトル、信号ＢＭが“１”の動画ブロックは、ブロックマッチング処理部８０で検出したＶａを、動きベクトル信号Ｖとして出力する。
【０１４８】
図３２は、動きベクトル検出部７５の第２の構成例図である。本構成例は、図３１の構成に隣接動き情報検出部８３と、動きベクトル修正部８４とを追加して、より精度の高い動きベクトルの検出を行うものである。隣接動き情報検出部８３は、隣接ブロックとの動きの相関関係を検出する信号処理を行うもので、その動作概略を図３３（ａ）、図３３（ｂ）を用いて説明する。図３３（ａ）に示すように、隣接動き情報検出部８３は、現ブロックに接する上下と左右の隣接ブロックとの境界領域ｌｕ，ｌｒ，ｌｄ，ｌｌにおける動き検出信号ＦＤの形態で動きの相関関係を検出し、図３３（ｂ）に示す隣接ブロック動き情報信号ＡＢＭ（１〜９）を出力する。例えば、境界領域に動き検出信号ＦＤに“１”が複数個数（例えば４以上）存在する状態が領域ｌｕのみの場合（ｌｕ≠０，ｌｒ＝ｌｄ＝ｌｌ＝０）は、上ブロックと動きの相関関係があると判定し、信号ＡＢＭに“１”を出力する。以下同様に、“１”の動き検出信号ＦＤが複数個数（例えば４以上）存在する状態が領域ｌｒ，ｌｄ及びｌｌのみの場合は、それぞれ右、下及び左ブロックと動きの相関関係があると判定し、信号ＡＢＭ２〜４を出力する。
【０１４９】
また、“１”の動き検出信号ＦＤが複数個数（例えば４以上）存在する状態が連続した２つの領域で発生する場合は、対応する複数の隣接ブロックと動きの相関関係があると判定し、信号ＡＢＭ５〜８を出力する。例えば、“１”の動き検出信号ＦＤが複数個数（例えば４以上）存在する状態が領域が領域ｌｕ及びｌｒで発生する場合は、上と右ブロックとの動きの相関関係を示すＡＢＭ５を出力する。なお、動き検出信号ＦＤに“１”が複数個数（例えば４以上）存在する状態がこれら以外の形態の場合は、現ブロックのみで精度の高い動きベクトルの検出が可能と判定し、ＡＢＭ９を出力する。
【０１５０】
動きベクトル修正部８４は、隣接ブロック動き情報信号ＡＢＭに応じて、図３３（ｂ）に示す様に、現ブロックと該当する隣接ブロックの動きベクトルの平均操作で修正動きベクトルを生成し出力する。例えば、信号ＡＢＭが１の時は、現ブロックの動きベクトルＶｏと上ブロックの動きベクトルＶｕとの平均で生成した修正動きベクトル（Ｖｏ＋Ｖｕ）／２を出力する。また、信号ＡＢＭが５の時は、現ブロックの動きベクトルＶｏと、上ブロックの動きベクトルＶｕと、右ブロックの動きベクトルＶｒとの平均で生成した修正動きベクトル（Ｖｏ＋Ｖｕ＋Ｖｒ）／３を出力する。なお、信号ＡＢＭが９の時は、現ブロックの動きベクトルＶｏをそのまま出力する。以上に述べた簡単な修正処理で、より高精度な動きベクトルの検出ができる。
【０１５１】
図３４は、動きベクトル検出部７５の第３の構成例図である。図中、静止ブロック検出部８１、ブロックマッチング処理部８０は、図３１の同じ番号を付す部分と実質的に同じである。制御部８３’は、静止ブロック検出部８１からのブロック単位の信号ＢＭに従って、ブロックマッチング処理部８０及び画素動きベクトル算出部８２’の動作に必要な制御信号ＣＴを生成する。画素動きベクトル算出部８２’は、ブロック単位の動きベクトルＶａから、画素の動きベクトル信号Ｖを算出する。
【０１５２】
図３５は、画素動きベクトル算出部８２’の第１の構成例図である。算出部８２’は、後で図３６で説明するように、現ブロックとこれに隣接する上下左右ブロックの動きベクトルを用いて、ミニブロック単位（例えば２画素×２ライン）で動き補正誤差が最少になる動きベクトルをミニブロック内の画素の動きベクトルに割り当てる処理を行い、動きベクトル信号Ｖを出力する。隣接ブロック動きベクトル配列部８４’は、制御信号ＣＴに従い、ブロック単位の動きベクトルＶａから上記ミニブロックに対応する現ブロックと隣接ブロックの動きベクトルＶｏ，Ｖｕ，Ｖｒ，Ｖｄ，Ｖｌを出力する。
【０１５３】
誤差算出部８５−１，…，８５−６は、それぞれ現フレームの信号Ｓ７３と前フレームの信号Ｓ７４に対して、ミニブロック単位に以下の式（７）の動き補正誤差信号ＥＲ，ＥＲｏ，…及びＥＲｌを算出する。
【０１５４】
【数７】

【０１５５】
ここで、記号ａｂｓ｛ ｝は絶対値、Ｖｉｘ，Ｖｉｙ（ｉ＝ｏ，ｕ，ｒ，ｄ又はｌ）は動きベクトルＶｉのｘ方向、ｙ方向の成分、Σはミニブロック内の全ての画素の総和を示す。
【０１５６】
判定部８６は、動き補正誤差信号ＥＲ，ＥＲｏ，…及びＥＲｌの中で最少値を検出し、この最少値に対応する動きベクトルＶｍｂをミニブロック内の画素の動きベクトルとして出力する。選択部８７は、制御信号ＣＴが静止ブロックを示す時は、現ブロックの動きベクトルＶｏ（Ｖｏ＝０）、動画ブロックの時は動きベクトルＶｍｂを選択し、画素の動きベクトル信号Ｖを出力する。
【０１５７】
図３６は、上記画素単位の動きベクトル算出の概略及び効果を説明する図で、動画像面の一部を示す。図中の現ブロックは、動きの異なるドット領域の動画像物体ｐと斜線領域の動画像物体ｑが混在している。従って、現ブロックの動きベクトルＶｏは、いずれの動画像物体ｐ、ｑの動きとも異なったものになり、動きベクトル検出が不正確となる。一方、隣接する上ブロックと左ブロックで検出する動きベクトルＶｕ，Ｖｌは、動画像物体ｐの動きとほぼ一致する。また、右ブロックと下ブロックで検出する動きベクトルＶｒ，Ｖｄは、動画像物体ｑの動きとほぼ一致する。
【０１５８】
ミニブロックＡは動画像物体ｐの領域であるので、動き補正誤差は信号ＥＲｕ又はＥＲｌが最少になる。従って、ミニブロックＡの画素には動きベクトルＶｏの代わりに動きベクトルＶｕ又はＶｌが割り当てられる。一方、ミニブロックＢは動画像物体ｑの領域であるので、動き補正誤差は信号ＥＲｒ又はＥＲｄが最少になる。従って、ミニブロックＢの画素には動きベクトルＶｏの代わりに動きベクトルＶｒ又はＶｄが割り当てられる。また、ミニブロックＣは静止の領域であるので、動き補正誤差は信号ＥＲが最少になる。従って、ミニブロックＣの画素には動きベクトルＶｏの代わりに動きベクトル０が割り当てられる。
【０１５９】
上述のように、ミニブロック単位で動き補正誤差を算出し、これが最少となる動きベクトルをミニブロックの画素の動きベクトルに割り当てる処理で、ブロック単位で検出する動きベクトルに不正確な動きベクトルが存在する時でも、画素単位ではほぼ正確な動きベクトルの算出が実現できる。すなわち、画像の一部が不適切な画像に置き換えられる孤立点的な劣化を大幅に抑圧できる。
【０１６０】
図３７は、図３４の画素動きベクトル算出部８２’の第２の構成例図である。本構成例は、図３５の構成に特異ベクトル修正部８８を追加し、より精度の高い動きベクトルの検出を行うものである。すなわち、特異ベクトル修正部８８は、始めに、現ミニブロックの動きベクトルＶｏｍと、これに隣接する上下左右のミニブロックの動きベクトルＶｕｍ，Ｖｒｍ，Ｖｄｍ，Ｖｌｍとで以下の式（８）に示す差分値ＥＶ１、ＥＶ２、ＥＶ３及びＥＶ４を計算する。
【０１６１】
【数８】

【０１６２】
この差分値が全て許容誤差範囲（例えば、ｘ方向１画素以内、又はｙ方向１ライン以内）を越える動きベクトルＶｏｍは特異ベクトルと判定する。そして、特異ベクトルに対しては、隣接する上下左右のミニブロックの動きベクトルとの平均値で生成する修正ベクトルＶｍｄに置き換える。従って、動きの不正確な特異ベクトルは、より精度の高い修正ベクトル（Ｖｍｄ＝（Ｖｏｍ＋Ｖｕｍ＋Ｖｒｍ＋Ｖｄｍ＋Ｖｌｍ）／５）で置き換えられ、動きベクトルの更なる精度向上を図ることができる。
【０１６３】
上述のように、ミニブロック単位で動き補正誤差を算出し、これが最少となる動きベクトルをミニブロックの画素の動きベクトルに割り当てる処理で、ブロック単位で検出する動きベクトルに不正確な動きベクトルが存在する時でも、画素単位ではほぼ正確な動きベクトルの算出が実現できる。すなわち、画像の一部が不適切な画像に置き換えられる孤立点的な劣化を大幅に抑圧できる。
【０１６４】
図３８は、図２８の動き補正処理部７６の第１の構成例のブロック図である。加算部８９は、現フレームの信号Ｓ７３と前フレームの信号Ｓ７４とを加算平均し、内挿フレームの静止領域の信号成分Ｓａｖを生成する。補正信号生成部９０−１は、前フレームの信号Ｓ７４と補正補間動きベクトルＶｐｒで動き補正信号Ｓｐｒを生成し、補正信号生成部９０−２は現フレームの信号Ｓ７３と補正補間動きベクトルＶｃｔで動き補正信号Ｓｃｔを生成する。補正信号生成部９０−１、９０−２の動作概略を図４０（ａ）に示す。内挿フレームｆｉｐの点Ａ（ｘ、ｙ）に対しては、動き補正信号Ｓｐｒは前フレームｆｐｒの点Ａ（ｘ、ｙ）を補正補間動きベクトルＶｐｒ（水平方向成分Ｖｐｒｘ，垂直方向成分Ｖｐｒｙ）で移動させた点Ａ’’（ｘ＋Ｖｐｒｘ，ｙ＋Ｖｐｒｙ）の位置の信号、動き補正信号Ｓｃｔは現フレームｆｃｔの点Ａ（ｘ、ｙ）を補正補間動きベクトルＶｃｔ（水平方向成分Ｖｃｔｘ，垂直方向成分Ｖｃｔｙ）で移動させた点Ａ’（ｘ−Ｖｃｔｘ，ｙ−Ｖｃｔｙ）の位置の信号である。すなわち、
【０１６５】
【数９】

【０１６６】
である。従って、点Ａでは点Ａ’，Ａ’’の画素の信号を読み出すようにメモリ回路の読み出しアドレスを補正補間動きベクトルで制御することで簡単に実現できる。なお、補正補間動きベクトルの生成に関しては後述する。
【０１６７】
加算部９２では、両者の動き補正信号ＳｐｒとＳｃｔとを加算平均し、内挿フレームの動画領域の信号成分Ｓｍｃを生成する。
【０１６８】
スイッチ部９３は、動き検出信号ＦＤが“０”の画素では信号Ｓａｖを選択し、信号ＦＤが“１”の画素では信号Ｓｍｃを選択する。この出力に動画領域は動き補正型の信号処理でフレーム数変換したフレーム周波数が６０ＨｚのＮＴＳＣ方式の順次走査の信号Ｓ５を得る。
【０１６９】
フレーム順制御部９１は、フレームシーケンス信号ＦＳのフレーム順情報をもとに、動き補正処理に必要な補正補間動きベクトルＶｃｔ，Ｖｐｒを生成する。この動作概略を図４０（ｂ）に示す。フレーム周波数５０ＨｚのＰＡＬ順次走査フレーム順の１から５の信号に対し、動き補正型のフレーム内挿処理で、フレーム順１から６のフレーム周波数が６０ＨｚのＮＴＳＣ順次走査の信号に変換する。この際、補正補間動きベクトルは、内挿するフレーム位置に合致する必要がある。そこで、フレームシーケンス信号ＦＳのフレーム順情報に応じて、同図に示す様に、動きベクトル信号Ｖに係数加重する係数値ｋａ，ｋｂを変化させ、以下の演算式（１０）で補正補間動きベクトルＶｐｒ、Ｖｃｔを生成する
【０１７０】
【数１０】

【０１７１】
従って、フレーム順が２の内挿フレームでは、Ｖｐｒ＝Ｖ＊５／６，Ｖｃｔ＝−Ｖ＊１／６（ｋａ＝５，ｋｂ＝１）、３のものでは、Ｖｐｒ＝Ｖ＊４／６，Ｖｃｔ＝−Ｖ＊２／６（ｋａ＝４，ｋｂ＝２）…の如く、時間方向での位置ずれがない補正補間動きベクトルを生成する。この結果、時間方向での揺らぎのないフレーム数変換を実現する。
【０１７２】
図３９は、図２８の動き補正処理部７６の第２の構成例のブロック図である。これは、内挿フレームの静止領域の信号成分Ｓａｖを現フレームの信号Ｓ７３で生成する点に図３８の構成例と異なり、より簡単な信号処理で実現できる。なお、他の各部の構成、機能は、図３８の構成例と同じであり、説明は省略する。
【０１７３】
以上に述べた如く、本実施例によれば、動き補正の信号処理に要する演算量が少なく、回路規模も小さく、また、画質劣化の少ないＰＡＬ−ＮＴＳＣ順次走査の方式変換装置が実現できる。
【０１７４】
図４１は、本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。本実施例は、ＰＡＬ方式のテレビジョン信号をＰＡＬ方式のテレビジョン信号と同一走査線数のフレーム周波数が６０Ｈｚの順次走査の信号に変換するものである。
【０１７５】
本実施例は、図２８の垂直６−５変換部７２を除いたもので、他の部分は実質的に図２８の構成と同じであるので、その詳細な説明は省く。本実例によれば、動き補正の信号処理に要する演算量が少なく、回路規模も小さく、また、画質劣化の少ない、フレーム周波数６０ＨｚのＰＡＬ順次走査への方式変換装置が実現できる。
【０１７６】
図４２は、本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。本実施例は、ＰＡＬ方式のテレビジョン信号をフレーム周波数が６０Ｈｚの順次走査のＮＴＳＣ方式のテレビジョン信号に変換するもので、動きベクトルの検出の信号処理を簡易にしたものである。同図のＩＰ変換部７１、垂直６−５変換部７２、フレームメモリ７３、動き検出部７４、動き補正処理部７６は、その構成及び動作が第１の実施例のものと同一であるので、その説明は省略する。
【０１７７】
簡易型動きベクトル検出部９４は、動き検出部７４の動き検出信号ＦＤを用いてブロック単位又は画素単位の動きベクトルを検出する。
【０１７８】
図４３は、簡易型動きベクトル検出部９４の第１の構成例のブロック図である。静止ブロック検出部８１はブロック単位で動き検出信号ＦＤの“１”の有無を検出し、全て“０”の場合のみ信号ＢＭに“０”、それ以外の場合は“１”を出力する。制御部８３は、信号ＢＭを制御信号ＣＴにし、ブロックマッチング処理部９６及び画素動きベクトル算出部８２’に加える。
【０１７９】
ブロックマッチング処理部９６は、制御信号ＣＴが静止ブロックを示す場合は、信号Ｖａに０を出力する。一方、制御信号ＣＴが動画ブロックを示す場合には、１フレーム遅延部９５で１フレーム期間遅延させた前フレームの動き検出信号ＦＤｐｒと、現フレームの動き検出信号ＦＤとで、ブロックマッチング処理による誤差最小のブロック対の探索を行い、得られた動きベクトルを信号Ｖａに出力する。この場合、信号ＦＤｐｒ、ＦＤは“０”と“１”の２値信号であるため、この誤差最小のブロック対の探索は、ＥＸＯＲ（排他的論理和）回路とアダー回路と比較回路を組み合わせた極めて簡単な論理回路で行うことができる。
【０１８０】
画素動きベクトル算出部８２’は、前述の図３５、図３７と同様な構成で、ミニブロック単位に、現ブロックとこれに隣接する上下左右のブロックの動きベクトルで１フレーム期間遅延させた前フレームの動き検出信号ＦＤｐｒと、現フレームの動き検出信号ＦＤとの動き補正誤差を算出し、これが最少となる動きベクトルを画素の動きベクトルに割り当てる。信号ＦＤとＦＤｐｒは２値の信号であるため、動き補正誤差の算出をより簡単に実行することができる。
【０１８１】
図４４は、簡易型動きベクトル検出部９４の第２の構成例のブロック構成図で、ブロック単位の動きベクトルを検出するものである。静止ブロック検出部８１はブロック単位で動き検出信号ＦＤの“１”の有無を検出し、全て“０”の場合のみ信号ＢＭに“０”、それ以外の場合は“１”を出力する。選択部８２は、信号ＢＭが“０”の静止ブロックは０の動きベクトル、ＢＭが“１”の動画ブロックは簡易ブロックマッチング処理部２６で検出した動きベクトルＶａを動きベクトル信号Ｖとして出力する。
【０１８２】
簡易ブロックマッチング処理部９６は、信号ＢＭが“１”の場合のみ、１フレーム遅延部９５で１フレーム期間遅延させた前フレームの動き検出信号ＦＤｐｒと、現フレームの動き検出信号ＦＤとで、ブロックマッチング処理による誤差最小のブロック対の探索を行い、得られた動きベクトルＶａを出力する。この場合、信号ＦＤｐｒ、ＦＤは“０”と“１”の２値信号であるため、この誤差最小のブロック対の探索は、ＥＸＯＲ（排他的論理和）回路とアダー回路と比較回路を組み合わせた極めて簡単な論理回路で行うことができる。従って、ブロックマッチング処理で動きベクトルを探索する信号処理の演算量の大幅な低減、及び回路規模の削減を図ることができる。
【０１８３】
図４５は、簡易型動きベクトル検出部９４の第３の構成例のブロック構成図で、ブロック単位の動きベクトルを検出するものである。本構成例は、図４４の構成に、隣接動き情報検出部８３と、動きベクトル修正部８４とを追加して、精度の高い動きベクトルの検出を行うものである。すなわち、前述の図３２と同様に、隣接ブロックとの境界領域での動き検出信号ＦＤの形態で動きの相関関係を検出し、現ブロックと動きの相関が高い隣接ブロックとの動きベクトルの平均操作で修正動きベクトルを生成し出力する。
【０１８４】
以上に述べた如く、本実施例によれば、代表的に図２８に示された実施例と比較して、更に動き補正の信号処理に要する演算量が少なく、回路規模も小さい方式変換装置が実現できる。
【０１８５】
図４６は、本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。本実施例は、ＰＡＬ方式のテレビジョン信号をフレーム周波数が６０Ｈｚの順次走査のＮＴＳＣ方式のテレビジョン信号に変換するもので、特に、動きの滑らかさが損なわれるモーションジャダーの目立ち易い速度の動きに対してのみ動き補正処理を行うものである。
【０１８６】
図中のＩＰ変換部７１と、垂直６−５変換部７２と、フレームメモリ７３と、動き検出部７４と、動きベクトル検出部７５は、図２８と同様の構成、動作を行う。ＭＣ動作制御部９７は、動きベクトル信号Ｖで、ブロック毎、画素あるいはミニブロック単位でモーションジャダーが目立ちやすい速度（例えば、数秒〜１０秒／画面幅又は画面高）の動きを検出する。そして、動きベクトル信号Ｖがこの範囲の速度に該当するブロック、画素あるいはミニブロックでは“１”、それ以外では、“０”のＭＣ制御信号ＩＰＭを出力する。
【０１８７】
動き補正処理部９８は、図３９に示した構成を若干変更した形態で実現する。図３９に示した構成では、スイッチ部９３は動き検出信号ＦＤで信号Ｓ７３と信号Ｓｍｃとの選択を行うが、本実施形態では、これを動き検出信号ＦＤとＭＣ制御信号ＩＰＭとの論理積演算（ＡＮＤ回路）で得られる信号に変更する。すなわち、動き検出信号ＦＤが“１”、かつ、ＭＣ制御信号ＩＰＭが“１”の場合に信号Ｓａｖを選択する。この出力にモーションジャダーの目立ちやすい速度の動きに対してのみ動き補正型の信号処理でフレーム数変換したフレーム周波数が６０ＨｚのＮＴＳＣ方式の順次走査の信号Ｓ７５を得る。本実施例によれば、特定範囲の動き速度の信号のみについて信号処理を行うので、演算量が少なく、回路規模も小さく、動き補正処理をモーションジャダー妨害の目立ちやすい動きに限定した方式変換装置が実現できる。
【０１８８】
図４７は、本発明の他の実施例による動き補正型画像信号の変換装置の構成ブロック図である。本実施形態は、ＰＡＬ方式のテレビジョン信号をフレーム周波数が６０Ｈｚの順次走査のＮＴＳＣ方式のテレビジョン信号に変換するもので、特に図４２の構成に、図４６に示されたの実施例で述べたＭＣ動作制御部９７と動き補正処理部９８とを追加して構成したものである。図４６に示された実施例と同様な動作を行い、モーションジャダーの目立ちやすい速度の動きに対してのみ動き補正型の信号処理でフレーム数変換したフレーム周波数が６０ＨｚのＮＴＳＣ方式の順次走査の信号Ｓ５を得る。本実施例によれば、回路規模の更なる小型化を図った方式変換装置を実現する。
【０１８９】
図４８は、本発明の他の実施例による動き補正型画像信号の変換装置の構成ブロック図である。本実施例は、ＰＡＬ方式のテレビジョン信号をフレーム周波数が６０Ｈｚの順次走査のＮＴＳＣ方式のテレビジョン信号に変換するもので、特に画面全体が一様な速度で動く水平パンや上下パンや、文字スクロール等の特殊な動きに対してのみ、動き補正型の信号処理を行うに好適なものである。
【０１９０】
本実施例は、前述の図４６のＭＣ動作制御部９７をＭＣ限定動作制御部９９で置き換えたものである。
【０１９１】
ＭＣ限定動作制御部９９は、動き検出信号ＦＤと動きベクトル信号Ｖを用いて、特殊な動きの検出を行う。すなわち、ブロック、ミニブロックあるいは画素単位で動きベクトル信号Ｖ≠０のブロックの動きベクトルの大きさと方向が全画面領域でほぼ同じ値をとる場合は上下パンや水平パンの動きと判定する。そして、全ての画面領域で“１”の信号を信号ＩＰＭに出力する。また、動き検出信号ＦＤで検出した動き領域の形状が帯状で、かつ、この領域のブロックの動きベクトルがほぼ同じ値をとる場合は文字スクロールの動きと判定する。そして、該当する文字スクロール領域のブロックで１の信号を信号ＩＰＭに出力する。これ以外の領域は、信号ＩＰＭには“０”を出力する。
【０１９２】
動き補正処理部９８は、前述の如く、信号ＩＰＭと動き検出信号ＦＤとの論理積演算の信号でスイッチ９３を制御するので、この出力に特殊な動きに限定して動き補正型の信号処理でフレーム数変換を行った信号を得る。
【０１９３】
本実施例によれば、モーションジャダーの目立ちやすい特殊な動きに限定して動き補正処理する方式変換装置が実現できる。
【０１９４】
図４９は、本発明による動き補正型画像信号の変換装置の第７の実施形態の構成ブロック図である。本実施例は、図４７のＭＣ動作制御部９７をＭＣ限定動作制御部９９で置き換えたものである。また、ＭＣ限定動作制御部９９の構成及び動作は、図４８の実施例と同様である。本実施例によれば、回路規模の更なる小型化を図った方式変換装置を実現している。
【０１９５】
図５０は、本発明の他の実施例による動き補正型画像信号の変換装置をテレビジョン受像機に適用した実施例を示す構成ブロック図である。なお、本実施例においては、画像表示部がフレーム周波数６０Ｈｚ、走査線数５２５本のＮＴＳＣ方式の順次走査表示を例に説明する。
【０１９６】
ベースバンド帯域のテレビジョン信号ＶＳは、ＮＴＳＣデコーダ部１００と、ＰＡＬデコーダ部１０１と、制御部１０２とに入力する。ＮＴＳＣデコーダ部１００は、ＮＴＳＣ方式に準じた復調処理（ＹＣ分離、色復調）の信号処理を行い、飛び越し走査の復調信号Ｓ８０（輝度信号と色差信号）を出力する。
【０１９７】
ＰＡＬデコーダ部１０１は、ＰＡＬ方式に準じた復調処理（ＹＣ分離、色復調）の信号処理を行い、飛び越し走査の復調信号Ｓ８１（輝度信号と色差信号）を出力する。制御部１０２は、テレビジョン信号ＶＳの同期信号をもとに方式判別を行い、該当方式の受像に必要な制御信号ＣＳを生成する。スイッチ部１０３は、ＮＴＳＣ方式では信号Ｓ８０、ＰＡＬ方式では信号Ｓ８１を制御信号ＣＳで選択する。
【０１９８】
ＩＰ変換部１０４は、動き適応型の飛び越し−順次の走査変換の信号処理を行い、順次走査の信号を出力する。スケーリング部１０５は、画像表示部のフォーマット（アスペクト比や走査線数）に変換する信号処理を行う。例えば、ＰＡＬ方式の信号は垂直６−５変換処理で走査線数５２５本の信号に変換する。また、ＰＣ画像信号等の順次走査の信号Ｓ８３は、所定の垂直変換処理で５２５本の走査線数の信号に変換する。
【０１９９】
フレームレート変換部１０６は、上述の変換装置で動き補正型のフレーム数変換の信号処理を行い、画像表示部１０８と同一のフレーム周波数の信号に変換する。例えば、ＰＡＬ方式のフレーム周波数５０Ｈｚの順次走査の信号は、動き補正のフレーム内挿処理でフレーム周波数６０Ｈｚの信号に変換する。
【０２００】
色空間変換部１０７は、輪郭補正や階調補正等の画質改善処理及び３原色信号への変換、逆ガンマ補正（表示部がリニアなガンマ特性の場合）等の信号処理を行う。そして、この出力信号を順次走査表示部１０８に供給して画像の表示を行う。
【０２０１】
本テレビジョン受像機によれば、マルチソース対応機能や画質向上を低コストで実現するテレビジョン受像機が実現でき、多機能化、高画質化に顕著な効果が得られる。なお、画像表示部がＨＤＴＶ方式に準拠したものでも、フレーム数変換に本発明の動き補正型画像信号の変換装置を適用することができる。
【０２０２】
図５１（ａ）、図５１（ｂ）は、本発明の他の実施例による動き補正型画像信号の変換装置で、映画等のフレーム周波数が２４Ｈｚのフィルム画像をフレーム周波数が６０Ｈｚの順次走査の信号に変換する装置の一実施例の構成及び動作を説明する図である。
【０２０３】
図５１（ａ）は、装置のブロック構成図で、ビデオ復調部１０９と、ＩＰ変換部１１０と、フレーム数変換部１１１と、制御部１１２からなる。
【０２０４】
入力映像信号ＶＳは、ビデオ復調部１０９で所定の復調処理を行い、輝度信号と色差信号からなる飛び越し走査の信号Ｓ９０を復調する。
【０２０５】
制御部１１２は、映像信号ＶＳのフレーム間差分信号成分がゼロとなるフレームの発生周期等より、映像信号が一般画像の信号かテレシネ画像の信号（映画等のフィルム画像を２−３プルダウン処理でテレビジョン方式のフォ−マットに変換した信号）かを判定し、信号ＣＴＳに一般画像では１、テレシネ画像では０の信号を出力する。
【０２０６】
ＩＰ変換部１１０は、信号ＣＴＳが“１”の時は、従来の動き適応型の走査変換処理で順次走査の信号に変換する。一方、信号ＣＴＳが“０”の時は、フィルムモ−ドの補間処理で同一駒の信号である前後のフィ−ルドの信号で補間走査線の信号を生成し、フレーム周波数が２４Ｈｚのテレシネ順次走査の信号に変換する。
【０２０７】
フレーム数変換部１１１は、信号ＣＴＳが“１”の時は、前述した実施例と同様な動作の動き補正型のフレーム数変換処理でフレーム周波数６０Ｈｚの順次走査の信号ＶＯを生成する。一方、信号ＣＴＳが“０”の時は、図５１（ｂ）に示すフレーム順のシーケンスで、動き補正処理に必要な補正補間動きベクトルＶｃｔ，Ｖｐｒを生成する。すなわち、同図に示す様に、動きベクトル信号Ｖに係数加重する係数値ｋａ，ｋｂを変化させ、以下の演算で補正補間動きベクトルＶｐｒ、Ｖｃｔを生成する。
【０２０８】
【数１１】

【０２０９】
従って、フレーム順が２の内挿フレームでは、Ｖｐｒ＝Ｖ＊２／５，Ｖｃｔ＝−Ｖ＊３／５（ｋａ＝２，ｋｂ＝３）、３の内挿フレームでは、Ｖｐｒ＝Ｖ＊４／５，Ｖｃｔ＝−Ｖ＊１／５（ｋａ＝４，ｋｂ＝１）…の如く、補正補間動きベクトルを生成する。そして、フレーム周波数２４Ｈｚのテレシネ順次走査のフレーム順の１から２の信号に対し、動き補正型のフレーム内挿処理で、フレーム順１から５のフレーム周波数が６０Ｈｚの順次走査の信号ＶＯに変換する。
【０２１０】
以上に述べた如く、本実施例によれば、映画等のフィルム画像をフレーム周波数が６０Ｈｚの順次走査の信号に変換するフレーム数変換装置を、低コスト、高品質で実現することができる。
【０２１１】
以上、本発明は上記実施例に限定されるものではなく、例えば、図３２〜図４９に示された実施形態において、図４１に示された実施例のように、垂直６−５変換部を省略した構成で、ＰＡＬ方式のテレビジョン信号をフレーム周波数が５０Ｈｚより高い順次走査の信号に変換する方式変換装置が実現できる。
【０２１２】
【発明の効果】
上記実施例によれば、動き補正の信号処理に要する演算量が少なく、回路規模も小さく、また、画質劣化の少ない方式変換装置が実現できる。このため、テレビジョン受像機におけるマルチソース対応機能や画質向上の実現に顕著な効果を得ることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施例を示す方式変換装置のブロック構成図である。
【図２】動き検出部の一構成例を示す図である。
【図３】ブロック単位動きベクトル探索部の一構成例を示す図である。
【図４】画素単位動きベクトル生成部の第１構成例を示す図である。
【図５】画素単位動きベクトル生成部の第２構成例を示す図である。
【図６】画素単位動きベクトル生成部の第３構成例を示す図である。
【図７】画素単位動きベクトル生成部の第４構成例を示す図である。
【図８】動き補正内挿フレーム生成部の第１構成例を示す図である。
【図９】（ａ）乃至（ｃ）はそれぞれフレーム順制御部と動き補正信号生成部の動作概略を示す図である。
【図１０】動き補正内挿フレーム生成部の第２構成例を示す図である。
【図１１】本発明の第２の実施例を示す方式変換装置のブロック構成図である。
【図１２】シーンチェンジ検出部の一構成例を示す図である。
【図１３】本発明の第３の実施例を示す方式変換装置のブロック構成図である。
【図１４】本発明の第４の実施例を示す方式変換装置のブロック構成図である。
【図１５】本発明の第５の実施例を示す方式変換装置のブロック構成図である。
【図１６】本発明の第６の実施例を示す方式変換装置のブロック構成図である。
【図１７】ブロック単位動きベクトル探索処理のフローチャートを示す図である。
【図１８】（ａ）及び（ｂ）はそれぞれブロック単位動きベクトル探索動作の概略を示す図である。
【図１９】画素単位動きベクトルの第１の生成方法の概略を示す図である。
【図２０】画素単位動きベクトル生成動作の概略を示す図である。
【図２１】（ａ）及び（ｂ）はそれぞれ画素単位動きベクトルの第２の生成方法の概略を示す図である。
【図２２】画素単位動きベクトルの第３の生成方法の概略を示す図である。
【図２３】（ａ）及び（ｂ）はそれぞれ画素単位動きベクトルの第４の生成方法の概略を示す図である。
【図２４】本発明の一実施例によるテレビジョン受像機を示す全体ブロック構成図である。
【図２５】本発明の他の実施例によるテレビジョン受像機を示す全体ブロック構成図である。
【図２６】本発明の他の実施例によるテレビジョン受像機を示す全体ブロック構成図である。
【図２７】テレビジョン受像機の第４の実施例を示す全体ブロック構成図である。
【図２８】本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。
【図２９】図２８の垂直６−５変換部２における信号処理概略図である。
【図３０】図２８の動き検出部４の一構成例のブロック図である。
【図３１】図２８の動きベクトル検出部５の第１の構成例のブロック図である。
【図３２】図２８の動きベクトル検出部５の第２の構成例のブロック図である。
【図３３】図３２の隣接動き情報検出部１３の動作概略の説明図である。
【図３４】図２８の動きベクトル検出部５の第３の構成例のブロック図である。
【図３５】図３４の画素動きベクトル算出部１２’の第１の構成例のブロック図である。
【図３６】画素動きベクトル算出部の動作説明のための部分画像図である。
【図３７】図３４の画素動きベクトル算出部１２’の第２の構成例のブロック図である。
【図３８】図２８の動き補正処理部６の第１の構成例のブロック図である。
【図３９】図２８の動き補正処理部６の第２の構成例のブロック図である。
【図４０】（ａ）及び（ｂ）は、動き補正処理によるフレーム内挿の動作概略説明図である。
【図４１】本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。
【図４２】本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。
【図４３】図４２の簡易型動きベクトル検出部２４の第１の構成例の構成ブロック図である。
【図４４】図４２の簡易型動きベクトル検出部２４の第２の構成例の構成ブロック図である。
【図４５】図４２の簡易型動きベクトル検出部２４の第３の構成例の構成ブロック図である。
【図４６】本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。
【図４７】本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。
【図４８】本発明の他の実施例による動き補正型画像信号の変換装置の第６の実施形態の構成を示すブロック図である。
【図４９】本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。
【図５０】本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。
【図５１】（ａ）及び（ｂ）は、本発明の他の実施例による動き補正型画像信号の変換装置の構成を示すブロック図である。
【符号の説明】
１、７１、１０４、１１０…ＩＰ変換部、２…動き補正フレーム数変換部、３、９５…１フレーム遅延部、４、７４…動き検出部、５…ブロック単位動きベクトル探索部、６…画素単位動きベクトル生成部、７…動き補正内挿フレーム生成部、８、７７…減算部、７２…垂直７６−５変換部、７３…フレームメモリ、７５…動きベクトル検出部、７６、９８…動き補正処理部、７８…２値化部、７９…平滑部、８０…ブロックマッチング処理部、８１…静止ブロック検出部、８２…選択部、８２’…画素動きベクトル算出部、８３…隣接動き情報検出部、８３’…制御部、８４…動きベクトル修正部、８４’…隣接ブロック動きベクトル配列部、８５…誤差算出部、８６…判定部、８７…選択部、８８…特異ベクトル修正部、８９、９２…加算部、９０…補正信号生成部、９１…フレーム順制御部、９３、１０３…スイッチ部、９４…簡易型動きベクトル検出部、９６…簡易ブロックマッチング処理部、９７…ＭＣ動作制御部、９９…ＭＣ限定動作制御部、１００…ＮＴＳＣデコーダ部、１０１…ＰＡＬデコーダ部、１０２…制御部、１０５…スケーリング部、１０６…フレームレート変換部、１０７…色空間変換部、１０８…順次走査表示部、１０９…ビデオ復調部、１１１…フレ−ム数変換部、１１２…制御部。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image signal system conversion apparatus and a television receiver, and more particularly to an image signal system conversion apparatus suitable for generating an interpolated frame and converting the number of frames of an image signal by signal processing for motion correction. The present invention relates to a television receiver.
[0002]
[Prior art]
System conversion, which is signal conversion between different television systems, is widely used for program exchange and the like in the field of broadcasting. In general, since the conversion of the number of operation lines and the field frequency is required in the system conversion, resolution degradation and image quality degradation such as motion judder in which smoothness is lost in motion images occur.
[0003]
In order to prevent such deterioration, a signal processing technique such as a motion adaptive scanning line number / sequential scanning conversion method has been devised for scanning line number conversion, and a motion correction type frame number conversion method has been devised for frame number conversion.
[0004]
Of these, the motion correction type frame number conversion method generates an interpolated frame signal by moving the image position of the preceding and succeeding frames using a motion vector, and is extremely effective in removing motion judder in the motion image. For this reason, almost all broadcast-related system conversion devices adopt this method.
[0005]
As for a motion prediction method for a television image, for example, Japanese Patent Application Laid-Open No. 7-170496 (French Patent Application No. 93402188.2 filed on September 8, 1993) published on July 4, 1995. And Japanese Patent Application No. 93117661.4 filed on Nov. 2, 1993). In this method, a motion vector of one pixel is calculated using a motion vector of one block of interest and a motion vector of three adjacent blocks. Thus, it is possible to provide an apparatus that combines the advantage of reliability of a large block with the performance of a more localized position determination motion vector.
[0006]
However, the signal processing for frame number conversion for motion correction used in a broadcast-related system conversion device requires a huge amount of computation for signal processing for motion vector search, and adopting this as it is in a television receiver is a circuit. Difficult in terms of scale and cost. Further, the above-described motion prediction method for a television image has a problem in the accuracy of a motion vector in units of pixels, so that an accurate motion vector cannot be obtained, and image quality degradation may occur.
[0007]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION An object of the present invention is to provide an image signal system conversion device having high image quality and a small circuit scale.
[0008]
Another object of the present invention is to provide a multi-source compatible high-quality and low-cost television receiver.
[0009]
[Means for Solving the Problems]
According to an aspect of the present invention, a motion vector related to a predetermined motion correction error obtained by searching for a block-based motion vector based on an image signal and using a motion vector of the searched current block and adjacent blocks in units of mini-blocks. Is converted to a pixel unit motion vector in the mini-block, and an image signal format conversion device configured to convert the number of frames of the image signal by generating an interpolation frame of the image signal using the pixel unit motion vector, Achieved.
[0010]
According to another aspect of the present invention, an interlaced scanning image signal is converted into a progressive scanning image signal by a motion adaptive scanning line interpolation process. Next, signal processing for conversion of the number of motion correction frames is performed on the image signal converted into sequential scanning. For this reason, it is possible to detect a motion vector necessary for motion correction with higher accuracy than an interlaced scanning signal. Further, in order to greatly reduce the amount of calculation required for motion vector search generation, at least two stages of signal processing are performed: search for block-unit motion vectors and generation of pixel-unit motion vectors using these as reference vectors.
[0011]
Employing such signal processing can greatly reduce the amount of computation required for searching and generating motion vectors in pixel units necessary for motion correction processing. In addition, since the motion vector with the smallest motion correction error is assigned to the pixel unit motion vector in the mini-block, the image quality is deteriorated due to the inaccuracy of the motion vector, that is, an isolated image in which part of the image is replaced with an inappropriate image. It is possible to greatly suppress point degradation.
[0012]
According to another aspect of the present invention, the motion compensation frame interpolation process can be used for motion judder speed movements that are not smooth, and special movements such as vertical panning, horizontal panning, and character scrolling. Do it only for. In the scene change, the motion vector search and motion correction frame interpolation processing operations are stopped.
[0013]
As a result, it is possible to suppress the occurrence of image quality degradation in which the edge portion of the moving image inherent to the motion correction process flickers or the motion looks unnatural. In addition, it is possible to suppress the generation of a huge amount of calculation during a scene change.
[0014]
According to another aspect of the present invention, a television receiver searches for a block unit motion vector based on an input unit that inputs a plurality of different types of image signals, and the image signal from the input unit. A plurality of image format conversion units for converting the number of frames of the image signal by generating a pixel unit motion vector using the vector and generating an interpolation frame of the image signal using the pixel unit motion vector, and each image format A multiplexing unit that multiplexes output signals from the conversion unit and a display unit that displays an image based on the output signals of the multiplexing unit are provided.
[0015]
Thus, for example, PAL-NTSC television signal system conversion, PAL 50 Hz-60 Hz conversion, frame image 24 Hz film image-sequential scan conversion of frame frequency 60 Hz, television signal-computer (personal computer) image signal conversion, etc. It becomes possible to realize the frame rate conversion apparatus at an extremely low cost. Also, by using this system conversion device, a multi-source compatible high-quality and low-cost television receiver can be obtained.
[0016]
According to another aspect of the present invention, a motion information detection unit that detects image motion information from an image signal generation unit of a first image signal such as a PAL television signal or a PC image, A motion correction processing unit that converts the number of frames by motion compensation type frame interpolation processing using the motion vector of the first image signal, and the second image having a frame number higher than the number of frames of the first image signal. In the apparatus for converting to an image signal, the motion information detection unit is divided into a motion detection unit for detecting the presence or absence of motion for each pixel from a difference signal component between frames of the first image signal, and the first image signal is divided into blocks. The motion detection unit does not detect a motion vector for a block containing only a pixel whose motion is not detected by the motion detection unit, and detects a motion vector of the block using a block matching process. Constituting provided a motion vector detecting portion that performs.
[0017]
Preferably, the motion vector detection unit detects a correlation of motion between a block to be processed (abbreviated as current block) and a plurality of adjacent blocks by using a signal of the motion detection unit. A vector correction unit is provided that generates a corrected motion vector from the motion vectors of adjacent blocks having a high correlation of motion with the current block. The vector correcting unit divides a block in which motion is detected and a block in which motion is detected into a plurality of small (mini) blocks, and calculates a correction error due to motion vectors of adjacent blocks in units of mini blocks. And correcting the motion vector corresponding to the minimum value of the correction error in units of pixels or mini blocks assigned as the motion vector of the pixels in the mini block.
[0018]
The motion correction processing unit that converts the number of frames in the motion correction type frame interpolation processing is
(1) Based on the signal from the motion detection unit, motion correction processing is performed only on pixels in which motion has been detected. Even in a block for which a motion vector has been obtained, in a pixel-by-pixel process in motion correction in which the number of frames is converted, a pixel for which no motion is detected is processed with the motion vector set to zero.
[0019]
(2) The smoothness of the motion is impaired. The motion judder's conspicuous speed and specific motion vectors such as special motion such as up / down pan, horizontal pan and character scroll are detected and corrected for the signal of only the specific motion. Frame interpolation processing is performed on a pixel basis.
[0020]
As described above, since the motion detection unit performs block matching processing with a large amount of calculation only for blocks including pixels in which motion has been detected, it is possible to reduce the size of devices such as memories and arithmetic circuits. . In addition, since block matching processing is reduced, a vector correction unit that generates a corrected motion vector from the motion vector of an adjacent block having a high correlation between the current block and the motion can be provided, so that a highly accurate motion vector can be easily detected. Realized by processing. Furthermore, when performing correction frame interpolation processing, it is possible to perform processing for each pixel that moves in units of pixels using a signal indicating the presence or absence of motion of the motion detection unit, so that it is necessary for signal processing while maintaining image quality accuracy. The amount of computation processing, and hence the circuit scale, can be greatly reduced.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment of the present invention will be described with reference to FIGS. The present embodiment is an image signal format conversion device for converting an interlaced scanning input image signal into a progressive scanning image signal sequence S4 having a higher frame frequency.
[0022]
FIG. 1 is a block diagram of the present embodiment. In the figure, an IP conversion unit 1 receives an interlaced scanning input image signal S1 (luminance signal component and color difference signal component), performs interlaced-sequential scanning conversion, and sequentially scans a signal sequence S2 (luminance signal component and color difference). Signal component). The interlaced-sequential scan conversion is performed, for example, by performing motion adaptive interpolation processing on the luminance signal component and generating interpolated scanning line signals by interline interpolation processing. When the input image signal is a telecine image signal (a signal obtained by converting a film image such as a movie into a television signal format by 2-3 pull-down processing), a film mode interpolation process is performed (interlaces belonging to the same film frame). A signal sequence of a scanning image in the form of a film image is generated by generating an interpolated scanning line signal from the scanning signal.
[0023]
The motion correction frame number conversion unit 2 generates a signal sequence of an interpolated frame by motion correction processing, thereby sequentially scanning the signal sequence S2 obtained from the IP conversion unit 1 with a higher frame frequency. Image signal sequence S4 (luminance signal component and chrominance signal component) and output them. One frame delay unit 3, motion detection unit 4, block unit motion vector search unit 5, pixel unit motion vector generation unit 6, And a motion compensation interpolation frame generation unit 7.
[0024]
Here, the 1-frame delay unit 3 outputs the input signal sequence with a delay of 1 frame.
[0025]
The motion detection unit 4 subtracts the luminance signal component of the signal sequence S3 of the previous frame obtained from the 1-frame delay unit 3 from the luminance signal component of the signal sequence S2 of the current frame to extract a difference signal between one frame, This is binarized and the motion detection signals MI1 and MI2 are output. This configuration will be described later.
[0026]
The block unit motion vector search unit 5 detects a motion vector BV in block units (for example, 16 pixels × 16 lines or 8 pixels × 8 lines) as follows. First, it is determined that a block whose motion detection signal MI1 is all 0 is a still block, and 0 is output to the block unit motion vector BV. On the other hand, it is determined that a block including 1 in MI1 is a moving image block, and a block pair search for a minimum error is performed by block matching processing on the luminance signal components of signals S2 and S3, and a block unit motion vector BV is obtained. To detect. This configuration will be described later, and its operation will be described next.
[0027]
In the block unit motion vector search, the block unit motion vector BV is searched according to the signal processing flowchart shown in FIG.
[0028]
(1) In the first step, a block in which motion is not detected by a frame difference signal (still block) and a block in which motion is detected (moving image block) are classified.
[0029]
(2) In the second step, the still block does not search for a motion vector, and 0 is assigned to the motion vector BV. In addition, as shown in FIG. 18A, the moving image block first calculates a motion correction error with respect to a plurality of preset representative motion vectors (BVa, BVb, BVc, BVd,..., BVn in the figure). To do. That is, the signal fct (x, y) of the pixel in the current frame block and the signal fpr (x + BVx, y + BVy) obtained by moving the position of the pixel of the previous frame by the x component BVx and the y component BVy of the representative motion vector. The absolute values of the difference components are integrated to obtain a representative motion vector BV1 that minimizes the difference component. (3) In the third step, as shown in FIG. 18 (b), a search is performed by a block matching process on the motion vectors in the horizontal ± DX and vertical ± DY regions starting from the representative motion vector BV1, and the motion The one with the smallest correction error is detected as a motion vector BV in block units. The block unit motion vector search unit 5 operates as described above.
[0030]
The pixel unit motion vector generation unit 6 generates the pixel unit motion vector PV as follows. First, a pixel whose motion detection signal MI2 is 0 is assigned 0 to PV. On the other hand, for a pixel with MI2, the motion vector that minimizes the motion correction error is calculated in units of mini-blocks (for example, 2 pixels × 2 lines) using the motion vectors of the current block and the adjacent upper, lower, left, and right blocks. This is assigned to the motion vector of the pixel in the mini-block. This operation will be described later, and its operation will be described next.
[0031]
In the pixel unit motion vector generation, the pixel unit motion vector PV is generated by any one of the four types of signal processing flowcharts shown in FIGS. First, the first signal processing will be described with reference to FIGS. 19 and 20.
[0032]
(1) In the first step, the motion correction error in the current block is calculated from the motion vector BV in block units, and the size is compared with the threshold value TH.
[0033]
(2) In the second step, when the motion correction error is less than the threshold value TH, it is determined that the motion vector BV is accurate, and this motion vector BV is assigned to all the pixels in the block. On the other hand, if the motion correction error is greater than or equal to the threshold value TH, as shown in FIG. 20, the motion vector of the current block and the reference block adjacent thereto is used, and for each mini-block (for example, horizontal MX pixel × vertical MY line), A motion vector that minimizes the motion correction error is obtained in the horizontal MX + 2 and vertical MY + 2 calculation regions including the mini-block. That is, the difference component between the signal fct (x, y) of the pixel in the mini-block and the signal fpr (x + BVx, y + BVy) obtained by moving the position of the pixel of the previous frame by the x component BVx and y component BVy of the motion vector. Are obtained, and a motion vector that minimizes the absolute value is obtained as PV. The motion vector PV is assigned to the pixels in the mini-block.
[0034]
(3) In the third step, a motion vector 0 is assigned to a pixel whose motion detection signal MI2 is 0.
[0035]
In the second to fourth signal processing described below, the processing in the second step when the threshold value is equal to or higher than the threshold value TH is different from the first signal processing.
[0036]
In the second signal processing shown in FIGS. 21A and 21B, when the motion correction error is equal to or greater than the threshold value TH, the block matching process using the motion vector BV of the current block as a reference vector is performed. The motion vector PV1 for each block size (1/2 horizontal and vertical) is searched again. Next, using this PV1 as a reference vector, the motion vector PV2 for each sub-block SB2 (size of ½ of SB1 both horizontally and vertically) is searched again. Thereafter, this motion vector re-search process is performed up to the size of the mini-block, and a mini-block motion vector PV is generated. Then, this motion vector PV is assigned to a pixel in the mini-block.
[0037]
On the other hand, in the third signal processing shown in FIG. 22, when the motion correction error is equal to or greater than the threshold value TH, the block matching processing using the motion vector BV of the current block as a reference vector, the sub-block SB1 (both horizontal and vertical block sizes) is used. Search again for the motion vector PV1 every 1/2). Next, using the motion vector between PV1 obtained by re-search and the reference block adjacent to the current block shown in FIG. 20, the mini-block is included for each mini-block (for example, horizontal MX pixel × vertical MY line). A motion vector PV that minimizes a motion correction error in the horizontal MX + 2 and vertical MY + 2 calculation regions is obtained. The motion vector PV is assigned to the pixels in the mini-block.
[0038]
In the fourth signal processing shown in FIGS. 23A and 23B, the sub-block SB1 (block size horizontal and vertical ½) and the sub-block SB2 (horizontal and vertical ½ the size of SB1). In the following, block matching processing using BV as a reference vector is performed on the sub-block SBn having the mini-block size, and sub-block motion vectors PV1, PV2,. Next, for each mini-block, the one of PV1, PV2,..., PVn that minimizes the motion correction error is calculated and assigned to the motion vector of the pixel in the mini-block. The pixel unit motion vector generation unit 6 operates as described above.
[0039]
The motion correction interpolation frame generation unit 7 creates a corrected interpolation motion vector using the pixel unit motion vector PV, and moves the image positions of the current frame signal S2 and the previous frame signal S3 by the corrected interpolation motion vector. The signal generates an interpolated frame signal. Then, a progressively scanned image signal S4 having a frame frequency increased by a motion correction type frame number conversion process is obtained from this output. This specific configuration will also be described later.
[0040]
Hereinafter, the main block part in a present Example is demonstrated.
[0041]
FIG. 2 is a diagram illustrating a configuration example of the motion detection unit 4. The subtraction unit 8 performs a subtraction operation on the luminance signal components of the signal S2 of the current frame and the signal S3 of the previous frame, and extracts a difference signal component FD between one frame. If the signal level of the differential signal component FD is less than the set value ± Tha, the binary quantization unit 9-1 determines that it is a still region, and if it exceeds ± Tha, determines that it is a moving image region and detects 1 motion. The signal MI1 is output. The binary quantizing unit 9-2 outputs the motion detection signal MI2 of 1 when the signal level of the differential signal component FD is 0 when it is determined to be still, otherwise it is determined as a moving image.
[0042]
FIG. 3 is a diagram illustrating a configuration example of the block unit motion vector search unit 5. The static block determination unit 10 detects the presence / absence of 1 in the motion detection signal MI1 in block units (for example, 16 pixels × 16 lines or 8 pixels × 8 lines). When all the signals MI1 are 0, it is determined that the block is a still block and 0 is output to the signal BM.
[0043]
The control unit 11 controls the operations of the block matching first processing unit 12 and the block matching second processing unit 13 according to the signal BM. That is, in the still block whose signal BM is 0, the motion vector search operation is not performed and 0 is output to the block unit motion vector BV. Then, only the motion picture block whose signal BM is 1 performs the motion vector search operation described below.
[0044]
The block matching first processing unit 12 searches for a motion vector in the second step shown in FIG. In other words, using the luminance signal components of the signal S2 of the current frame and the signal S3 of the previous frame, a plurality of preset representative motion vectors (BVa, BVb,..., BVn shown in FIG. 18) are moved by block matching processing. A correction error is calculated, and the one with the smallest correction error is output to the representative motion vector BV1. It should be noted that the motion vectors of the block immediately before the end of the search can be used together with the plurality of representative motion vectors.
[0045]
The block matching second processing unit 13 searches for a motion vector in the third step shown in FIG. In other words, using the luminance signal components of the signal S2 of the current frame and the signal S3 of the previous frame, with respect to the motion vector determined from the representative motion vector BV1 as the starting point, the x component is in the range of ± DX and the y component is in the range of ± DY. The motion correction error is calculated by the block matching process, and the one that minimizes the error is output to the block unit motion vector BV.
[0046]
As a result, the search for the block unit motion vector can be limited to a moving image block, and a partial search using a representative motion vector is possible, so that the amount of signal processing required for the search can be greatly reduced.
[0047]
FIG. 4 is a diagram illustrating a first configuration example of the pixel unit motion vector generation unit 6. This is suitable for performing the signal processing according to FIGS. 19 and 20 described above.
[0048]
The correction error calculation unit 14 performs the process of the first step shown in FIG. That is, a motion correction error based on the block unit motion vector BV is calculated for the luminance signal components of the current frame signal S2 and the previous frame signal S3. When the error value is less than the threshold value TH, 0 is output to the signal PM, and when it is equal to or greater than the threshold value TH, 1 is output.
[0049]
The control unit 15 generates control signals PC1 and PC2 necessary for signal processing in the second and third steps shown in FIG. 19 based on the signal PM and the motion detection signal MI2.
[0050]
The correction error calculation units 17-1,..., 17-N perform signal processing in the case where it is equal to or greater than the threshold value of the second step in FIG. That is, when the control signal PC1 indicates a threshold value or more, the motion vector V0 of the current block generated by the reference motion vector generator 16 and the motion vectors V1,..., VN corresponding to the adjacent blocks shown in FIG. For each block (eg, 2 pixels × 2 lines of horizontal MX = 2 and vertical MY = 2), motion correction errors ER0 and ER1 in the calculation area of horizontal 4 (MX + 2) pixels and vertical 4 (MY + 2) lines are included. ... ERN is calculated. The calculation of the motion correction error is realized by the calculation shown in (Equation 1) for either the luminance signal component of the current frame signal S2 and the previous frame signal S3, or the luminance signal component and the color difference signal component. it can.
[0051]
[Expression 1]

[0052]
In (Expression 1), S2 (x, y) is a pixel signal of the current frame in the calculation region, S3 (VN) is a pixel signal of the previous frame whose position is moved by the motion vector VN, and abs {} is absolute The value, Σ is the sum of the pixels in the calculation area, VNx is the x component of the motion vector VN, and VNy is the y component.
[0053]
The pixel motion vector setting unit 18 performs signal processing of less than the threshold of the second step and third step of FIG. That is, when the control signal PC2 indicates less than the threshold value, the motion vector V0 of the current block is output to the pixel unit motion vector PV. On the other hand, when the value is greater than or equal to the threshold value, the motion vector having the minimum value among the motion correction errors ER0, ER1,..., ERN is output as the motion vector PV of the pixel in each mini-block.
[0054]
When the motion detection signal MI2 indicates a pixel of 0, the control signal PC2 forcibly outputs 0 as the pixel unit motion vector PV.
[0055]
FIG. 5 is a diagram illustrating a second configuration example of the pixel unit motion vector generation unit. Then, a pixel-based motion vector is generated by the signal processing shown in FIGS. 21 (a) and 21 (b).
[0056]
The correction error calculation unit 14 is the same as that shown in FIG. 4 and performs the first step shown in FIG. 21A. If the value of the block-unit motion correction error is less than the threshold TH, the correction error calculation unit 14 outputs the signal PM. 1 is output when 0 or more than the threshold value TH.
[0057]
Based on the signal PM and the motion detection signal MI2, the control unit 15 generates the control signals PC3 and PC2 necessary for the signal processing in the second and third steps shown in FIG.
[0058]
The re-search first processing unit 19, the re-search second processing unit 20, and the re-search third processing unit 21 perform the signal processing of the second step in FIG. That is, when the control signal PC3 indicates a threshold value or more, a motion vector re-search process is performed. First, as shown in FIG. 21 (b), the re-search first processing unit 19 uses the motion vector BV as a reference vector for each sub-block SB1 whose block size is reduced to a half size both horizontally and vertically. A matching process is performed, and the re-searched motion vector PV1 in units of SB1 is output. Next, the re-search second processing unit 20 performs block matching processing using the motion vector PV1 as a reference vector for each sub-block SB2 obtained by reducing the sub-block SB1 to ½ both horizontally and vertically. The motion vector PV2 is output. The re-search third processing unit 21 performs block matching processing using the motion vector PV2 as a reference vector for each sub-block SBN having a mini-block size obtained by reducing the sub-block SB2 to 1 / n both horizontally and vertically, and re-searches the SBN. A unit motion vector, that is, a mini-block unit motion vector PV3 is output. On the other hand, when the control signal PC3 indicates less than the threshold, the re-search first processing unit 19, the re-search second processing unit 20, and the re-search third processing unit 21 stop the operation of the re-search process, and the motion vector PV3 To output the motion vector BV of the current block.
[0059]
The pixel motion vector setting unit 22 performs the signal processing of the third step in FIG. That is, when the motion detection signal MI2 indicates a pixel of 0, the control signal PC2 forcibly outputs 0 as the pixel unit motion vector PV. On the other hand, when the motion detection signal MI2 indicates one pixel, the control signal PC2 outputs PV3 as the pixel unit motion vector PV.
[0060]
FIG. 6 is a diagram illustrating a third configuration example of the pixel unit motion vector generation unit. This is suitable for performing the signal processing according to FIG. 22 described above, and is realized by adding a re-search processing unit 23 to the configuration of FIG.
[0061]
When the control signal PC4 indicates a threshold value or more, the re-search processing unit 23 performs block matching using the motion vector BV of the current block as a reference vector for each sub-block SB1 whose block size is reduced to 1/2 both horizontally and vertically. Processing is performed, and the re-searched motion vector PV1 of SB1 unit is output. On the other hand, when PC4 indicates less than the threshold, the re-search operation is stopped and the motion vector BV of the current block is output. Then, a motion vector PV1 in sub-block SB1 unit used as a reference vector in the signal processing equal to or higher than the threshold value in the second step in FIG. 22 is generated.
[0062]
The subsequent operation is the same as that shown in FIG.
[0063]
FIG. 7 is a diagram illustrating a fourth configuration example of the pixel unit motion vector generation unit. The pixel unit motion vector is generated by the signal processing illustrated in FIGS. 23A and 23B.
[0064]
The correction error calculation unit 14 is the same as that shown in FIG. 4 and performs the first step process shown in FIG. 23A. If the value of the block-unit motion correction error is less than the threshold value TH, the correction error calculation unit 14 outputs the signal PM. 1 is output when 0 or more than the threshold value TH.
[0065]
Based on the signal PM and the motion detection signal MI2, the control unit 15 generates the control signals PC5 and PC2 necessary for the signal processing in the second and third steps shown in FIG.
[0066]
The re-search first processing unit 24, the re-search second processing unit 25, and the re-search third processing unit 26 perform the signal processing of the second step in FIG. That is, when the control signal PC5 indicates a threshold value or more, a motion vector re-search process is performed. First, as shown in FIG. 23 (b), the re-search first processing unit 24 performs a block operation using the motion vector BV as a reference vector for each sub-block SB1 whose block size is reduced to a half size both horizontally and vertically. A matching process is performed, and the re-searched motion vector PV1 in units of SB1 is output. Next, the re-search second processing unit 25 performs block matching processing using the motion vector BV as a reference vector for each sub-block SB2 whose block size is reduced to ¼ both horizontally and vertically, and re-searches the unit of SB2 The motion vector PV2 is output. The re-search third processing unit 26 performs block matching processing using the motion vector BV as a reference vector for each sub-block SBN having a mini-block size in which the block size is reduced to 1 / n both horizontally and vertically, and re-searched SBN units Motion vector, that is, a motion vector PV3 in units of mini-blocks is output. On the other hand, when the control signal PC5 indicates less than the threshold value, the re-search first processing unit 24, the re-search second processing unit 25, and the re-search third processing unit 26 stop the operation of the re-search process, and PV1, PV2 , PV3 outputs the motion vector BV of the current block.
[0067]
The pixel motion vector setting unit 27 performs signal processing of less than the threshold of the second step and third step of FIG. That is, when the control signal PC2 indicates less than the threshold value, the motion vector PV1 of the current block is output to the pixel unit motion vector PV. On the other hand, when the value is greater than or equal to the threshold value, a motion vector having a minimum motion correction error among PV1, PV2, and PV3 is output as a motion vector of a pixel in each mini-block.
[0068]
When the motion detection signal MI2 indicates a pixel of 0, the control signal PC2 forcibly outputs 0 as the pixel unit motion vector PV.
[0069]
FIG. 8 is a diagram illustrating a first configuration example of the motion compensation interpolation frame generation unit 7, and FIGS. 9A to 9C are diagrams for explaining the operation thereof.
[0070]
The frame order control unit 28 generates corrected interpolation motion vectors Vct and Vpr necessary for the motion correction process from the pixel unit motion vector PV. The outline of this operation is shown in FIGS. 9A and 9B, taking as an example the case where the number of frames is converted from a signal with a frame frequency of 50 Hz to a signal with a frame frequency of 60 Hz. The progressive scanning signal with a frame frequency of 50 Hz generates an interpolated frame by correction type signal processing based on the motion vector PV as shown in FIG. 6 is converted into a progressive scanning signal having a frame frequency of 60 Hz. At this time, the corrected interpolation motion vector needs to match the frame position to be interpolated. Therefore, as shown in the figure, coefficient values ka and kb to which the coefficient of weight is applied to the motion vector signal PV are changed, and corrected interpolation motion vectors Vpr and Vct are generated by the calculation shown in (Equation 2).
[0071]
[Expression 2]

[0072]
In other words, interpolation frames with a frame order of 2 are Vpr = PV * 5/6, Vct = −PV * 1/6 (ka = 5, kb = 1), and 3 are Vpr = PV * 4 / 6, Vct = −PV * 2/6 (ka = 4, kb = 2)... To generate coefficient values ka and kb, and generate a corrected interpolated motion vector having no positional deviation in the time direction. As a result, frame number conversion without fluctuation in the time direction is realized.
[0073]
The motion correction signal generation unit 29 generates a motion correction signal Sct using the current frame signal S2 and the corrected interpolated motion vector Vct. In addition, the motion correction signal generation unit 30 generates a motion correction signal Spr using the signal S3 of the previous frame and the corrected interpolation motion vector Vpr. An outline of this operation is shown in FIG. The signal at the point A (x, y) in the interpolation frame is obtained by moving the point A (x, y) by the corrected interpolation motion vector Vpr (horizontal component Vprx, vertical component Vtry) in the signal S3 of the previous frame. The signal at the point A ′ (x1, y1) = (x + Vprx, y + Vtry), and in the current frame signal S2, the point A (x, y) is the corrected interpolation motion vector Vct (horizontal component Vctx, vertical component Vcty) It corresponds to the signal at the position of the moved point A ″ (x2, y2) = (x−Vctx, y−Vcty). Accordingly, the motion correction signals Spr and Sct are generated by the following (formula 3).
[0074]
[Equation 3]

[0075]
This signal processing can be realized by controlling the read operation of the memory circuit built in the motion correction signal generation unit. In other words, an address is generated by shifting the address for reading by the position of the corrected interpolation motion vectors Vpr and Vct, and the pixel signals corresponding to the points A ′ and A ″ are read at this address.
[0076]
The adder 31 averages the motion correction signals Spr and Sct of the two, and obtains an image signal S4 of sequential scanning whose frame frequency is increased by converting the number of frames for motion correction.
[0077]
FIG. 10 is a diagram illustrating a second configuration example of the motion compensation interpolation frame generation unit. This is a motion compensation frame interpolation process only when the motion judder obstruction is noticeable at a speed or when it is a special movement such as horizontal panning, up / down panning, or character scrolling.
[0078]
The frame order control unit 28, the motion correction signal generation units 29 and 30, and the addition unit 31 in FIG. 8 perform the same operation as in FIG. 8 and obtain a signal Smc subjected to motion correction frame interpolation processing at the output of the addition unit 31.
[0079]
Based on the pixel unit motion vector PV, the motion speed detection unit 32 detects a motion at a speed at which motion judder interference is conspicuous, or a special motion such as horizontal pan, up / down pan, and character scroll.
[0080]
For example, the motion judder obstruction is known to be particularly noticeable in the case of a movement that can follow the line of sight up to about 1 second / screen width and 1 second / screen height. Therefore, the motion speed detection unit determines the speed component of the motion vector PV using a speed corresponding to about 1 second / screen width, 1 second / screen height as a threshold, and is 1 when the speed is less than the threshold, and 0 when the speed is higher than the threshold. This detection can be performed by the first operation of outputting the signal SL.
[0081]
In addition, the horizontal and vertical pans move the entire screen at a uniform speed. Therefore, the motion speed detection unit measures the size and direction of the pixel unit motion vector PV ≠ 0 over the entire screen area, and outputs 1 to the signal SL in all the screen areas only when it takes almost the same value. This detection can be performed by the operation 2.
[0082]
On the other hand, in character scrolling or the like, the shape of the motion region is a band shape, and the motion vectors in this region have almost the same value. Accordingly, the motion speed detection unit detects a band-like region in which the size and direction of the pixel unit motion vector PV ≠ 0 are substantially the same, and outputs this 1 in the signal SL only in this region. Can do.
[0083]
The motion speed detection unit can be realized in various operation forms such as one of the first, second, and third operations, or a combination of these operations.
[0084]
The switch unit 33 selects the signal S2 of the current frame when the signal SL is 1, and selects the signal Smc when the signal SL is 0. Then, a sequential scanning image signal S4 obtained by interpolating a motion correction frame only in a motion of a speed at which motion judder disturbance is conspicuous or a special motion region such as horizontal panning, up / down panning, and character scrolling is obtained. .
[0085]
As described above, according to the present embodiment, it is possible to realize a high-quality image signal system conversion apparatus that requires a small amount of calculation for search and generation of motion vectors. And a remarkable effect is obtained for cost reduction.
[0086]
Next, a second embodiment of the present invention will be described with reference to the block diagram of FIG. The present embodiment is suitable for performing an operation of stopping the signal processing of the motion correction process in the scene change area.
[0087]
The IP conversion unit 1, the frame delay unit 3, the motion detection unit 4, the block unit motion vector search unit 5, and the pixel unit motion vector generation unit 6 shown in FIG. 1 are the same as those shown in FIG.
[0088]
The scene change detection unit 34 performs an operation of detecting a region where a scene change has occurred based on the generation form of the inter-frame difference signal component in one frame period. An example of this configuration is shown in FIG. The subtraction unit 8 performs a subtraction operation on the luminance signal components of the signal S2 of the current frame and the signal S3 of the previous frame, and extracts a difference component FD between one frame. In general, in the scene change region, the content of the image is switched, so that the signal level of the difference component FD has a relatively large value. Therefore, the binary quantization unit 36 binary-quantizes the signal FD for each pixel with a relatively high level threshold value ± Thb. Then, 0 is output to the signal QS when the pixel is less than the threshold value ± Thb, and 1 is output when the pixel exceeds the threshold value. The 1-frame accumulating unit 37 measures the number of pixels whose signal QS is 1 in one frame period, and outputs the accumulated value AQ in one frame period. The determination unit 38 has a cumulative value AQ of more than half the number of pixels of the entire screen in order to avoid erroneous operation of erroneously detecting a scene change as the movement of the horizontal pan and the vertical pan moving at a uniform speed throughout the screen. Further, when the occurrence is limited to one frame period, it is determined as a scene change area, and 1 is output to the signal SC over one frame period. Otherwise, 0 is output.
[0089]
The block unit motion vector search unit 5 and the pixel unit motion vector generation unit 6 preferentially stop the motion vector search and generation operations only during the period when the signal SC is 1. When the signal SC is 0, the same operation as in FIG. 1 is performed.
[0090]
In addition, the motion compensation interpolation frame generation unit 35 preferentially selects the signal S2 of the current frame and outputs it to S4 during the period when the signal SC is 1. When the signal SC is 0, the same operation as that of the motion compensation interpolation frame generation unit 7 in FIG. 1 is performed.
[0091]
As described above, according to the present embodiment, it is possible to avoid the generation of a huge amount of calculation for motion vector search and generation in the scene change area. Further, it is possible to realize a high-quality image signal system conversion device with a smaller calculation amount, and a remarkable effect can be obtained in cost reduction.
[0092]
Next, a third embodiment of the present invention will be described with reference to a block diagram shown in FIG. This embodiment is suitable for performing both frame rate conversion processing for motion correction and reduction conversion for the number of scanning lines of an image signal.
[0093]
The interlaced scanning input image signal S1 (luminance signal component and color difference signal component) is input to the IP converter 1 to perform interlaced-sequential scanning conversion. For example, a luminance signal component is generated by motion adaptive interpolation processing, and a color difference signal is generated by interpolation processing between lines to generate an interpolated scanning line signal, and a sequential scanning signal series S2 (luminance signal component and color difference signal component) is obtained as an output. . When the input image signal is a telecine image signal (a signal obtained by converting a film image such as a movie into a television signal format by 2-3 pull-down processing), a film mode interpolation process (interlaced scanning signal belonging to the same film frame) (Interpolated scanning line signal is generated in step S3) to generate a sequential scanning signal sequence in the form of a film image.
[0094]
The scaling processing unit 39 performs a reduction conversion process of N / M times the number of scanning lines in a vertical compression signal process using a vertical MN conversion process (M> N) of linear interpolation characteristics. For example, a signal with 625 scanning lines in the PAL system is converted into a signal with 525 scanning lines in the NTSC system. Then, a sequentially scanned image signal S10 with a reduced number of scanning lines is output. In addition, since this structure can be easily implement | achieved by a prior art, description of a specific structural example etc. is abbreviate | omitted.
[0095]
The motion correction frame number conversion unit 2 has the same configuration and operation as those shown in FIG. Then, using the signal S10 of the current frame and the signal S11 of the previous frame delayed by one frame period by the one-frame delay unit 3, signal processing for frame interpolation for motion compensation is performed, and frame rate conversion and output are performed. A sequentially scanned image signal S4 subjected to scanning line reduction conversion is obtained.
[0096]
As described above, according to the present embodiment, an image signal format conversion apparatus, for example, a PAL format television, which performs both frame rate conversion processing for motion correction and reduction conversion of the number of scanning lines of an image signal. An apparatus for converting a signal into an NTSC progressive scanning image signal can be realized at a very low cost.
[0097]
Next, a fourth embodiment of the present invention will be described with reference to a block diagram shown in FIG. This embodiment is also suitable for performing both frame rate conversion processing for motion correction and reduction conversion of the number of scanning lines of an image signal. In this embodiment, as in the embodiment shown in FIG. 13, the IP conversion unit 1 performs interlaced-sequential scan conversion, and the scaling processing unit 39 uses N / M times the number of scanning lines by vertical compression signal processing. Perform reduction conversion processing.
[0098]
The configuration and operation of the motion correction frame number conversion unit 2 are exactly the same as those shown in FIG. Then, using the signal S10 of the current frame and the signal S11 of the previous frame delayed by one frame period by the one-frame delay unit 3, signal processing for frame interpolation for motion compensation is performed, and frame rate conversion and output are performed. A sequentially scanned image signal S4 subjected to scanning line reduction conversion is obtained.
[0099]
As described above, according to the present embodiment, an image signal format conversion apparatus, for example, a PAL format television, which performs both frame rate conversion processing for motion correction and reduction conversion of the number of scanning lines of an image signal. An apparatus for converting a signal into an NTSC progressive scanning image signal can be realized at a very low cost.
[0100]
Next, a fifth embodiment of the present invention will be described with reference to a block diagram shown in FIG. This embodiment is suitable for performing both frame rate conversion processing for motion correction and enlargement conversion of the number of scanning lines of an image signal. In the figure, the IP conversion unit 1 and the motion correction frame number conversion unit 2 have the same configuration and operation as those shown in FIG.
[0101]
The progressively scanned image signal S4 obtained by converting the number of frames for motion correction is subjected to vertical enlargement signal processing by vertical MN conversion processing (M <N) of linear interpolation characteristics in the scaling processing unit 39, and N / M-fold enlargement conversion processing is performed. For example, a signal with 525 scanning lines of the NTSC system is converted into a signal with 720 scanning lines corresponding to SVGA of a personal computer. Then, an image signal S5 for sequential scanning with an increased number of scanning lines is output. In addition, since this structure can be easily implement | achieved by a prior art, description of a specific structural example etc. is abbreviate | omitted.
[0102]
As described above, according to the present embodiment, an image signal format conversion apparatus, for example, an NTSC system television, which performs both frame rate conversion processing for motion correction and enlargement conversion of the number of scanning lines of an image signal. An apparatus for converting a signal into an image signal for progressive scanning with the number of scanning lines corresponding to SVGA of a personal computer can be realized at a very low cost.
[0103]
Next, a sixth embodiment of the present invention will be described with reference to a block diagram shown in FIG. This embodiment is suitable for performing both frame rate conversion processing for motion correction and enlargement conversion of the number of scanning lines of an image signal.
[0104]
In the figure, the IP conversion unit 1 and the motion correction frame number conversion unit 2 are identical in configuration and operation to those shown in FIG.
[0105]
The progressively scanned image signal S4 obtained by converting the number of frames for motion correction is subjected to vertical enlargement signal processing by vertical MN conversion processing (M <N) of linear interpolation characteristics in the scaling processing unit 39, and N / M-fold enlargement conversion processing is performed. For example, a signal with 525 scanning lines of the NTSC system is converted into a signal with 720 scanning lines corresponding to SVGA of a personal computer. Then, an image signal S5 for sequential scanning with an increased number of scanning lines is output. In addition, since this structure can be easily implement | achieved by a prior art, description of a specific structural example etc. is abbreviate | omitted.
[0106]
The above-mentioned technical means of the present invention realizes motion correction frame number conversion with a small circuit scale, low cost, and high image quality that can be incorporated in a television receiver, and is compatible with multi-source and multi-display. A television receiver having a function compatible with multi-window display can be realized.
[0107]
FIG. 24 is an overall block diagram showing a television receiver according to another embodiment of the present invention. In this embodiment, the display unit is suitable for CRT, PDP, LCD with a scanning line number of 625, frame frequency of 60 Hz, sequential scanning, or scanning line number of 1080 (1125), field frequency of 60 Hz, and interlaced scanning. Is.
[0108]
Broadcast waves TV1, TV2,..., TVN (for example, current TV system NTSC signals, PAL signals) are subjected to predetermined demodulation processing by the TV demodulation units 51-1,. Demodulate into components.
[0109]
The digital broadcast wave TVD is subjected to predetermined digital demodulation and decoding processing by the IRD 52, and the luminance signal component and color difference of SD (signal of the same image format as the current TV system) or HD (signal of the image format equivalent to HDTV) Demodulate to signal component.
The image signal of the personal computer (for example, RGB three primary color signals) is subjected to color space conversion signal processing by the color conversion unit 53 and converted into a luminance signal component and a color difference signal component.
[0110]
The above input signals are input to the image format converters 60-1,..., 60-M via the signal bus 59. The IP conversion unit 1 converts the interlaced scanning signal into a sequential scanning signal by, for example, motion adaptive scanning line interpolation signal processing. The motion correction frame number conversion unit 2 converts a signal having a frame frequency of less than 60 Hz (for example, 50 Hz for the PAL system or 24 Hz for a film image) into a signal having a frame frequency of 60 Hz by frame interpolation processing for motion correction. Also, the scaling processing unit 39 converts the number of scanning lines (if the display unit has 625 scanning lines, the signal of 525 scanning lines of the NTSC system is converted to 625 signals by the 5-6 conversion processing of the number of scanning lines. Conversion to a signal), enlargement / reduction processing of an image size according to various display forms such as multi-window, two-screen moving image, PIP (Picture in picture), POP (Picture out picture).
[0111]
The image quality improvement units 61-1 to 61-M perform luminance gradation correction, color space conversion that matches the color space characteristics of the display unit, and inverse gamma correction (when the display unit has linear characteristics such as PDP and LCD). Perform signal processing.
[0112]
The MPX unit 62 is a multiplexing unit that multiplexes signals and integrates and combines the output signals from the image quality improvement units to generate an image signal in a predetermined display form. Then, the image is reproduced on the display unit 55.
[0113]
Information on the display form selected and designated by the viewer is input to the control unit 58 via the remote controller 56 and the remote control signal receiving unit 57. Then, the control unit 58 generates control signals necessary for the operation of each unit according to this information and outputs the control signals to the controlled unit 54.
[0114]
In this block configuration diagram, the image format conversion units 60-1 to 60-M which are the main points of the present invention include an IP conversion unit 1, a motion correction frame number conversion unit 2, and a scaling processing unit 39. The above-mentioned embodiment can be used. In addition, since each block except these can be easily configured by the conventional technique, description thereof is omitted here.
[0115]
According to the present embodiment, the amount of calculation required for the search and generation of a motion vector necessary for performing frame rate conversion for motion correction can be reduced to several tenths compared with the conventional method, and the circuit scale is extremely large. Can be small. For this reason, a television receiver having a built-in function of frame rate conversion for motion correction can be realized at a relatively low cost. In addition, a remarkable effect can be obtained in improving the image quality and functionality of TV images.
[0116]
Next, a television receiver according to another embodiment of the present invention will be described with reference to an overall block diagram shown in FIG. This embodiment is suitable for a CRT, PDP, and LCD in which the display unit has a scanning line number of 525, a frame frequency of 60 Hz, and a sequential scanning form. The difference from the embodiment shown in FIG. 24 is that the order of the scaling process and the motion correction frame number conversion process in the signal processing in the image format conversion unit is reversed. Therefore, the motion correction frame number conversion will be described below.
[0117]
In the image format conversion units 62-1,..., 62-M, first, the IP conversion unit 1 converts the interlaced scanning signal into a sequential scanning signal. In other words, the interlaced scanning image signal (luminance signal component and chrominance signal component) generates the interpolated scanning line signal for the motion signal adaptive interpolation processing for the luminance signal component and interline processing for the chrominance signal component, and sequentially scans. Signal series (luminance signal component and color difference signal component). When the input image signal is a telecine image signal (a signal obtained by converting a film image such as a movie into a television signal format by 22-3 pull-down processing), the film mode interpolation processing (interlaced scanning belonging to the same film frame) is performed. The signal of the interpolated scanning line is generated by the signal) to generate a signal sequence of sequential scanning in the form of a film image.
[0118]
Next, the scaling processing unit 39 performs reduction conversion of the number of scanning lines and enlargement / reduction processing of the image size. For example, a PAL signal having 625 scanning lines is subjected to 6-5 conversion processing for the number of scanning lines, and converted to a signal having 525 scanning lines of the NTSC system. In addition, image size enlargement / reduction processing is performed according to various display forms such as multi-window, two-screen video, PIP (Picture in picture), and POP (Picture out picture).
[0119]
The motion correction frame number conversion unit 2 converts a signal having a frame frequency of less than 60 Hz (for example, 50 Hz for the PAL system or 24 Hz for a film image) into a signal having a frame frequency of 60 Hz by frame interpolation processing for motion correction. At this time, in the preceding scaling process, the signal of 625 scanning lines in the PAL method is converted into a signal of 525 scanning lines in which the number of scanning lines is reduced to 5/6. Therefore, the amount of calculation for searching for a motion vector necessary for converting the number of frames for motion correction can be reduced to 5/6 in the case of 625 scanning lines. Note that the specific configuration of the motion correction frame number conversion unit 2 is the same as that in the above-described embodiment, and a description thereof will be omitted.
[0120]
As described above, according to the present embodiment, the amount of calculation required for searching and generating a motion vector necessary for performing frame rate conversion for motion correction is reduced to a few tenths compared with the conventional method. The circuit scale can be made extremely small. For this reason, a television receiver having a built-in function of frame rate conversion for motion correction can be realized at a relatively low cost. In addition, a remarkable effect can be obtained in improving the image quality and functionality of TV images.
[0121]
Next, a television receiver according to another embodiment of the present invention will be described with reference to the overall block diagram shown in FIG. In the present embodiment, MIX units 63-1 to 63-K, which are signal mixing units, are added to the embodiment of FIG. 24 and realized by a smaller number of image format conversion units 60-1 to 60-M ′. This is suitable for further cost reduction.
[0122]
MIX units 63-1,..., 63-K receive 2-channel TV signals of the same system among the image signals demodulated by the TV demodulation units 51-1,. Then, in the case of a two-screen video or PIP using a TV signal with the same display format, a synthesis process of a two-channel TV signal is performed. For example, in the case of a two-screen moving image, the signal processing of the operation of arranging the signal of one channel at the position of the left half of the screen and the signal of the other channel at the position of the right half of the screen is performed and output. In PIP, the signal processing of the operation of arranging the signal of one channel at the position of the main screen and the signal of the other channel at the position of the child screen is performed and output. On the other hand, in display modes other than the above, the signal of any one channel used for display is output.
[0123]
The image format conversion units 60-1,..., 60-M ′ perform the same processing as in FIG. However, in the case of a two-screen moving image or PIP display form using the same TV signal, the scaling processing unit has already converted to the required signal form using the outputs of the MIX units 63-1 to 63-K. The signal processing for enlargement / reduction is not performed.
As described above, in this embodiment, in the two-screen moving image or PIP display mode, the conversion process is performed by the MIX unit provided in the preceding stage of the image format conversion unit. For this reason, the number of image format conversion units to be used can be reduced, and a lower-cost television receiver can be realized.
[0124]
Next, a television receiver according to another embodiment of the present invention will be described with reference to the overall block diagram shown in FIG. In the present embodiment, MIX units 63-1 to 63-K are added to the embodiment of FIG. 25 to reduce the number of image format conversion units 62-1 to 62-M ′, thereby further reducing the cost. Is preferred. The operations of the MIX units 63-1 to 63-K are the same as those shown in FIG. Other configurations and operations are the same as those in FIG.
[0125]
As described above, according to these embodiments, it is possible to obtain a remarkable effect in improving the image quality and functionality of a television image, and the amount of calculation required for motion vector search and generation in motion correction signal processing. As compared with the conventional method, and the circuit scale can be greatly reduced. Therefore, it is possible to realize a high-quality and low-cost television receiver having functions for multi-source, multi-display, and multi-window display.
[0126]
Here, the reduction rate of the calculation amount required for the search and generation of motion vectors in the motion correction signal processing will be obtained.
[0127]
First, the calculation amount reduction rate of the block-by-block motion vector search process can be obtained as follows.
[0128]
When the search area is horizontal ± DX pixels and vertical ± DY lines, the block matching process per block requires (2DX + 1) (2DY + 1) times in the full search method. On the other hand, the block matching process per moving image block is (DX / 2 + 1) (DY / 2 + 1) times in the second step and (DX / 4 + 1) (DY / 4 + 1) times in the third step. Here, assuming that the occurrence probability of a moving image block is Mb (0 ≦ Mb ≦ 1), DX = 16, DY = 16, and the calculation amount reduction rate of the block search is Kb, Kb is given by (Expression 4).
[0129]
[Expression 4]

[0130]
Therefore, in the search in block units, even when one screen is the worst of all moving image blocks (Mb = 1), the search can be performed with a calculation amount of about 10% as compared with the full search method.
[0131]
Next, the calculation amount reduction rate of the pixel-by-pixel motion vector search process can be obtained as follows.
[0132]
In general, the motion vector BV of the current block is used as a reference vector, and a re-search is performed in a range of about horizontal ± DX / 4 pixels and vertical direction ± DY / 4 lines in which the search area is reduced in units of pixels to obtain a final motion. A method of generating a vector is adopted. If the block size is horizontal BX pixels and vertical BY lines, the re-search process required in this case requires (DX / 2 + 1) (DY / 2 + 1) · BX · BY search processes. On the other hand, for the block having the threshold value TH or higher, (number of reference vectors 9) · (three types of luminance 1 system and color difference 2 system) · (BX / 2) · (BY / 2) times of re-searching is performed. Here, if the occurrence probability of a block equal to or higher than the threshold TH is Mp (0 ≦ Mp ≦ 1), DX = DY = 16, BX = BY = 16, and the calculation amount reduction rate of pixel search is Kp, Kp is ( It is given by equation 5).
[0133]
[Equation 5]

[0134]
Therefore, even in the worst case (Mp = 1) in which all of one screen is a moving image block, the search can be performed with a calculation amount of about 8% compared to the all-pixel search method.
[0135]
Since the motion vector is generated in two stages, the above-described search in block units and the re-search in pixel units, if the overall calculation amount reduction rate is Kmv, Kmv can be expressed by (Equation 6). Can do.
[0136]
[Formula 6]

[0137]
Therefore, even in the worst case (Mb = Mp = 1), the calculation amount required for the search and generation of motion vectors can be reduced by two digits or more as a whole. As a result, the scale of the circuit that performs the signal processing for motion correction can be extremely reduced.
[0138]
According to the above-described embodiment, it is possible to obtain an image signal system conversion device with high image quality and a small circuit scale. Further, by using this system conversion device, a multi-source compatible high-quality and low-cost television receiver can be realized.
[0139]
FIG. 28 is a block diagram showing a configuration of a motion correction type image signal converting apparatus according to another embodiment of the present invention. In this embodiment, a PAL television (hereinafter abbreviated as TV) signal is converted into an NTSC progressive scanning TV signal.
[0140]
The demodulated signal S71 (luminance signal component and chrominance signal component) of the PAL system TV signal is input to the IP converter 71, and the interlaced scanning signal is converted into a sequential scanning signal (hereinafter abbreviated as interlaced → sequential scanning conversion). To do. That is, a luminance signal component is generated by motion adaptive interpolation processing, and a color difference signal is generated by interpolation processing between lines to generate an interpolated scanning line signal, and a sequential scanning signal sequence S2 having a frame frequency of 50 Hz is obtained as an output.
[0141]
The vertical 6-5 converter 72 converts the number of scanning lines in the 6-5 conversion process and generates a signal series S73 (however, the frame frequency is 50 Hz) having the number of scanning lines equivalent to the NTSC TV signal. That is, as shown in FIG. 29, an input / output characteristic is calculated with a two-point linear interpolation characteristic for a set of six scanning lines a, b, c, d, e, and f, and five scans are performed. Generate signals for lines v, w, x, y, z. The IP conversion unit 71 and the vertical 6-5 conversion unit 72 constitute an image signal generation unit of an image signal whose frame frequency is converted, and a conventionally known technique can be used.
[0142]
The signal S73 and the signal S74 delayed by one frame period in the frame memory 73 (hereinafter referred to as the signal of the previous frame) are input to the motion detection unit 74, the motion vector detection unit 75, and the motion correction processing unit 76.
[0143]
The motion detection unit 74 extracts, for each pixel, a difference signal component for one frame from the luminance signal components of the signals S73 and S74, performs binarization and smoothing processing, and performs a motion detection signal FD ( A binary signal of “0” without motion and “1” with motion) is output. The specific configuration of the motion detection unit 74 will be described later.
[0144]
The motion vector detection unit 75 detects a motion vector in block units (for example, 16 pixels × 16 lines or 8 pixels × 8 lines) by block matching processing. That is, a block in which the motion detection signal FD of all the pixels in the block is “0” is determined to be still, and 0 is output to the motion vector signal V. On the other hand, the block including the pixel “1” in the motion detection signal FD is determined to be a moving image, and a block pair search is performed for the luminance signal components of the signals S73 and S74 to minimize the error by block matching processing. Is output as a motion vector signal V. A specific configuration of the motion vector detection unit 75 will also be described later.
[0145]
The motion correction processing unit 76 performs motion correction type signal processing on the pixel whose motion detection signal FD is “1”. That is, a corrected interpolated motion vector is created from the motion vector V, and an interpolated frame signal is generated using a signal obtained by moving the image positions of the current frame signal S73 and the previous frame signal S74 by the corrected interpolated motion vector. On the other hand, for a pixel whose motion detection signal FD is “0”, an interpolated frame signal is generated using the average value of the current frame signal and the previous frame signal or the current frame signal. An NTSC progressive scanning signal S75 having a frame frequency of 60 Hz obtained by performing motion compensation type frame number conversion processing on this output is obtained. The configuration of the motion correction processing unit 76 will be described later.
[0146]
Hereinafter, the configuration and operation of the main block unit in the present embodiment will be described.
FIG. 30 is a configuration example diagram of the motion detection unit 74. The subtractor 77 performs a subtraction operation on the luminance signal components of the current frame signal S73 and the previous frame signal S74 of sequential scanning to obtain a difference signal component between one frame for each pixel. When the signal level of the differential signal component is less than the set value ± Th, the binarization unit 78 determines that it is a still region and determines that it is “0”, and if it is ± Th or more, it determines that it is a moving image region and “2” Outputs a value signal. The smoothing unit 79 performs a smoothing process such as an integration operation in a horizontal / vertical space region. Then, a motion detection signal FD obtained by removing isolated points and replenishing discontinuous points is obtained.
[0147]
FIG. 31 is a diagram illustrating a first configuration example of the motion vector detection unit 75. The stationary block detector 81 detects the presence / absence of “1” in the motion detection signal FD for each block (for example, 16 pixels × 16 lines or 8 pixels × 8 lines). Then, “0” is output to the signal BM only when the signal FD is “0” for all the pixels in the block, and “1” is output otherwise. Only when the signal BM is “1”, the block matching processing unit 80 uses the luminance signal components of the current frame signal S73 and the previous frame signal S74 of sequential scanning to search for a block pair with the smallest error in the block matching processing. The motion vector Va in the obtained block pair is output. As a result, since the motion vector Va is searched only when the signal BM is “1”, the motion vector search by the block matching process can be limited to the moving image block, and the amount of signal processing required for the search can be greatly reduced. . The selection unit 82 outputs, as a motion vector signal V, a motion vector of 0 for a still block whose signal BM is “0” and a motion vector signal V of a moving image block whose signal BM is “1”.
[0148]
FIG. 32 is a diagram illustrating a second configuration example of the motion vector detection unit 75. In this configuration example, an adjacent motion information detection unit 83 and a motion vector correction unit 84 are added to the configuration of FIG. 31 to detect a motion vector with higher accuracy. The adjacent motion information detection unit 83 performs signal processing for detecting the correlation of motion with adjacent blocks, and an outline of the operation will be described with reference to FIGS. 33 (a) and 33 (b). As shown in FIG. 33 (a), the adjacent motion information detection unit 83 correlates motion in the form of motion detection signals FD in the boundary regions lu, lr, ld, and ll between the upper and lower and left and right adjacent blocks in contact with the current block. The relationship is detected, and the adjacent block motion information signal ABM (1-9) shown in FIG. 33B is output. For example, when the number of “1” s in the motion detection signal FD in the boundary region is plural (for example, 4 or more) only in the region lu (lu ≠ 0, lr = ld = ll = 0), the motion of the upper block It is determined that there is a correlation, and “1” is output to the signal ABM. Similarly, when there are only a plurality of (1 or more) motion detection signals FD of “1” (for example, 4 or more) in the regions lr, ld, and ll, there is a correlation between the motions of the right, lower, and left blocks, respectively. Determine and output signals ABM2-4.
[0149]
In addition, when a state in which a plurality of motion detection signals FD of “1” exist (for example, 4 or more) occurs in two continuous regions, it is determined that there is a correlation between the motions of the corresponding adjacent blocks, and Signals ABM5-8 are output. For example, when a state where a plurality of “1” motion detection signals FD exist (for example, 4 or more) occurs in the regions lu and lr, ABM5 indicating the correlation between the motions of the upper and right blocks is output. . If the state in which a plurality of “1” s exist in the motion detection signal FD (for example, 4 or more) is in any other form, it is determined that a highly accurate motion vector can be detected using only the current block, and ABM 9 is output. To do.
[0150]
The motion vector correction unit 84 generates and outputs a corrected motion vector by an average operation of the motion vectors of the current block and the corresponding adjacent block, as shown in FIG. 33B, in accordance with the adjacent block motion information signal ABM. For example, when the signal ABM is 1, a corrected motion vector (Vo + Vu) / 2 generated by averaging the motion vector Vo of the current block and the motion vector Vu of the upper block is output. When the signal ABM is 5, a corrected motion vector (Vo + Vu + Vr) / 3 generated by averaging the motion vector Vo of the current block, the motion vector Vu of the upper block, and the motion vector Vr of the right block is output. When the signal ABM is 9, the motion vector Vo of the current block is output as it is. With the simple correction process described above, it is possible to detect a motion vector with higher accuracy.
[0151]
FIG. 34 is a diagram illustrating a third configuration example of the motion vector detection unit 75. In the figure, the stationary block detection unit 81 and the block matching processing unit 80 are substantially the same as the parts denoted by the same numbers in FIG. The control unit 83 ′ generates a control signal CT necessary for the operation of the block matching processing unit 80 and the pixel motion vector calculation unit 82 ′ in accordance with the block-unit signal BM from the still block detection unit 81. The pixel motion vector calculation unit 82 ′ calculates a pixel motion vector signal V from the block-unit motion vector Va.
[0152]
FIG. 35 is a diagram illustrating a first configuration example of the pixel motion vector calculation unit 82 ′. As will be described later with reference to FIG. 36, the calculation unit 82 ′ uses the motion vectors of the current block and the upper, lower, left, and right blocks adjacent thereto to minimize the motion correction error in units of mini-blocks (for example, 2 pixels × 2 lines). A motion vector signal V is output by performing a process of assigning the motion vector to be a motion vector of a pixel in the mini-block. The adjacent block motion vector array unit 84 ′ outputs motion vectors Vo, Vu, Vr, Vd, and Vl of the current block and the adjacent block corresponding to the mini-block from the block unit motion vector Va according to the control signal CT.
[0153]
The error calculation units 85-1,..., 85-6 respectively perform motion correction error signals ER, ERo,... Of the following equation (7) in units of mini-blocks for the current frame signal S73 and the previous frame signal S74. And ERl.
[0154]
[Expression 7]

[0155]
Here, the symbol abs {} is an absolute value, Vix, Viy (i = o, u, r, d, or l) is the x direction component of the motion vector Vi, the y direction component, and Σ is all the pixels in the mini-block. Indicates the sum.
[0156]
The determination unit 86 detects the minimum value among the motion correction error signals ER, ERo,..., And ERl, and outputs a motion vector Vmb corresponding to the minimum value as a motion vector of the pixels in the mini-block. The selection unit 87 selects the motion vector Vo (Vo = 0) of the current block when the control signal CT indicates a still block, and outputs the motion vector signal V of the pixel when the control signal CT is a moving image block.
[0157]
FIG. 36 is a diagram for explaining the outline and effect of the motion vector calculation for each pixel, and shows a part of the moving image plane. In the current block in the figure, a moving image object p in a dot area and a moving image object q in a hatched area with different movements are mixed. Therefore, the motion vector Vo of the current block is different from the motion of any moving image object p, q, and motion vector detection becomes inaccurate. On the other hand, the motion vectors Vu and Vl detected by the adjacent upper block and left block substantially coincide with the motion of the moving image object p. Further, the motion vectors Vr and Vd detected in the right block and the lower block substantially coincide with the motion of the moving image object q.
[0158]
Since the mini-block A is an area of the moving image object p, the signal ERu or ERl is minimized as the motion correction error. Accordingly, the motion vector Vu or Vl is assigned to the pixel of the mini-block A instead of the motion vector Vo. On the other hand, since the mini-block B is an area of the moving image object q, the signal ERr or ERd has the minimum motion correction error. Therefore, the motion vector Vr or Vd is assigned to the pixel of the mini-block B instead of the motion vector Vo. Further, since the mini-block C is a stationary region, the signal ER is minimized as the motion correction error. Therefore, the motion vector 0 is assigned to the pixel of the mini-block C instead of the motion vector Vo.
[0159]
As described above, the motion correction error is calculated in units of mini-blocks, and the motion vector that minimizes this is assigned to the motion vector of the pixel in the mini-block. There is an inaccurate motion vector in the motion vector detected in units of blocks. Even when this is done, the motion vector can be calculated almost accurately in pixel units. That is, it is possible to greatly suppress isolated point deterioration in which a part of an image is replaced with an inappropriate image.
[0160]
FIG. 37 is a diagram illustrating a second configuration example of the pixel motion vector calculation unit 82 ′ illustrated in FIG. In this configuration example, a singular vector correction unit 88 is added to the configuration of FIG. 35 to detect a motion vector with higher accuracy. That is, the singular vector correction unit 88 first shows the following equation (8) using the motion vector Vom of the current mini-block and the motion vectors Vum, Vrm, Vdm, and Vlm of the vertical and horizontal mini-blocks adjacent thereto. Difference values EV1, EV2, EV3, and EV4 are calculated.
[0161]
[Equation 8]

[0162]
A motion vector Vom in which all the difference values exceed an allowable error range (for example, within one pixel in the x direction or within one line in the y direction) is determined as a singular vector. Then, the singular vector is replaced with a correction vector Vmd generated by an average value of the motion vectors of the adjacent vertical, horizontal, and mini-blocks. Therefore, the singular vector with inaccurate motion is replaced with a correction vector (Vmd = (Vom + Vum + Vrm + Vdm + Vlm) / 5) with higher accuracy, and the accuracy of the motion vector can be further improved.
[0163]
As described above, the motion correction error is calculated in units of mini-blocks, and the motion vector that minimizes this is assigned to the motion vector of the pixel in the mini-block. There is an inaccurate motion vector in the motion vector detected in units of blocks. Even when this is done, the motion vector can be calculated almost accurately in pixel units. That is, it is possible to greatly suppress isolated point deterioration in which a part of an image is replaced with an inappropriate image.
[0164]
FIG. 38 is a block diagram of a first configuration example of the motion correction processing unit 76 of FIG. The adder 89 adds and averages the signal S73 of the current frame and the signal S74 of the previous frame to generate a signal component Sav of the still region of the interpolation frame. The correction signal generation unit 90-1 generates a motion correction signal Spr based on the signal S74 of the previous frame and the correction interpolation motion vector Vpr, and the correction signal generation unit 90-2 moves based on the signal S73 of the current frame and the correction interpolation motion vector Vct. A correction signal Sct is generated. An outline of the operation of the correction signal generation units 90-1 and 90-2 is shown in FIG. For the point A (x, y) of the interpolated frame fip, the motion correction signal Spr uses the point A (x, y) of the previous frame fpr as the corrected interpolation motion vector Vpr (horizontal component Vprx, vertical component Vpr). The signal at the position of the point A ″ (x + Vprx, y + Vppy) moved in step S, and the motion correction signal Sct is the corrected interpolated motion vector Vct (the horizontal component Vctx, the vertical component Vcty) of the point A (x, y) of the current frame fct. ) Is a signal at the position of the point A ′ (x−Vctx, y−Vcty) moved at (). That is,
[0165]
[Equation 9]

[0166]
It is. Therefore, it can be easily realized by controlling the read address of the memory circuit with the corrected interpolation motion vector so that the signal of the pixel at the points A ′ and A ″ is read at the point A. The generation of the corrected interpolation motion vector will be described later.
[0167]
The adder 92 adds and averages both the motion correction signals Spr and Sct to generate a signal component Smc of the moving image area of the interpolation frame.
[0168]
The switch unit 93 selects the signal Sav for the pixel whose motion detection signal FD is “0”, and selects the signal Smc for the pixel whose signal FD is “1”. In this output, the moving image area obtains an NTSC progressive scanning signal S5 having a frame frequency of 60 Hz obtained by converting the number of frames by motion compensation type signal processing.
[0169]
The frame order control unit 91 generates corrected interpolation motion vectors Vct and Vpr necessary for the motion correction process based on the frame order information of the frame sequence signal FS. An outline of this operation is shown in FIG. The PAL progressive scan frame order 1 to 5 signal with a frame frequency of 50 Hz is converted into an NTSC sequential scan signal with a frame frequency of 1 to 6 in the frame order 1 to 6 and a frame frequency of 60 Hz by motion compensation type frame interpolation processing. At this time, the corrected interpolation motion vector needs to match the frame position to be interpolated. Therefore, according to the frame order information of the frame sequence signal FS, as shown in the figure, the coefficient values ka and kb to be weighted to the motion vector signal V are changed, and the corrected interpolation motion vector is expressed by the following equation (10). Generate Vpr and Vct
[0170]
[Expression 10]

[0171]
Therefore, Vpr = V * 5/6, Vct = −V * 1/6 (ka = 5, kb = 1) in the interpolated frame in which the frame order is 2, and Vpr = V * 4/6 in the case of 3, , Vct = −V * 2/6 (ka = 4, kb = 2)..., A corrected interpolated motion vector having no positional deviation in the time direction is generated. As a result, frame number conversion without fluctuation in the time direction is realized.
[0172]
FIG. 39 is a block diagram of a second configuration example of the motion correction processing unit 76 of FIG. This is different from the configuration example of FIG. 38 in that the signal component Sav in the still region of the interpolation frame is generated from the signal S73 of the current frame, and can be realized by simpler signal processing. The configuration and function of other units are the same as those in the configuration example of FIG.
[0173]
As described above, according to this embodiment, it is possible to realize a PAL-NTSC sequential scanning system conversion apparatus that requires a small amount of computation for motion correction signal processing, a small circuit scale, and little image quality degradation.
[0174]
FIG. 41 is a block diagram showing a configuration of a motion correction type image signal converting apparatus according to another embodiment of the present invention. In this embodiment, a PAL television signal is converted into a progressive scanning signal having a frame frequency of 60 Hz and the same scanning line number as the PAL television signal.
[0175]
In the present embodiment, the vertical 6-5 converter 72 shown in FIG. 28 is omitted, and the other parts are substantially the same as those shown in FIG. 28, and therefore detailed description thereof is omitted. According to this example, it is possible to realize a method conversion apparatus for PAL sequential scanning with a frame frequency of 60 Hz, which requires a small amount of calculation for signal processing for motion correction, a small circuit scale, and little image quality degradation.
[0176]
FIG. 42 is a block diagram showing a configuration of a motion correction type image signal converting apparatus according to another embodiment of the present invention. In this embodiment, a PAL television signal is converted into a progressive scanning NTSC television signal having a frame frequency of 60 Hz, and the signal processing for detecting a motion vector is simplified. Since the IP conversion unit 71, vertical 6-5 conversion unit 72, frame memory 73, motion detection unit 74, and motion correction processing unit 76 in the figure are the same in configuration and operation as those in the first embodiment, The description is omitted.
[0177]
The simplified motion vector detection unit 94 detects a motion vector in units of blocks or pixels using the motion detection signal FD of the motion detection unit 74.
[0178]
FIG. 43 is a block diagram of a first configuration example of the simplified motion vector detection unit 94. The still block detection unit 81 detects the presence / absence of “1” in the motion detection signal FD in units of blocks, and outputs “0” to the signal BM only when all are “0”, and “1” otherwise. The control unit 83 converts the signal BM into the control signal CT and adds it to the block matching processing unit 96 and the pixel motion vector calculation unit 82 ′.
[0179]
The block matching processing unit 96 outputs 0 to the signal Va when the control signal CT indicates a still block. On the other hand, when the control signal CT indicates a moving image block, an error caused by block matching between the motion detection signal FDpr of the previous frame delayed by one frame period by the 1 frame delay unit 95 and the motion detection signal FD of the current frame. A search for the minimum block pair is performed, and the obtained motion vector is output to the signal Va. In this case, since the signals FDpr and FD are binary signals of “0” and “1”, the search for the block pair with the smallest error is a combination of an EXOR (exclusive OR) circuit, an adder circuit, and a comparison circuit. This can be done with a very simple logic circuit.
[0180]
The pixel motion vector calculation unit 82 ′ has the same configuration as that of FIG. 35 and FIG. 37 described above, and the previous frame delayed by one frame period with the motion vector of the current block and the upper, lower, left, and right adjacent blocks in units of mini-blocks. Motion correction error between the motion detection signal FDpr of the current frame and the motion detection signal FD of the current frame is calculated, and the motion vector that minimizes the motion correction error is assigned to the motion vector of the pixel. Since the signals FD and FDpr are binary signals, the motion correction error can be calculated more easily.
[0181]
FIG. 44 is a block diagram of a second configuration example of the simplified motion vector detection unit 94, which detects a motion vector in units of blocks. The still block detection unit 81 detects the presence / absence of “1” in the motion detection signal FD in units of blocks, and outputs “0” to the signal BM only when all are “0”, and “1” otherwise. The selection unit 82 outputs the motion vector Va detected by the simple block matching processing unit 26 as a motion vector signal V for a motion block of 0 for a still block whose signal BM is “0” and a moving image block whose BM is “1”.
[0182]
Only when the signal BM is “1”, the simple block matching processing unit 96 generates a block based on the motion detection signal FDpr of the previous frame delayed by one frame period by the 1 frame delay unit 95 and the motion detection signal FD of the current frame. A search is made for the block pair with the smallest error by the matching process, and the obtained motion vector Va is output. In this case, since the signals FDpr and FD are binary signals of “0” and “1”, the search for the block pair with the smallest error is a combination of an EXOR (exclusive OR) circuit, an adder circuit, and a comparison circuit. This can be done with a very simple logic circuit. Therefore, it is possible to greatly reduce the amount of calculation of signal processing for searching for a motion vector by block matching processing and to reduce the circuit scale.
[0183]
FIG. 45 is a block diagram of a third configuration example of the simplified motion vector detection unit 94, which detects a motion vector in units of blocks. In this configuration example, an adjacent motion information detection unit 83 and a motion vector correction unit 84 are added to the configuration of FIG. 44 to detect a motion vector with high accuracy. That is, as in FIG. 32 described above, the motion correlation is detected in the form of the motion detection signal FD in the boundary region with the adjacent block, and the motion vector is averaged between the current block and the adjacent block having a high motion correlation. Generates and outputs a modified motion vector.
[0184]
As described above, according to the present embodiment, compared with the embodiment shown in FIG. 28, there is a method conversion apparatus that requires a smaller amount of computation and a smaller circuit scale than that required for motion correction signal processing. realizable.
[0185]
FIG. 46 is a block diagram showing a configuration of a motion correction type image signal converting apparatus according to another embodiment of the present invention. In this embodiment, a PAL television signal is converted into a progressive scanning NTSC television signal having a frame frequency of 60 Hz. In particular, the motion judder whose motion smoothness is impaired is easily noticeable. The motion correction process is performed only for the above.
[0186]
The IP conversion unit 71, vertical 6-5 conversion unit 72, frame memory 73, motion detection unit 74, and motion vector detection unit 75 in the figure perform the same configuration and operation as in FIG. The MC operation control unit 97 detects a motion at a speed (for example, several seconds to 10 seconds / screen width or screen height) at which the motion judder is conspicuous for each block, pixel or mini-block unit with the motion vector signal V. Then, the MC control signal IPM of “1” is output when the motion vector signal V corresponds to the speed in this range, and “0” is output otherwise.
[0187]
The motion correction processing unit 98 is realized in a form in which the configuration shown in FIG. 39 is slightly changed. In the configuration shown in FIG. 39, the switch unit 93 selects the signal S73 and the signal Smc by the motion detection signal FD. In this embodiment, the switch unit 93 calculates the logical product of the motion detection signal FD and the MC control signal IPM. Change to a signal obtained by (AND circuit). That is, the signal Sav is selected when the motion detection signal FD is “1” and the MC control signal IPM is “1”. For this output, an NTSC progressive scanning signal S75 having a frame frequency of 60 Hz, obtained by converting the number of frames by motion correction type signal processing only for the motion of the motion judder that is conspicuous, is obtained. According to the present embodiment, since signal processing is performed only for a signal having a motion speed in a specific range, there is a method conversion device that has a small amount of calculation, a small circuit scale, and motion compensation processing limited to motion that is easily noticeable for motion judder interference realizable.
[0188]
FIG. 47 is a block diagram showing the configuration of a motion correction type image signal converting apparatus according to another embodiment of the present invention. In this embodiment, a PAL television signal is converted into a progressive scanning NTSC television signal having a frame frequency of 60 Hz. In particular, the configuration shown in FIG. 42 is described in the embodiment shown in FIG. The MC operation control unit 97 and the motion correction processing unit 98 are additionally provided. 46. An NTSC sequential scanning signal having a frame frequency of 60 Hz obtained by performing the same operation as that of the embodiment shown in FIG. 46 and converting the number of frames by motion correction type signal processing only for the motion of the motion judder that is conspicuous. Get S5. According to the present embodiment, a system conversion device that achieves further circuit size reduction is realized.
[0189]
FIG. 48 is a block diagram showing the configuration of a motion correction type image signal converting apparatus according to another embodiment of the present invention. In this embodiment, a PAL television signal is converted into a progressive scanning NTSC television signal with a frame frequency of 60 Hz. It is suitable for performing motion compensation type signal processing only for special movements such as scrolling.
[0190]
In the present embodiment, the MC operation control unit 97 in FIG. 46 is replaced with an MC limited operation control unit 99.
[0191]
The MC limited operation control unit 99 uses the motion detection signal FD and the motion vector signal V to detect special motion. That is, when the magnitude and direction of the motion vector of the block, mini-block, or block in which the motion vector signal V ≠ 0 takes almost the same value in the entire screen area, it is determined that the movement is an up / down pan or a horizontal pan. Then, a signal “1” is output to the signal IPM in all screen areas. Further, when the shape of the motion area detected by the motion detection signal FD is a band shape, and the motion vectors of the blocks in this area have substantially the same value, it is determined that the movement is a character scroll. Then, a 1 signal is output to the signal IPM in the corresponding block of the character scroll area. In other areas, “0” is output as the signal IPM.
[0192]
As described above, the motion correction processing unit 98 controls the switch 93 with the logical product operation signal of the signal IPM and the motion detection signal FD. A signal having undergone frame number conversion is obtained.
[0193]
According to the present embodiment, it is possible to realize a system conversion device that performs motion correction processing only for special movements that are prominent in motion judder.
[0194]
FIG. 49 is a block diagram showing the configuration of the seventh embodiment of the motion-correction image signal converting apparatus according to the present invention. In the present embodiment, the MC operation control unit 97 in FIG. 47 is replaced with an MC limited operation control unit 99. The configuration and operation of the MC limited operation control unit 99 are the same as those in the embodiment of FIG. According to the present embodiment, a system conversion device that further reduces the circuit scale is realized.
[0195]
FIG. 50 is a configuration block diagram showing an embodiment in which a motion correction type image signal converting apparatus according to another embodiment of the present invention is applied to a television receiver. In this embodiment, an NTSC sequential scanning display in which the image display unit has a frame frequency of 60 Hz and 525 scanning lines will be described as an example.
[0196]
The baseband band television signal VS is input to the NTSC decoder unit 100, the PAL decoder unit 101, and the control unit 102. The NTSC decoder unit 100 performs signal processing of demodulation processing (YC separation, color demodulation) in accordance with the NTSC system, and outputs an interlaced scanning demodulated signal S80 (luminance signal and color difference signal).
[0197]
The PAL decoder unit 101 performs signal processing of demodulation processing (YC separation and color demodulation) in accordance with the PAL system, and outputs an interlaced scanning demodulated signal S81 (luminance signal and color difference signal). The control unit 102 performs system discrimination based on the synchronization signal of the television signal VS, and generates a control signal CS necessary for image reception of the corresponding system. The switch unit 103 selects the signal S80 with the control signal CS in the NTSC system and the signal S81 in the PAL system.
[0198]
The IP conversion unit 104 performs signal processing of motion-adaptive interlaced-sequential scanning conversion, and outputs a sequential scanning signal. The scaling unit 105 performs signal processing for converting into the format (aspect ratio and the number of scanning lines) of the image display unit. For example, a PAL signal is converted into a signal having 525 scanning lines by vertical 6-5 conversion processing. Further, the progressive scanning signal S83 such as a PC image signal is converted into a signal of 525 scanning lines by a predetermined vertical conversion process.
[0199]
The frame rate conversion unit 106 performs signal processing for motion correction type frame number conversion using the above-described conversion device, and converts the signal into a signal having the same frame frequency as that of the image display unit 108. For example, a progressive scan signal with a PAL frame frequency of 50 Hz is converted into a signal with a frame frequency of 60 Hz by motion interpolation frame interpolation processing.
[0200]
The color space conversion unit 107 performs signal processing such as image quality improvement processing such as contour correction and gradation correction, conversion to three primary color signals, and inverse gamma correction (when the display unit has a linear gamma characteristic). The output signals are sequentially supplied to the scanning display unit 108 to display an image.
[0201]
According to the present television receiver, it is possible to realize a television receiver that realizes a multi-source compatible function and image quality improvement at low cost, and a remarkable effect can be obtained in increasing the number of functions and improving the image quality. Even if the image display unit conforms to the HDTV system, the motion correction type image signal conversion device of the present invention can be applied to the frame number conversion.
[0202]
51 (a) and 51 (b) are motion correction type image signal converters according to another embodiment of the present invention, which sequentially scan a film image such as a movie with a frame frequency of 24 Hz and a frame frequency of 60 Hz. It is a figure explaining the structure and operation | movement of one Example of the apparatus converted into a signal.
[0203]
FIG. 51A is a block diagram of the apparatus, which includes a video demodulation unit 109, an IP conversion unit 110, a frame number conversion unit 111, and a control unit 112.
[0204]
The input video signal VS is subjected to predetermined demodulation processing by the video demodulator 109 to demodulate the interlaced scanning signal S90 composed of the luminance signal and the color difference signal.
[0205]
The control unit 112 determines whether the video signal is a general image signal or a telecine image signal (film image such as a movie by 2-3 pull-down processing based on the generation cycle of the frame in which the inter-frame difference signal component of the video signal VS is zero. A signal converted into a television format), and a signal CTS is 1 for a general image and 0 for a telecine image.
[0206]
When the signal CTS is “1”, the IP conversion unit 110 converts the signal into a progressive scan signal by a conventional motion adaptive scan conversion process. On the other hand, when the signal CTS is “0”, the interpolated scanning line signal is generated by the field signal before and after the same frame signal in the film mode interpolation process, and the telecine sequential scanning with the frame frequency of 24 Hz is performed. Convert to signal.
[0207]
When the signal CTS is “1”, the frame number conversion unit 111 generates a progressive scanning signal VO with a frame frequency of 60 Hz by motion correction type frame number conversion processing similar to the above-described embodiment. On the other hand, when the signal CTS is “0”, the corrected interpolated motion vectors Vct and Vpr necessary for the motion correction process are generated in the sequence in the frame order shown in FIG. That is, as shown in the figure, the coefficient values ka and kb to which the motion vector signal V is weighted are changed, and corrected interpolation motion vectors Vpr and Vct are generated by the following calculation.
[0208]
[Expression 11]

[0209]
Therefore, Vpr = V * 2/5, Vct = −V * 3/5 (ka = 2, kb = 3) in the interpolated frame of frame order 2, Vpr = V * 4 in the interpolated frame of 3 / 5, Vct = −V * 1/5 (ka = 4, kb = 1)... Then, the signal of 1 to 2 in the frame order of the telecine sequential scanning with the frame frequency of 24 Hz is converted into the signal VO of the sequential scanning with the frame frequency of 1 to 5 in the frame order of 60 Hz by the motion correction type frame interpolation processing. .
[0210]
As described above, according to the present embodiment, a frame number conversion device that converts a film image such as a movie into a progressive scanning signal having a frame frequency of 60 Hz can be realized at low cost and high quality.
[0211]
As described above, the present invention is not limited to the above-described embodiment. For example, in the embodiment shown in FIGS. 32 to 49, the vertical 6-5 conversion unit is provided as in the embodiment shown in FIG. With the omitted configuration, it is possible to realize a system conversion apparatus that converts a PAL television signal into a progressive scan signal having a frame frequency higher than 50 Hz.
[0212]
【The invention's effect】
According to the above-described embodiment, it is possible to realize a method conversion apparatus that requires a small amount of calculation for signal processing for motion correction, a small circuit scale, and little image quality degradation. For this reason, a remarkable effect can be obtained in the realization of the multi-source compatible function and the image quality improvement in the television receiver.
[Brief description of the drawings]
FIG. 1 is a block configuration diagram of a method conversion apparatus showing a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration example of a motion detection unit.
FIG. 3 is a diagram illustrating a configuration example of a block unit motion vector search unit;
FIG. 4 is a diagram illustrating a first configuration example of a pixel unit motion vector generation unit;
FIG. 5 is a diagram illustrating a second configuration example of a pixel unit motion vector generation unit;
FIG. 6 is a diagram illustrating a third configuration example of a pixel unit motion vector generation unit;
FIG. 7 is a diagram illustrating a fourth configuration example of a pixel unit motion vector generation unit;
FIG. 8 is a diagram illustrating a first configuration example of a motion compensation interpolated frame generation unit.
FIGS. 9A to 9C are diagrams illustrating an outline of operations of a frame order control unit and a motion correction signal generation unit, respectively.
FIG. 10 is a diagram illustrating a second configuration example of a motion compensation interpolation frame generation unit.
FIG. 11 is a block diagram of a method conversion apparatus showing a second embodiment of the present invention.
FIG. 12 is a diagram illustrating a configuration example of a scene change detection unit.
FIG. 13 is a block diagram of a method conversion apparatus showing a third embodiment of the present invention.
FIG. 14 is a block diagram of a method conversion apparatus showing a fourth embodiment of the present invention.
FIG. 15 is a block diagram of a method conversion apparatus showing a fifth embodiment of the present invention.
FIG. 16 is a block diagram of a method conversion apparatus showing a sixth embodiment of the present invention.
FIG. 17 is a diagram illustrating a flowchart of block unit motion vector search processing;
FIGS. 18A and 18B are diagrams each showing an outline of a block unit motion vector search operation; FIG.
FIG. 19 is a diagram illustrating an outline of a first generation method of a pixel-unit motion vector.
FIG. 20 is a diagram illustrating an outline of a pixel unit motion vector generation operation;
FIGS. 21A and 21B are diagrams each schematically illustrating a second generation method of a pixel unit motion vector.
FIG. 22 is a diagram illustrating an outline of a third generation method of a pixel-unit motion vector.
FIGS. 23A and 23B are diagrams schematically illustrating a fourth generation method of pixel unit motion vectors, respectively. FIGS.
FIG. 24 is an overall block diagram showing a television receiver according to an embodiment of the present invention.
FIG. 25 is an overall block diagram showing a television receiver according to another embodiment of the present invention.
FIG. 26 is an overall block diagram showing a television receiver according to another embodiment of the present invention.
FIG. 27 is an overall block diagram showing a fourth embodiment of a television receiver.
FIG. 28 is a block diagram showing a configuration of a motion correction type image signal converting apparatus according to another embodiment of the present invention.
29 is a schematic diagram of signal processing in the vertical 6-5 conversion unit 2 of FIG. 28. FIG.
30 is a block diagram of a configuration example of a motion detection unit 4 in FIG. 28. FIG.
FIG. 31 is a block diagram of a first configuration example of the motion vector detection unit 5 of FIG. 28;
32 is a block diagram of a second configuration example of the motion vector detection unit 5 of FIG. 28. FIG.
33 is an explanatory diagram of an outline of operation of the adjacent motion information detection unit 13 in FIG. 32. FIG.
34 is a block diagram of a third configuration example of the motion vector detection unit 5 in FIG. 28. FIG.
35 is a block diagram of a first configuration example of a pixel motion vector calculation unit 12 ′ in FIG. 34. FIG.
FIG. 36 is a partial image diagram for explaining the operation of the pixel motion vector calculation unit;
37 is a block diagram of a second configuration example of the pixel motion vector calculation unit 12 ′ in FIG. 34. FIG.
38 is a block diagram of a first configuration example of the motion correction processing unit 6 in FIG. 28. FIG.
FIG. 39 is a block diagram of a second configuration example of the motion correction processing unit 6 in FIG. 28;
FIGS. 40A and 40B are schematic diagrams for explaining an operation of frame interpolation by motion correction processing. FIGS.
FIG. 41 is a block diagram showing a configuration of a motion-correction-type image signal conversion device according to another embodiment of the present invention.
FIG. 42 is a block diagram showing a configuration of a motion correction type image signal converting apparatus according to another embodiment of the present invention.
43 is a configuration block diagram of a first configuration example of the simplified motion vector detection unit 24 of FIG. 42. FIG.
44 is a configuration block diagram of a second configuration example of the simplified motion vector detection unit 24 of FIG. 42. FIG.
45 is a configuration block diagram of a third configuration example of the simplified motion vector detection unit 24 of FIG. 42. FIG.
FIG. 46 is a block diagram showing a configuration of a motion correction type image signal converting apparatus according to another embodiment of the present invention.
FIG. 47 is a block diagram showing a configuration of a motion correction type image signal converting apparatus according to another embodiment of the present invention.
FIG. 48 is a block diagram showing a configuration of a sixth embodiment of a motion compensation image signal converting apparatus according to another embodiment of the present invention;
FIG. 49 is a block diagram showing a configuration of a motion correction type image signal converting apparatus according to another embodiment of the present invention.
FIG. 50 is a block diagram showing a configuration of a motion-correction type image signal conversion apparatus according to another embodiment of the present invention.
FIGS. 51A and 51B are block diagrams showing the configuration of a motion correction type image signal conversion apparatus according to another embodiment of the present invention. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 71, 104, 110 ... IP conversion part, 2 ... Motion correction frame number conversion part, 3, 95 ... 1 frame delay part, 4, 74 ... Motion detection part, 5 ... Block unit motion vector search part, 6 ... Pixel Unit motion vector generation unit, 7 ... motion correction interpolation frame generation unit, 8, 77 ... subtraction unit, 72 ... vertical 76-5 conversion unit, 73 ... frame memory, 75 ... motion vector detection unit, 76, 98 ... motion correction Processing unit 78... Binarization unit 79 79 Smoothing unit 80 Block matching processing unit 81 Still block detection unit 82 Selection unit 82 'Pixel motion vector calculation unit 83 Adjacent motion information detection unit , 83 '... control unit, 84 ... motion vector correction unit, 84' ... adjacent block motion vector arrangement unit, 85 ... error calculation unit, 86 ... determination unit, 87 ... selection unit, 88 ... singular vector correction unit, 89, 92 ... adder DESCRIPTION OF SYMBOLS 90 ... Correction signal generation part, 91 ... Frame order control part, 93, 103 ... Switch part, 94 ... Simple motion vector detection part, 96 ... Simple block matching process part, 97 ... MC operation control part, 99 ... MC limited operation | movement Control unit 100 ... NTSC decoder unit 101 ... PAL decoder unit 102 ... Control unit 105 ... Scaling unit 106 ... Frame rate conversion unit 107 ... Color space conversion unit 108 ... Sequential scanning display unit 109 ... Video demodulation , 111... Frame number conversion unit, 112.

Claims (1)

A scan converter that converts interlaced scanning image signals into sequential scanning image signals;
A motion detection unit that detects a motion of an image using a frame difference signal of the progressive scanning image signal;
A motion vector search unit for searching for a motion vector in units of blocks;
A motion vector of 0 is assigned to pixels that do not detect motion in the motion detection unit ,
Using the motion vector of the current block and the adjacent block searched by the search unit for the pixels in the mini-block included in the current block searched by the search unit, including the pixels whose motion is detected by the motion detection unit A pixel unit motion vector generation unit that assigns a motion vector that minimizes a predetermined motion correction error obtained in units of mini-blocks as a unit motion vector of a pixel;
An image signal method comprising: a motion-corrected interpolation frame generation unit that generates an interpolated frame signal of an image signal using the pixel motion vector, and configured to generate a sequential operation image signal with the number of frames converted In the conversion device,
The motion correction interpolation frame generation unit includes a motion speed detection unit that detects a motion speed based on the motion vector generated by the pixel unit motion vector generation unit, and substantially the same speed is detected by the speed detection unit. An image signal format conversion apparatus that generates the interpolated frame signal that has been subjected to motion correction using only the pixel unit motion vector for only a region.

Images