JP2510879B2 - Television standard converter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television standard conversion device for converting one television signal into another television signal in two television systems having different scanning formats, In particular, it relates to a field interpolation using a motion vector.

(Prior Art) Television standard conversion requires conversion of the number of scanning lines and conversion of the number of fields. Generally, these conversions digitize a television signal and store it in a memory having a capacity of two or more fields. , The address counter is controlled at the time of reading.

FIG. 16 is a block diagram showing a configuration example of a television standard conversion device (hereinafter referred to as a TV conversion device) which receives a digitized component signal, that is, a luminance signal Y and color difference signals RY and BY. The TV format conversion apparatus shown in the figure comprises a multiplexing circuit 21, memories 22a and 22b, line interpolation circuits 23a to 23d, and field interpolation circuits 24a and 24b.

The digitized Y signal is input to the memory 22a having a capacity of 2 fields, and the color difference signals RY and BY are multiplexed by the multiplexing circuit 21.
Is input to The multiplexing circuit 21 time-division-multiplexes RY and BY, and its output is a memory 22 having a capacity of 2 fields.
Sequentially written to b. Hereinafter, this multiplexed color difference signal will be referred to as a C signal. In the memory 22a, signals of two fields are read at the same time. At the time of reading the memory 22a, an address counter (not shown) is controlled to increase or decrease the number of scanning lines. The output signal of the memory 22a is input to the line interpolation circuits 23a and 23b, respectively. Here, image distortion caused by an increase or decrease in the number of scanning lines is corrected by using signals of several adjacent lines in the same field. Thereafter, the field interpolation circuit 24a corrects the discontinuity of the moving image caused by the increase or decrease in the number of fields by the linear interpolation between the fields. The operation for the C signal is almost the same as that for the Y signal. The line interpolation processing methods in the line interpolation circuits 23a to 23d are digital interpolation using a method of performing linear interpolation using signals of two adjacent lines in the same field and digital signals using signals of several adjacent lines in the same field. There is a filter method. Although the deterioration of resolution is less when using a digital filter, there is a method of using adjacent signals between fields as a method of further reducing the deterioration of resolution. However, when a signal between fields is used, a good correction can be performed for a still image because the correlation between signals in the field and the correlation between signals in the field are large. On the other hand, the signal correlation between fields becomes small, and when the interpolation processing is performed using the signals between fields, the image is distorted. Therefore, when the line interpolation processing between fields is used, it is necessary to apply this only for a still image and perform the line interpolation processing within a field for a moving image. Therefore, a new motion detection function is needed.

FIG. 17 is a block diagram showing a configuration example of a TV system converter having the motion detection circuit and adopting the interline / intrafield adaptive type line interpolation method. In the figure,
The same reference numerals as those in FIG. 16 denote the same components, and with respect to the device of FIG. 16, delay circuits 25, 27a and 27b, a motion detection circuit 26, a memory 29, line interpolation circuits 30a and 30b, Delay circuits 31a and 31b and switching circuits 32a and 32b are added. Motion detection is performed using the Y signal. The delay circuit 25 is configured by using a 1-frame capacity FIFO memory or a normal memory for motion detection. The motion detection circuit 26 detects a motion using signals separated by one frame obtained at the input and output of the delay circuit 25. For example, after calculating the difference between one frame for each pixel, a two-dimensional low-pass filter. The noise component is removed with, and if the output level of this low-pass filter is larger than the threshold value, it is determined that there is motion. 1 bit of the motion detection signal indicating the presence / absence of motion detected in this way is set to 2
It is stored in the field capacity memory 29. On the other hand, the Y signal and the C signal are delayed by the delay circuits 27a and 27b by the time required for motion detection and then stored in the memories 22a and 22b, respectively. The outputs of the memories 22a and 22b are, as shown in FIG.
Line interpolation circuits 23a to 23d in the same field and line interpolation circuits 30a and 30b for performing line interpolation processing between fields
To the field interpolation circuits 24a and 24d.
After the moving image is corrected (field interpolation processing) at b, it is input to the switching circuits 32a and 32b. The signals interline-field interpolated by the line interpolating circuits 30a and 30b are used only for a still image, so that there is no need for motion correction. Therefore, the field interpolating circuits 24a and 24b do not pass through and the delay circuits 31a and 31b are input to the switching circuits 32a and 32b. The OR circuit 31 ORs the motion detection signals of the respective fields read in parallel from the memory 29, and then the switching circuits 32a, 32
Entered in b. As a result, when the motion detection signal of one of the fields indicates that there is motion (“1”) (during a moving image), the switching circuits 32a and 32b cause the field interpolation circuits 24a and 24b.
Output signal is selected and output. On the other hand, when the motion detection signal of any field indicates no motion (“0”) (at the time of still image), the output signals of the delay circuits 31a and 31b (that is, the signals interline-interpolated between the fields) Are selected and output by the switching circuits 32a and 32b.

(Problems to be Solved by the Invention) However, in the TV system conversion device having the above-described configuration, image distortion caused by an increase or decrease in the number of scanning lines can be corrected almost without deterioration of resolution, but a moving image may not be displayed due to an increase or decrease in the number of fields. Continuity cannot be completely corrected by linear interpolation processing using signals between fields, and especially in parallel moving images or signals with a wide moving image area, this lack of smoothness of movement appears prominently. There is a point.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a TV system conversion device capable of smoothly correcting even a parallel moving image or an image having a wide moving image area.

(Means for Solving the Problem) In order to solve the above problems, the present invention provides a first memory having a capacity of 2 fields or more and storing a digitized luminance signal, and a capacity of 2 fields or more. Have,
Second, storing digitized and quantized color difference signals
Memory, first detection means for detecting the presence or absence of motion from the inter-frame difference of each pixel from one of the input signal and the output signal of the first memory, and the same field for the output signal of the first memory. A first line interpolating means for performing line interpolation using the line information in the first and second line interpolating means using line information between two fields interlaced with the output signal of the first memory. 2 line interpolation means, 3rd line interpolation means for performing line interpolation on the output signal of the 2nd memory using line information in the same field, and for the output signal of the 2nd memory Of the first and second line interpolating means based on the detection result of the first detecting means and the fourth line interpolating means for performing line interpolation by using the line information between the two fields interlaced with each other. Output signal First selection means for selecting one,
A television standard conversion apparatus comprising: a second selection unit that selects one of the output signals of the third and fourth line interpolation units based on the detection result.
The output signal of the selection means of 1 field separated by m pixels
It is divided into n line (m, n; integer) blocks, and second detection means for detecting a motion vector for each block, and validity / invalidity of the motion vector detected by the second detection means are determined. , Determining means for outputting the motion vector at the time of validity determination, converting means for converting the output signal of the determining means into a motion vector corresponding to the scanning line, and the output signal of the first selecting means for each field. Two l to store
Third and fourth memories having a capacity of (n or more) lines, and a second memory having a capacity of two l (n or more) lines for storing the output signal of the second selecting means corresponding to each field. Fifth and sixth memories, correction means for changing the read address by the value of the product of the motion vector from the conversion means and the field interpolation ratio, and outputting the contents of the third to sixth memories; First field interpolation means for performing field interpolation on the output signals of the third and fourth memories, and second field interpolation means for performing field interpolation on the output signals of the fifth and sixth memories. It is provided.

(Operation) The present invention operates as follows. The first selection means (for example, a switching circuit to be described later) on the side of the luminance signal (Y signal) is based on the detection result of the first detection means (for example, the motion detection circuit or the like), and the first and second line interpolation means The second selection means on the side of the multiplexed color difference signals (C signals) works similarly to adaptively select and output one of the output signals, and similarly outputs the third and fourth line interpolation means. It works to adaptively select and output one of the signals. The second detection means (for example, a motion vector detection circuit described later) works to detect the motion vector for each m × n block of the output signal of the first selection means separated by one field, and the determination means (for example, described later). The motion vector determining circuit) determines whether the detected motion vector is valid or invalid, and outputs the motion vector only when it is valid. The conversion means (for example, a memory described later) works to convert the determined motion vector for each block into a motion vector corresponding to a scanning line (line). The correction means (for example, a correction circuit in a field interpolation circuit described later) changes the read address by the value of the product of the line-converted motion vector and the field interpolation ratio, and Y
It serves to output the contents of the third and fourth memories on the signal side and the contents of the fifth and sixth memories on the C signal side.
As a result, position correction is performed on the signals (moving image lines) from the first and second selecting means, and for these, the same first and second field interpolating means (for example, a calculation to be described later) similar to the conventional one is performed. Field interpolation is performed by the circuit) to obtain the desired scan forming output component signals (Y signal, C signal). As described above, since the position correction is performed on the moving image according to the detected motion vector, the problem of the above-mentioned conventional technique can be solved.

(Embodiment) FIG. 1 is a block diagram of a TV system conversion apparatus showing a first embodiment of the present invention. In the figure, 1a, 1b and 1c are input terminals for inputting an input component signal, 2a and 2b are output terminals for outputting a converted output component signal, and 3 is an input signal (Y signal) from the input terminal 1a. A delay circuit for delaying by a frame, 4 is a detection circuit (corresponding to the above-mentioned first detection means) for detecting motion using the input / output signals of the delay circuit 3,
5a and 5b are delay circuits that delay the input signal by the motion detection time, 6 is a multiplexing circuit that time-division multiplexes the color difference signals RY and BY from the input terminals 1b and 1c, and 7 has a capacity of 2 fields,
Memory for storing motion detection signals indicating the presence or absence of motion, 8a, 8
b is a memory having a capacity of 2 fields and storing a Y signal and a multiplexed color difference signal C (corresponding to the above-mentioned first and second memories), and 9 is a logic of an output signal of each field of the memory 7. OR circuit for summing, memory 10a to 10d is memory 8
A line interpolation circuit (corresponding to the above-mentioned first and third line interpolation means) which performs line interpolation at an arbitrary line interpolation ratio using line information in one field for the output signals of a and 8b. ), 11a and 11b are line interpolation circuits that perform line interpolation at an arbitrary line interpolation ratio using line information between two fields interlaced with the output signals of the memories 8a and 8b (the above-mentioned first 2 and fourth line interpolating means),
Switching circuits (corresponding to the above-mentioned first selecting means) 12a and 12b select and output one of the output signals of the line interpolation circuits 10a and 10b and the line interpolation circuit 11a based on the output signal of the OR circuit 9. ), 12c, 12d are switching circuits for selecting and outputting one of the output signals of the line interpolation circuits 10c, 10d and the line interpolation circuit 11b based on the output signal of the OR circuit 9 (in the second selection means described above). Equivalent), 12e is a switching circuit that rearranges input signals in field units in order of earliest time based on the switching signal, 13e
Is a motion vector detection circuit that detects a motion vector from the output signal of the switching circuit 12e in block units of m pixels × n lines (m and n are integers), and 14 is a motion vector averaging circuit that averages the detected motion vectors. , 15 is a motion vector determination circuit that determines whether the motion vector averaged based on the output signal of the switching circuit 12e is valid or invalid, and outputs the motion vector when valid, and "0" when invalid, 16 is a block A memory (corresponding to the above-mentioned conversion means) for converting a unit motion vector into a motion vector corresponding to a scanning line, 17a is based on the output signal of the memory 16 and is used for position correction and field correction for the output signals of the switching circuits 12a, 12b. A field interpolation circuit 17b performs interpolation, and a field interpolation circuit 17b performs position correction and field interpolation on the output signals of the switching circuits 12c and 12d based on the output signal of the memory 16.

In the present embodiment, the control means such as the memories 7, 8a, 8b, 16 are omitted for simplicity of explanation. Also, the switching circuit
The switching signal for 12e etc. shall be given by the control part (not shown) which controls the whole apparatus.

The operation of the TV system changing apparatus configured as described above will be described.

Of the digitized component signals Y, RY, BY, the color difference signals RY, BY input from the input terminals 1b, 1c are time-division multiplexed by the multiplexing circuit 6. If the sampling frequency of the Y signal and the color difference signal is 2: 1
RY, BY, RY for each pixel based on the signal. The multiplexed color difference signal (C signal) and the Y signal input from the input terminal 1a are stored in the memory 8 via delay circuits 5a and 5b, respectively.
It is stored in a and 8b. When reading these memories 8a and 8b, the conversion of the number of scanning lines and the conversion of the number of fields are performed by controlling the read address of the memory by an address counter (not shown). That is, conversion of the number of scanning lines is performed by thinning out and repetitive insertion of scanning lines (lines), and conversion of the number of fields is also performed by thinning out and repetitive insertion of fields. However, the conversion of the number of fields is actually performed by controlling the field interpolation ratio of the field interpolation circuit.

On the other hand, the Y signal input from the input terminal 1a is directly input to the motion detection circuit 4 and also delayed by one frame by the delay circuit 3 and input. In the motion detection circuit 4, for example, the frame difference is calculated for each pixel, the noise component is removed from the value by a two-dimensional low-pass filter, and the number of pixels whose output value of the filter exceeds the threshold α ₁ is the threshold α ₂ or more. If so, the peripheral α ₃ pixel area centering on the image difference is determined to be in motion. However, for α ₁ , α ₂ , and α _3, the variable settings are fixed values, and the optimum values are determined by the image signal. However, in order to reduce the distortion of the line interpolation, the moving image is detected sensitively.

A motion detection signal indicating the presence or absence of motion is written in the memory 9. The writing / reading control of the memory 9 is exactly the same as that of the field converting memories 8a and 8b. The output signal for each field of the memory 9 is input to the OR circuit 10 and logically ORed.

As a result, if the motion detection signal of one of the fields indicates that there is motion (“1”), it means a moving image “1”.
Is output, and when the motion detection signals of both fields indicate no motion (“0”), “0” indicating a still image is output.

The signals of two fields are simultaneously read from the memories 8a and 8b. The Y signal of each field read from the memory 8a is input to the line interpolating circuits 10a and 10b for line interpolating processing within the field, and also input to the line interpolating circuit 11a for interline interpolating processing between fields. To be Similarly, the C signal of each field read from the memory 8b is also subjected to line interpolation processing within the field by the line interpolation circuits 10c and 10d, and line interpolation processing between fields by the line interpolation circuit 11b. . As described above, the line interpolation processing of the line interpolation circuits 10a to 10c uses the method of performing linear interpolation using the signals of two adjacent lines in the same field, and the signals of several adjacent lines in the same field. There is a method of obtaining an interpolated signal by using a digital filter method. However, whichever interpolating method is used, an interlace interpolation processing function is further required here.

The TV system converter is originally an independent synchronization system for the input side and the conversion output side, and the television signal is an interlaced signal. Therefore, a memory having a capacity of 2 fields is used to perform conversion on a field-by-field basis. The field conversion performed by the converter is odd field (1st) → odd field (1st), even field (2nd) → even field (2nd), odd field (1st) → even field (2nd), even field (2nd) → There are four cases of odd fields (1st). Normally, in the case of the same kind field conversion (in the case of,), the center of gravity of the image before and after the conversion does not change, but in the case of different kind of conversion (in the case of the case), the center of gravity of the images before and after the conversion moves up and down by one line. For example, for conversion from 60 fields to 50 fields (or vice versa),
Since the conversion from 6 fields to 5 fields (or vice versa) is performed, the movement of the center of gravity occurs every 6 fields (or every 5 fields). The interlaced interpolation process corrects the movement of the center of gravity by advancing or delaying the signal in the field by one line in the heterogeneous field conversion and simultaneously using the signal in the field. Therefore, the output signals of the line interpolation circuits 10a to 10d are not only line-interpolated signals but also interlaced-interpolated signals, and are corrected so that the centroids of the images of the two line interpolator output signals 21 and 22 match. (For details, see, for example
-25190). A second example of line interpolation processing between fields including this interlaced interpolation processing
Shown in Figures and 3. FIG. 2 is an enlarged view of the diagonal line pattern of the original signal. In the figure, white circles represent odd field (1st) signals, and white squares represent even field (2nd) signals. FIG. 3 shows conversion of the number of lines and line interpolation processing when the output side in the 525 → 625 system is an even field. In the figure, white circles indicate the above case (1st → 1s
t), the white square mark indicates the case of (2nd → 1st), and the black circle and the black square mark respectively indicate one line (1H) delay signal. Also, the line interpolation ratio (128 = 100%) in the figure is shown corresponding to the line number, and OH is the line interpolation ratio of the signal,
1H represents the line interpolation ratio of the signal delayed by one line. The broken line in the figure is a signal which has been line-converted when the memories 8a and 8b are read out, and the solid line is a signal obtained by line interpolation. In this case, the signal of the same line is repeatedly inserted every 5 lines by the line conversion, and the position of the repeatedly inserted line is set for each field for the purpose of reducing the distortion of this discontinuous portion and for interlaced interpolation. Is changed every 3 lines. In the figure, an interpolation method using two adjacent lines, which is easy to explain, is shown, but basically the same applies when a digital filter is used.

In the line interpolation processing between fields of the line interpolation circuits 11a and 11b, interpolation is performed using two adjacent lines between fields. An example of this case is shown in FIG. As shown in the figure, also in the case of the line interpolation between fields, the line interpolation processing considering interlaced interpolation is performed. Further, the center of gravity of the image of the line interpolation in the field and the center of gravity of the image of the interline line interpolation are also corrected so as to be the same, as can be seen from FIGS.

In this way, the line interpolation circuit 10a, 10b performs the line interpolation processing on the Y signal in the field and the line interpolation circuit
The Y signal line-interpolated between the fields in 11a is input to the switching circuits 12a and 12b as shown in FIG. C
Similarly, on the signal side, the output signals of the line interpolating circuits 10c and 10d and the output signal of the line interpolating circuit 11b are input to the switching circuits 12c and 12d. In this embodiment, unlike the case of FIG. 17, the first
As shown in the figure, the output signals of the line interpolating circuits 11a and 11b for performing the line interpolating processing between fields are switched to the switching circuits 12a to 12d.
However, since the same signal is input to each field interpolation circuit, the result is the same as when no field interpolation processing is performed.

In the switching circuits 12a to 12d, when the output signal of the OR circuit 9 indicates a moving image (“1”), the output signals of the line interpolation circuits 10a to 10d are selected and output, and when a still image is displayed (“0”). ) Selects and outputs the output signals of the line interpolation circuits 11a and 11b.

In this way, based on the output signal of the OR circuit 9, the output signal of the line interpolating circuit in the field or between the fields is adaptively switched by the switching circuit, and the output signals of the switching circuits 12a, 12b on the Y signal side are The signals are input to the field interpolation circuit 17a and the switching circuit 12e, and the output signals of the switching circuits 12c and 12d on the C signal side are input to the field interpolation circuit 17b.

In the switching circuit 12e, the input signals from the switching circuits 12a and 12b are rearranged in order of the earliest time field based on the switching signal from the control unit (not shown), and the earliest time signal is set as the current field signal. The signal one field before is taken as the previous field signal. The output signal of the switching circuit 12e is input to the motion vector detection circuit 13 and the motion vector determination circuit 15.

The motion vector detection circuit 13 detects a motion vector for each block of m pixels × n lines (m, n: integer) using the signals of the two fields separated by one field from the switching circuit 12e. Here, a block of 8 pixels × 8 lines with m = n = 8 is used as a reference block, and a motion vector is detected for each block over the entire screen. The block matching method and the iterative gradient method are well known as a method of detecting a motion vector that can be arithmetically processed in real time, but a method conversion device using a field interpolation method requires particularly accurate detection of motion. Also, the iterative gradient method is used because it is desirable that the circuit scale is small. For details, see
No. 60-158786.

FIG. 5 shows a motion vector detection circuit 13 using the iterative gradient method.
3 is a block diagram showing a configuration example of FIG. In the figure, 51 is a memory that stores the detected motion vector, 52 is a selection circuit that selects a motion vector as an initial displacement vector from the motion vector, and 53 is between the fields whose positions are displaced by the initial displacement vector. An arithmetic circuit that performs the gradient method using a signal, 54 is an adder that adds the arithmetic result of the arithmetic circuit 53 and the initial displacement vector of the output of the selection circuit 52, and 55 is the displacement of the value of the output of the adder 54 An arithmetic circuit for performing the gradient method arithmetic operation using the signals between the fields, and an adder 56 for adding the arithmetic result of the arithmetic circuit 55 and the deviation amount to output a motion vector.

A motion vector detects 8 pixels × 8 lines as one block, but in the calculation by the iterative gradient method, the calculation accuracy is improved in a wider block, so a signal within a block of 20 pixels × 16 lines is used. However, in this case, if all the pixels in 20 pixels x 16 lines are used, the arithmetic circuit becomes large, so
Every other pixel Total number of pixels on every other line 80 pixels (10 pixels x
8 lines) are used for the calculation of the iterative gradient method.

FIG. 6A shows the positional relationship between the motion vector detection block size and the iterative gradient method operation block.
A candidate vector of the initial displacement vector is shown in FIG.

The memory 51 stores the already detected motion vector, and the selection circuit 52 selects the initial displacement vector from the stored motion vector. The candidate vectors for the initial displacement vector are the following six types of motion vectors.
In FIG. 6 (b), the block to be detected of the motion vector is shown by the hatched portion, and the motion vector detected by this block
Bo = indicated as ^{(Vx (o), Vy (} o)), also showed already motion vectors that are detected in the peripheral blocks on the basis of this block in C ₁ -C _19. The six motion vectors are: the motion vector of the block immediately above the detected block of the current field: C ₁ the motion vector of the block immediately above the detected block of the current field: C ₂ the motion vector of the left block of the detected block of the current field: C ₃ Motion vector detected in the previous field immediately below the detected block: C ₁₁ Average vector of the previous field: Previous field acceleration vector: And Therefore, the memory memory 51 has a capacity such that these motion vectors can be read from the memory.

The selection circuit 52 selects the motion vector closest to the true motion as the initial displacement vector from the above six types of motion vectors. The selection method is the signal of the previous field, between the signal of the block whose block coordinates are displaced by the amount of each motion vector and the detected block of the current field,
The field difference value for each pixel is calculated, the block at which the sum of the absolute values becomes the minimum is detected, and the motion vector that gives that block is set as the initial displacement vector.

FIG. 7 is a block diagram showing an internal configuration example of the selection circuit 52,
The selection circuit 52 in the figure includes a memory 521 for storing a current field signal, six memories 522a to 522f for storing a previous field signal in correspondence with six types of motion vectors, and six subtractors.
523a to 523f, 6 absolute value circuits 524a to 524f, 6 accumulators 525a to 525f, 5 comparators 526a to 526e, 4 switching circuits 527a to 527d, and a motion vector selection circuit 528 To be done.

Of the output signals of the switching circuit 12e, the signal of the current field is input to the memory 521. This memory 521 is a switching circuit
The signal for each scanning line of 12e is taken out as a signal for each block, and the storage capacity of the calculation block size of 20 pixels × 16 lines requires a capacity of 16 lines or more. FIG. 8 shows an operation explanatory diagram of the memory 521 in the case of converting into a block of 8 pixels × 8 lines in the case of an input signal of q lines with q pixels per line. The calculation block of the iterative gradient method is every other pixel, every other line 10 pixels ×
Since there are 8 lines, the output of the memory 151 is 1 in this case.
The signal is every other pixel and every other line.

Six signals from the switching circuit 12e in the previous field are stored in the memory 522.
Input to a to 522f. To the other inputs of these memories 522a to 522f, six kinds of motion vectors (candidate vectors) C ₁ , C ₂ , C ₃ , C read from the memory 51 as shown in FIG.
₄ , and ′ are input respectively. These memories 522a
The function of ~ 522f is basically the same as the memory 521,
In addition, it has a function to shift the read address by the input motion vector when reading. Therefore, each memory (52
2a to 522f), signals for each block deviated by the input motion vector are input to the corresponding six subtraction circuits 523a to 523f. Each subtraction circuit (523a to 523f) has 80 pixels from the memory 521 and 8 pixels from the memories 522a to 522f for each block.
The difference from 0 pixels (field difference in this case) is calculated. The outputs of these subtraction circuits 523a to 523f are converted into absolute values by the corresponding absolute value circuits 524a to 524f, and then input to the corresponding accumulators 525a to 525f to accumulate 80 pixel differences. The accumulation results of the accumulators 525a and 525b are input to the comparison circuit 526a and the switching circuit 527a. Comparison circuit 52
The output signal indicating the comparison result of 6a is selected as the control signal of the switching circuit 527a from the output signals of the accumulators 525a and 525b, whichever has the smaller accumulation result and the motion vector selection circuit 528.
Output to The output signal of the selected switching circuit 527a is
It is input to the comparator 526b, where it is compared with the output signal of the accumulator 525c. According to this comparison result, the smaller accumulation result is selected by the switching circuit 527b and input to the comparator 526c. In this way, the output signals of the accumulators 525d, 525e, 525f are sequentially compared by the comparison circuit 526c and the switching circuit 527c, the comparator 526d and the switching circuit 527d, and the comparator 526e. The motion vector selection circuit 528 has six types of motion vectors C ₁ , C ₂ , C ₃ , C ₄ ,
, 'And the output signals of the five comparison circuits 526a to 526e are input, and the motion vector when the accumulation result in the six accumulation circuits 525a to 525f is the smallest is selected. This selected signal becomes the initial displacement vector, which is input to the arithmetic circuit 53 and the adder 54.

The gradient method arithmetic circuit 53 obtains the displacement vectors Vx ⁽¹⁾ and Vy ⁽¹⁾ by the following equations (1) to (4).

However, SGNΔx is the sign of Δx, SGNΔy is the sign of Δy,
DFD is a difference value between fields, and a, b, c, d are adjacent pixels in the current field of the reference pixel e. The positional relationship between these is
It is shown in FIG.

FIG. 10 is a block diagram showing an internal configuration example of the arithmetic circuit 53 (55). The arithmetic circuit 53 in the figure includes shift circuits 531 and 532,
Three subtraction circuits 533a, 533b, 533c, four memories 534a to 53
4d, 2 absolute value circuits 535a, 535b, 4 accumulation circuits 536a
˜536d, two code operation circuits 537a and 537b, two fractional circuits 538a and 538b, and two multiplication circuits 539a and 539b. Of the output signals of the switching circuit 12e, the current field signal is a 2-bit delay shift circuit 531, a subtraction circuit 533a,
2-line delay shift circuit 532, subtraction circuit 532b, memory 5
Input to 34e respectively. On the other hand, the signal of the previous field is input to the memory 534d. The subtraction circuit 533a is for obtaining Δx and SGNΔx in the equation (3) by subtracting the output signal of the shift circuit 531 from the input signal of the current field, and the subtraction circuit 533b is for the shift signal of the shift circuit 532 from the input signal of the current field. By subtracting the output signal, Δy and SGNΔy in the equation (4) are obtained. The output signals of these subtraction circuits 533a and 533b are stored in memories 534a and 534a, respectively.
Input to 534b. The operation of memories 534a-534c is a selection circuit
This is the same operation as the memory 521 of 52. The block unit output signals of the memories 534a and 534b are converted into absolute values by the absolute value circuits 535a and 535b, and then the accumulation circuits 536a and 536b perform accumulation of 80 pixels for each block. The memory 534d is the memory of the selection circuit 52.
The same movement as 522a to 522f, that is, the read address is displaced by the amount of the motion vector (in this case, the initial displacement vector). The subtraction circuit 53 outputs the output signals of the memories 534c and 534d.
3c is input and subtracted, and the output is the sign operation circuit 537.
The calculation of SGNΔx · DFD and SGNΔy · DFD is performed at a and 537b. The outputs of the sign arithmetic circuits 537a and 537b are accumulation circuits 536c and 536d.
, Where 80 pixels are accumulated for each block. The output signals of these accumulator circuits 536c and 536d are ΣSGNΔx · DFD, ΣSGNΔy · DF in the above equations (1) and (2).
D, and the output signals of the accumulator circuits 536a and 536b are Σ |
Δx |, Σ | Δy |. 1 / Σ | Δx in the fractional circuits 538a and 538b corresponding to the output signals of these accumulator circuits 536a and 536b.
After calculating | and 1 / Σ | Δy |, the multiplication circuits 539a and 539b output the output signals of the fractional circuit 538a and the accumulation circuit 536c, and the fractional circuit 53.
The displacement vectors Vx ⁽¹⁾ and Vy ⁽¹⁾ are calculated and output by multiplying the output signals of 8b and the accumulator circuit 536d, respectively.

In this way, the adder 54 adds an initial displacement vector to the displacement vector calculated by the arithmetic circuit 53, and the displacement vector Vx ⁽²⁾ is added by the arithmetic circuit 55 of the next gradient method using the initial displacement vector as the initial displacement vector. , Vy ⁽²⁾ is calculated by an arithmetic circuit 55 similar to the arithmetic circuit 53. The operation method 55 of the gradient method has the same basic operation as the operation circuit 53, and V ^0.1 = (Vx ⁽⁰⁾ + Vx ⁽¹⁾ , Vy ⁽⁰⁾ instead of the initial displacement vector in the memory 534d of FIG. + V
Enter y ⁽¹⁾ ). Others are the same as the arithmetic circuit 53.
The displacement vectors Vx ⁽²⁾ , Vy ⁽²⁾ and the initial displacement vector Bo = (Vx ⁽⁰⁾ , Vy ⁽⁰⁾ ) and the displacement vector V obtained by the arithmetic circuit 55
x ⁽¹⁾ , Vy ⁽¹⁾ are added by the adder 56 to obtain motion vectors V _X , V _Y
Becomes That is, the motion vectors V _X and V _Y are V _X = Vx ⁽⁰⁾ + Vx ⁽¹⁾ + Vx ⁽²⁾ …… (5) V _Y = Vy ⁽⁰⁾ ＋ Vy ⁽¹⁾ ＋ Vy ⁽²⁾ …… (6 ) Is. The motion vectors V _X and V _Y thus obtained are stored in the memory 51 and, at the same time, output to the next motion vector averaging circuit 14.

In addition, between the output of the switching circuit 12e and the arithmetic circuits 52, 54,
In order to reduce the calculation error of the gradient method due to noise,
A smoothing circuit for smoothing may be inserted. The smoothing circuit performs a calculation of the following formula for the pixels a _{1 to} a ₄ adjacent to the reference pixel a ₀ and outputs the smoothing output A ₀ . The positional relationship of the pixels a ₀ , a _{1 to} a ₄ is shown in FIG. 9 (b).

Also, instead of this smoothing circuit, a two-dimensional low-pass filter with a large number of taps may be used.

The motion vector averaging circuit 14 averages the motion vectors from the motion detecting circuit 13 in order to eliminate motion vector errors. As an example of averaging, several horizontal blocks and several vertical blocks centering on the current block are used as the motion vector, and the averaged vector is output to the motion vector determination circuit 15 as the motion vector.

In the motion vector determination circuit 15, the motion vector detection circuit
The motion vector obtained from 13 through the motion vector averaging circuit 14 is determined. As an example of this determination, the absolute value of the signal difference between the fields, which has been position-corrected by the detected motion vector, is calculated, and the value is accumulated by 32 pixels of 8 pixels × 4 lines (denoted as γ ₁ ). And calculate the absolute value of the difference between the fields without motion compensation, and use it in the same way as above.
Compared with the value obtained by accumulating 32 pixels (assumed to be γ ₂ ) and γ ₁ > γ
_In the case of _2, the motion vector is invalid and "0" is output. If γ ₁ <γ ₂ , the motion vector is valid and the motion vector is output.

FIG. 11 is a block diagram showing an internal configuration example of the motion vector determination circuit 15. The motion vector determination circuit 15 in FIG.
Three memories 151a to 151c, two subtraction circuits 152a and 152b,
Correction circuit 153, absolute value circuit 154, two accumulation circuits 155a and 155
b, composed of a comparison circuit 156 and a selection circuit 157. Among the output signals of the switching circuit 12e, the current field signal is input to the memory 151a and the subtraction circuit 152b, and the previous field signal is input to the memory 151b and the subtraction circuit 152b. Memory 15
The operations of 1a and 151b are similar to those of the memories 522a to 522f in FIG. However, the other input here is not the motion vector itself, but a motion vector having a value obtained by applying a field interpolation ratio in the motion vector correction circuit 153 as shown in FIG. The state of this motion vector correction is shown in FIG. In the figure, β, 1-β is the field interpolation ratio, 121
Is the block (reference block) on the interpolation field, 12
2 is a block of motion “0” on the previous field, 123 is a block of motion “0” on the current field, 124 is a motion compensation block on the previous field, 125 is a motion compensation block on the current field, and 126 is detected. Motion vector (B), 127 is a field interpolation corrected motion vector (B ⁺ =
-(1-β) B), 128 is a field interpolation correction motion vector (B ⁻ = βB) of the previous field. Subtraction circuit 152b
Then, the field difference is calculated for the pixels of the current field and the previous field, and the output is input to the memory 151c.
The operation of this memory is similar to that of the memory 521 shown in FIG. The output signals of the memories 151a and 151b calculate the difference between the signal of the current field whose motion has been corrected by the subtraction circuit 152a and the previous field whose motion has been corrected, and the output thereof is the absolute value circuit 154.
Is converted to an absolute value. Thereafter, the signal converted into the absolute value is input to the comparison circuit 156 after the accumulation circuit 155 has accumulated 32 pixels. The output signal of the memory 151c is the accumulator circuit 155b.
At 32, accumulation of 32 pixels is performed, and the result is input to the comparison circuit 156. The comparison circuit 156 compares the sum of the absolute values of the inter-field differences that have been motion-compensated, and the magnitude of the sum of the absolute values of the inter-field differences that have not been motion-corrected. The motion vector output from the motion vector selection circuit 157 is set to "0". On the other hand, if the motion-corrected inter-field difference is smaller, the selection circuit 157 outputs the motion vector.

Since the motion vector determined in this way is a block unit, it is necessary to make this correspond to the scanning line. The memory 16 has this conversion function, and performs an operation opposite to that of the memory 521 in the selection circuit 52 shown in FIG. That is, the signal for each block from the motion vector determination circuit 15 is converted into a signal for each scanning line by controlling the memory address, and FIG. 13 shows this in the figure. Since the detected motion vector is output for each block, if these are B ₁ , B ₂ , and B ₃ , the temporal length of B ₁ is 8 pixels × 4 lines (32 pixels) or more. (Motion vector detection is 8 pixels × 8 lines, but since the block for motion vector determination is 8 pixels × 4 lines, the motion vector during field interpolation is 8 pixels × 4 lines). The memory 16 converts the arrangement and outputs it as a block B ₁ (8 pixels) and a block B ₂ (8 pixels) for each scanning line as shown in FIG.

FIG. 14 is a block diagram showing an example of the internal configuration of the field interpolation circuits 17a and 17b. The field interpolation circuit 17a in FIG.
17b is two memories 171 having a capacity of 1 (n or more) lines.
a, 171b, a correction circuit 172 that corrects a motion vector, and a calculation circuit 173 that performs a field interpolation calculation. The memories 171a and 171b have a function of delaying the output signal of the line interpolation circuit by the time required for detecting the motion vector, and read according to the motion vector corrected by multiplying the motion vector by the field interpolation ratio in the correction circuit 172. There is a function of moving the position of the signal to be read by controlling the address. The motion vector correction circuit 172 multiplies the input motion vector by the field interpolation ratio, and the relationship between the corrected motion vectors is the same as B ⁺ and B ⁻ shown in FIG. However, in FIG. 14, memory 1
The input signal of 71a, 171b is the switching circuit 12a, 12b or 12 of FIG.
These are output signals of c and 12d, and are not output signals of the switching circuit 12e. Therefore, in the input signals of the memories 171a and 171b, there is no distinction between the current field and the previous field. Therefore, the sign of the motion vector corrected by the field interpolation ratio of the other input of the memories 171a and 171b is also controlled depending on which signal is earlier in time. That is, in the figure,
The field interpolation ratio β, 1-β is switched by the same signal as the switching signal input to the switching circuit 12e, and the motion vector corrected by β is read to the memory 171a (or 171b) storing the current field signal. Send to control the address,
The memory 171b (or 17 that stores the signal of the previous field
The motion vector corrected by 1-β is sent to 1a) for read address control. The arithmetic circuit 173 is composed of two multipliers and an adder for adding these outputs, and performs correction by linear interpolation used in the conventional TV system converter. Therefore, the switching circuits 12a, 12 on the Y signal side
From b to the corresponding memories 171a and 171 of the field interpolation circuit 17a
The Y signals are stored in b, and these signals are position-corrected by changing the read address by the corrected motion vector from the correction circuit 172 and read, and then the arithmetic circuit.
Field interpolation is performed at 173 and output. Similarly, on the C signal side, after the C signals are stored in the corresponding memories 171a and 171b of the field interpolating circuit 17b from the switching circuits 12c and 12d, position correction is performed at the time of reading these signals, and then the arithmetic circuit. Field interpolation is performed at 173 and output.

As described above, input component signals Y, RY, BY
Is converted into the output component signals Y and C.

When a digital encoder is used, the signal after field interpolation is input to the digital encoder circuit as it is, but when an analog encoder is used, it is converted to an analog signal by the D / A conversion circuit and then sent to the encoder. input. Encoder is NTSC, PAL, SECAM, PAL
There are M etc., and an encoder is selected according to the output side method.

FIG. 15 is a block diagram of a TV system converter showing a second embodiment. The difference from the first embodiment is as shown in FIG.
The memory for converting the number of scanning lines is a memory of 3 field capacity.
A switch 19 is provided for rearranging the signals of the fields read in parallel from the memory 18 in order of earliest time, and the motion detecting circuit 4 is arranged to detect the motion from the signal of the switch 19 one frame away. That is the point. Therefore, the delay circuits 5a and 5b on the input side in FIG. 1 are unnecessary.

In the above-described embodiment, the interpolation processing of the Y signal and the C signal constitutes exactly the same processing method, but the processing of the C signal is slightly simplified as compared with the Y signal, but the difference in image quality is small. In consideration of downsizing and cost reduction of the device, it is desirable to simplify the processing of the C signal system.

As an example of this, (1) a method of performing line interpolation using a digital filter for the Y signal and direct interpolation of two adjacent lines between the fields for the C signal in the line interpolation processing method, (2) Only the Y signal system uses the motion adaptive line interpolation method, and the C signal system has two adjacent fields in the field.
It is conceivable to use only linear interpolation between lines.

 Further, the motion vector averaging circuit 14 may be deleted.

Further, in the present embodiment, the correction circuits 172 are provided inside the field interpolation circuits 17a and 17b, respectively, but they are provided as a correction circuit common to the output of the memory 16, and the movements corrected by the field interpolation ratio by this correction circuit are provided. Vector is Y signal side, C
It may be sent to the memory of the field interpolation circuit on the signal side.

(Effect of the Invention) As described in detail above, according to the present invention, a motion vector is detected on the luminance signal side, and position correction is performed on a moving image of a luminance signal and a color difference signal according to the detected motion vector. Since the field interpolation is performed after performing the above, it is possible to smoothly correct even an image in which a parallel moving image has a wide moving image area.

[Brief description of drawings]

FIG. 1 is a block diagram of a TV system converter showing a first embodiment of the present invention, FIG. 2 is an enlarged view of a diagonal pattern, FIG. 3 is an explanatory view of line interpolation in a field, and FIG. FIG. 5 is an explanatory diagram of line interpolation between fields, FIG. 5 is a configuration diagram of a main part of a motion vector detection circuit, FIGS. 6 (a) and 6 (b) are explanatory diagrams of blocks and candidate vectors, and FIG. 7 is a selection circuit. Internal configuration diagram,
FIG. 8 is an operation explanatory diagram of the memory, FIGS. 9A and 9B are positional relationship diagrams of the reference pixel and the adjacent pixel, FIG. 10 is an internal configuration diagram of the arithmetic circuit, and FIG. 11 is a motion vector determination circuit. Internal configuration diagram of FIG. 12, FIG. 12 is an explanatory diagram of motion vector correction, FIG. 13 is an explanatory diagram of operation of a memory for line conversion, FIG. 14 is an internal configuration diagram of a field interpolation circuit, and FIG. 15 is the present invention. FIG. 16 is a block diagram of a TV system converter showing a second embodiment of the present invention, FIG. 16 is a block diagram of a conventional TV system converter, and FIG. 17 is a conventional motion detection circuit.
It is a block diagram of a TV system converter. 1a, 1b, 1c …… input terminal, 2a, 2b …… output terminal, 3,5a, 5b…
... delay circuit, 4 ... motion detection circuit, 6 ... multiplex circuit, 7,
8a, 8b, 16,18,51,151a to 151c, 171a, 171b, 521,522a to 522
f, 534a to 534d ... Memory, 9 ... OR circuit, 10a to 10d, 11
a, 11b ... Line interpolation circuit, 12a-12e, 527a-527d ... Switching circuit, 13 ... Motion vector detection circuit, 14 ... Motion vector averaging circuit, 15 ... Motion vector determination circuit, 17a, 17
b …… Field interpolation circuit, 19 …… Switch, 52,157 ……
Selector circuit, 53,55,173 ... Operation circuit, 54,56 ... Adder,
152a, 152b, 523a to 523f, 533a to 533c ... Subtractor, 154,524
a to 524f, 535a, 535b ... Absolute value circuit, 155a, 155b, 525a to 5
25f, 536a to 536d ... accumulation circuit, 156,526a to 526e ... comparison circuit, 537a, 537b ... sign arithmetic circuit, 538a, 538b ... fractional circuit, 539a, 539b ... multiplication circuit, 153,172 ... correction circuit .

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hirohisa Yamaguchi 2-3-2 Nishishinjuku, Shinjuku-ku, Tokyo International Telegraph and Telephone Corporation (56) References JP-A-61-32681 (JP, A) Special Features Kai 60-158786 (JP, A) JP 60-25190 (JP, B2)

Claims (1)

(57) [Claims] 1. A first memory having a capacity of 2 fields or more and storing a digitized luminance signal, and a second memory having a capacity of 2 fields or more and storing a digitized and quantified color difference signal. Memory, first detection means for detecting the presence or absence of motion from one of the input signal and the output signal of the first memory based on the inter-frame difference of each pixel, and the first detection means.
Line interpolating means for performing line interpolation on the output signal of the first memory using the line information in the same field, and a line between two fields interlaced with the output signal of the first memory Second line interpolation means for performing line interpolation using information, and third line interpolation means for performing line interpolation using line information in the same field for the output signal of the second memory , A fourth line interpolation means for performing line interpolation using line information between two fields interlaced with the output signal of the second memory, and a first line detection means based on the detection result of the first detection means. First selection means for selecting one of the output signals of the first and second line interpolation means, and one of the output signals of the third and fourth line interpolation means based on the detection result. Second choice In a television standard conversion device including :, the output signal of the first selecting means, which is separated by one field, is divided into blocks of m pixels × n lines (m, n; integer), and each block is moved. A second detecting means for detecting a vector, and a valid motion vector detected by the second detecting means,
A determination unit that determines invalidity and outputs the motion vector at the time of validity determination, a conversion unit that converts the output signal of the determination unit into a motion vector corresponding to the scanning line, and an output signal of the first selection unit. The third with the capacity of two l (n or more) lines to be stored corresponding to the field
And a fourth memory, and a fifth memory having a capacity of two l (n or more) lines for storing the output signal of the second selecting means corresponding to each field.
And a sixth memory, and the read address is changed by the value of the product of the motion vector from the conversion means and the field interpolation ratio, and the third to sixth memories are changed.
Correction means for outputting the contents of the memory, first field interpolation means for performing field interpolation on the output signals of the third and fourth memories, and field output signals of the fifth and sixth memories. A television standard conversion apparatus, comprising a second field interpolation means for performing interpolation.