JPH01307870A - Control system for vector processor - Google Patents

Abstract

PURPOSE:To perform the vector processing without wasting time neither excessively suppressing instructions unrelated to conflict by using a simple control mechanism for the processing of a succeeding instruction conflicting with the preceding instruction. CONSTITUTION:If conflict is detected while a vector register 7 or the like used for instruction execution is used by the preceding instruction, this information is added to the start element of the vector instruction and is flowed to an objective pipeline processing mechanism. The pipeline processing mechanism detects information to stop the processing in a pipeline stage above the stage of access to the vector register 7. The instruction processing assigned to the pipeline is stopped and access to the register 7 is stopped to avoid conflict. An instruction execution control mechanism reports resolution of conflict to the pipeline processing mechanism to restart the processing when detecting solution of conflict, and the vector register can be accessed without conflict not to waste time. When a conflict information counter is provided, loss of conflict solution information is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a vector processing device comprising a plurality of pipeline processing mechanisms. The present invention relates to a control method for a vector processing device that is suitable for eliminating vector instructions and efficiently processing vector instructions.

[Conventional technology]

When executing a vector instruction in a vector processing device consisting of multiple pipeline processing mechanisms and multiple vector registers, the processing device must determine in advance the pipeline processing mechanisms (also called resources) and vector registers used by the instruction. It is necessary to check whether it is in the "empty" state. If these are not in the "empty" state (this is called a resource conflict or register conflict), execution of the instruction will be delayed.

When such a conflict occurs, idle time occurs in resources and registers to which subsequent instructions are allocated, which reduces system performance. As a conventional technique for improving this performance degradation, for example, a technique called "chaining" is known. This technique processes so that even if writing to the vector register by the preceding vector instruction is not completed, the written element can be read by the subsequent instruction. In other words, processing is performed by connecting two pipelines (chain). This chaining can suppress the occurrence of wasted idle time in the pipeline processing mechanism due to register conflicts.

The technology related to chaining is described in "Nikkei Electronics, 1984.11.19, pages 262 to 264" and "Nikkei Electronics, 1983.
．． 4.11, pages 147 to 148" are known.

Furthermore, as a measure to prevent processing device performance from deteriorating in the event of a resource conflict, a method has been proposed in which each resource is provided with a buffer for the next instruction to be executed, and the next instruction is executed immediately after the currently executed instruction is completed.

This technique eliminates wasted time in transmitting and receiving control signals between an instruction activation management circuit and resources, thereby preventing performance degradation of the processing device.

[Problem to be solved by the invention]

However, the prior art does not take into account chaining of write operations to vector registers that are being executed one after another. That is, in the prior art, the issuance or execution of subsequent instructions that write into the vector register is inhibited until the successive writing of the vector register by the preceding instruction is completed, and in cases other than the above,
For example, the issuance or execution of subsequent instructions is inhibited even when a conflict occurs due to registers being issued by a subsequent instruction while registers are being issued by a preceding instruction, or by sharing of registers in a vector register peripheral circuit.

The vector instruction sequence when this is executed by a vector processing device is as follows. Here, VR is a vector register.

In this case, the VRO performs writing using the Load command and S
Although a conflict occurs when reading by the tore instruction, it can be avoided by using the chaining technique described above.

However, the situation changes when considering that the vector instruction is processed by a device with a maximum vector length of 50. In other words, since the vector instruction is hector processing with a vector length of 100, in a device with the vector length of 50, it is necessary to execute two of the vector instructions at the same time. The VRO will collide with the oad instruction.

In general, conflict avoidance in such cases is not performed because the implementation circuit of the technology equivalent to chaining becomes complicated. As a result, the second execution of the load instruction is
This means that the process will have to wait until the execution of the first Store instruction is completed.

However, in the pipeline processing mechanism, the processing that needs to be suppressed when a conflict occurs as described above is after the write operation to the vector register or the read operation from the vector register, and At the stage, it is possible to execute the processing of the instruction regardless of the conflict. In other words, in the pipeline processing mechanism, the conventional technology that inputs the subsequent instruction into the pipeline processing mechanism after the preceding instruction completely finishes accessing the vector register wastes idle time for stages unrelated to the conflict. Furthermore, even if instructions subsequent to the instruction whose issuance was suppressed due to a conflict do not cause a conflict, subsequent instructions are excessively stopped, which causes the processing system to This has the problem of causing a decrease in overall performance.

An object of the present invention is to prevent wasteful idle time from occurring in the execution of a subsequent instruction that causes a conflict with a preceding instruction, and to avoid excessive execution of instructions unrelated to the conflict. Therefore, it is possible to provide a control method for a vector processing device that can prevent the vector processing device from being inhibited by using a relatively simple control mechanism.

[Means to solve the problem]

According to the present invention, the object is to include a circuit that detects the occurrence of a conflict, and when a conflict is detected, adds conflict information indicating that a conflict has occurred to the first element of a vector instruction. and a means for notifying the pipeline processing mechanism of the information when conflict resolution is detected. This is achieved by providing a control means that stops the line processing at a specific stage and restarts the pipeline processing when a conflict release notification is received. Furthermore, the above object is achieved by providing each pipeline processing mechanism with a count information counter by notification of conflict resolution.

[Effect]

When a vector processing device attempts to execute a vector instruction, if a conflict state is detected in which a vector register, etc. used by that instruction is being used by a preceding instruction, the conflict information is stored at the beginning of the vector instruction. It is attached to the element and flowed into the destination pipeline processing mechanism. When the pipeline processing mechanism detects the conflict information added to the leading element, it stops processing at a pipeline stage upstream from a stage that accesses a vector register or the like. As a result, processing of instructions assigned to the pipeline is stopped, and accesses to vector registers and the like are naturally also inhibited, thereby avoiding access conflicts. However, the pipeline processing of the vector instruction in which a conflict has been detected will proceed halfway.

Furthermore, when the instruction execution control mechanism detects that the conflict has been resolved, it notifies the pipeline processing mechanism of the resolution information. When the pipeline processing mechanism receives the conflict resolution information, it restarts the stopped pipeline processing.

This makes it possible to access vector registers, etc. without conflicting with accesses of preceding instructions, and to minimize the occurrence of wasted idle time in the pipeline processing mechanism due to conflicts. Become.

Furthermore, the conflict information counter operates to count up in response to a conflict resolution notification and count down in response to processing of a command with conflict information. If this count value is "0", the pipeline processing mechanism assumes that the conflict resolution notification has not arrived and stops the pipeline processing, and if the counter value is not "0", the pipeline processing mechanism discards the conflict resolution information. It is determined that the counter has arrived, and the counter is counted down.
Control the pipeline to proceed without stopping it.

By providing such a conflict information counter, before the first element of a vector instruction to which conflict information is added arrives at a specific stage of the pipeline,
It is possible to prevent the conflict resolution information from disappearing when the conflict resolution information notification arrives. Moreover, even when instructions with short vector lengths are consecutive and a conflict occurs, conflict information can be counted, so it is possible to expand the scope of application of pipeline processing using the tree method.

(Embodiment) Hereinafter, one embodiment of the control method of the vector processing device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a vector instruction execution control device and an access instruction processing device according to the present invention, FIG. 2 is a block diagram showing the overall configuration of the vector processing device, and FIG.
4 is a block diagram showing the structure of the vector instruction execution control device, FIG. 4 is a block diagram showing the structure of the access instruction control circuit, and FIG. 5 is a block diagram showing the structure of the access sending control circuit. 1 to 5, 1 is a scalar processing unit, 2 is a vector instruction execution control device, 3.4 is an access instruction processing device, 5 and 6 are arithmetic units, 7 is a vector register, 8 is a main memory control device, 9 is a main storage device, 20 is an instruction register, 21 is an instruction activation management circuit, 22 is a state management circuit, 33 is an access instruction control circuit, 34 is an access request sending control circuit, 210, 212, 219 are decoding circuits, and 220 is a decoding circuit. Pipeline processing mechanism state management circuit, 221
346 is a vector register state management circuit, 346 is a conflict information detection circuit, and 353 is a non-zero detection circuit.

In the overall configuration of the vector processing device according to the present invention shown in FIG.
．． 6 is constituted by a pipeline processing mechanism.

A vector instruction sent from the scalar processing unit l, which is a normal central processing unit, is decoded by the vector instruction execution control unit 2, and the corresponding free pipeline in the access instruction processing unit 3.4 and the arithmetic units 5 and 6 is processed. Start the processing mechanism. The access command processing devices 3 and 4 control data transfer between the vector register 7 and the main storage device 9, and the vector register 7 stores a plurality of vector data. The main memory control device 8 receives access requests from the access command processing devices 3 and 4,
The main storage device 9 is accessed according to the access request.

The vector instruction execution control device 2, as shown in FIG.
an instruction register 20 for receiving vector instructions from the scalar processing unit 1; an instruction activation management circuit 21 for decoding the instructions in the instruction register 20 and activating the corresponding pipeline processing mechanism; It is composed of a state management circuit 22 that manages the state and provides information to the instruction activation management circuit 21. On the other hand, the access instruction processing device 3 is composed of four stages: an address calculation stage (2), an address conversion stage (2), an exception detection stage (2), and a request sending stage (2). The register 30a is a base address register VBR that holds the base value of the address of the access instruction sent from the vector instruction execution control device 2, and the register 30b is an increment register VBR that holds the increment value for determining the address of each vector element. Address register ViR. The address of the vector element corresponding to the access command is obtained by passing the address adder 32 with the first element as the value of the VBR 30a, and setting this in the address register 35a.
and ViR30b are sequentially generated. The address conversion mechanism 36 is a mechanism for converting the logical address found in the register 35a into an execution address, and can be realized by hardware such as a conversion table consisting of conversion pairs of logical addresses and real addresses.

The register 37a is a register that holds the real address after address translation, and the exception detection mechanism 38 detects addressing exceptions and storage protection exceptions of the translated address. The register 39a is a register that holds addresses after the exception is detected, and also functions as a request buffer for absorbing disturbances in request processing due to conflicts with requests from other access request control devices to the main storage device 9. . The access request sending control circuit 34 controls sending the request existing in the request buffer 39a to the main memory control device 8, and furthermore, when conflict occurrence information is detected at the exit of the request buffer 39a, the access request sending control circuit 34 sends the request existing in the request buffer 39a to the main memory control device 8. Until we receive a notice of conflict resolution from 2, the principal jI! It has a function to stop sending requests to the control device 8. The access command control circuit 33 holds the commands sent from the vector command execution control device 2, and the access command processing device 3
, 4, and controls the generation of access requests together with calculation instructions to the address adder 32. Registers 35b, 37b.

Reference numeral 39b is a register for a code indicating an access request and its type corresponding to the address registers of registers 35a, 37a, and 39a, respectively.

FIG. 3 shows details of the vector instruction execution control device 2. The state management circuit 22 includes a pipeline processing mechanism state management circuit 220 that maintains a busy state corresponding to a pipeline processing mechanism, and a vector register state management circuit 221 that maintains a busy state corresponding to a vector register. Each of the state management circuits 220 and 221 includes an instruction activation management circuit 21, a pipeline processing mechanism and a vector register 7.
The busy state is set at the time of startup, and the busy state is reset by notification of completion of processing from the pipeline processing mechanism or vector register 7.

The decoding circuit 210 in the instruction activation management circuit 21 is a circuit that decodes the instruction in the instruction register 20, and determines the pipeline processing mechanism and vector register used by the instruction. The comparison circuit 211 determines whether the pipeline processing mechanism determined by the decoding circuit 210 is in use, based on information from the state management circuit 220. As a result, if the target pipeline processing mechanism is "empty", the comparison circuit 211 provides an enable signal to the decoding circuit 215 via the gate 214, and sends an activation signal 2 to the pipeline processing mechanism.
15a is permitted. Further, if the target pipeline processing mechanism is "in use", the sending of the activation signal 215a from the decoding circuit 215 is inhibited, and at the same time, the sending of the instruction activation report 216b to the scalar processing unit 1 is also inhibited.

The comparison circuit 212 also determines whether the vector register determined by the decoding circuit 210 is in use or not by the state management circuit 22.
Judgment is made using the information from 1. As a result, if the target vector register is "empty", the comparator circuit 212
Enable 1 to the decoding circuit 215 via 217 and 214.
No. 8 is given, and the transmission of the activation signal 215a is permitted. Furthermore, even if the target vector register is "in use", if the flip-flop 213 indicating that the conflict generating instruction is already being executed is "0", the conflict-sensitive Ig 212a is added and the activation signal 215a is sent. If the flip-flop 213 is already at "L" and the output of the comparison circuit 212 also indicates that the vector register is "in use", the activation signal 215a is inhibited. The flip-flop 213 is set to "l" by activation of a conflicting instruction, and is reset when the conflict is resolved. In the embodiment of the present invention, in order to simplify the explanation, the pipeline processing mechanism is capable of accepting one instruction with conflict information, and the inhibition control of the activation signal 215a is based on the information of this flip-flop 213. Based on this.

According to the present invention, the pipeline processing mechanism can accept a plurality of instructions with conflict information.

In this case, the counter is counted up (or counted down) by the conflict resolution notification 241a instead of the flip-flop 213, and counted down (or counted down) by executing an instruction with conflict information.
It is possible to provide a counter that increases (up) and control the suppression of the activation signal 215a based on the value of this counter. For example, when the counter is counted up by a conflict resolution notification, the count value is “0”.
In this case, the activation signal 215a may be stopped by IrII.

Register 218 holds the number of the vector register causing the conflict.

The comparison circuit 240 is a circuit that compares the processing completion report from the vector register 9 and the hector registration disk number in which a conflict is occurring, which is held in the register 218.
If it loses, it sends the conflict resolution ill knowledge 241a to the pipeline processing mechanism, and resets the conflict ml block 213 which is currently being executed.

Also, at this time, since the hector register needs to be kept in a busy state, a signal obtained by inverting the output of the decoding circuit 244, which uses the signal 241a as a permission signal, is supplied to the AND gate 222. This prevents a busy reset of the vector register.

The decoding circuit 219 is a circuit for decoding the register number of the instruction decoding circuit 210 and setting the vector register state management circuit 221 to a "busy state". Further, the decoding circuit 215 is a circuit for decoding the number of the pipeline processing mechanism output from the decoding circuit 210 and sending the activation number 13 to the target Babe line processing mechanism. Note that gates 216, 217, 241, and 242 are AND gates, gate 214 is a NOR gate, and gate 243 is an inversion gate.

FIG. 4 shows details of the access command control circuit.

In FIG. 4, an activation signal 215a sent from the instruction activation management circuit 21 of the vector instruction execution control device 2 sets a busy flip-flop 332 indicating that an access instruction is being processed. Along with this, the code (including conflict existence information) indicating the type of access request accompanying the activation signal 215a and the vector length are set in the registers 330 and 331, respectively.
is set to The value of the vector length register 331 increases the number of sent access requests 320a by “+1” to the circuit 335.
and the value of the counter consisting of the register 334 and the comparison circuit 33
6 is compared. When the two values match, that is, when an access request for the specified vector fraction is sent, an instruction processing completion notification signal 336a is sent to the vector instruction execution control device, and the busy flip-flop 332 is reset and Execution vector length register 334
The value of is initialized to "0". On the other hand, access request 32
0a must be sent while determining the access request processing status within the access command processing device. For this reason, the number of issued requests and the number of access requests sent to the main memory control device 8 are monitored to prevent the request buffer 39a in the final stage of the access instruction processing device 3 from overflowing. . The value of the buffer count register 337 is initially reset to "0", and when the access request 320a is sent, the count value is incremented by "+1" by the adder 338.
It is set in register 377.

The value of this register 337 and the request buffer 39a
A comparison circuit 339 compares the number of A (in this embodiment, four) and if they match, the A
The ND gate 320 suppresses sending of the access request 320a. Further, upon receiving a signal 8a from the access request sending control circuit 34 indicating that one access request has been sent to the main memory control device, the adder 338 decrements the number of access requests in the register 337 by one.

FIG. 5 shows details of the access request sending control circuit 34.

In FIG. 5, the code (including conflict information), address, data, etc. associated with the access request 34a sent from stage 3 in the access instruction processing device 3 are set in the request buffer 39a and register 39b. Ru. The buffer position to be set at this time is indicated by a signal obtained by decoding the value of the inpointer register 340 by the decoding circuit 342, and the value of the inpointer is changed to "+l" in the adder 341 every time an access request 34a is sent. ° In addition, in pointer register 3
40 takes values from '0'' to '3', and after '3' is '0'
wrapped around. The access request set in the buffer 39a and the register 39b is sent to the selection circuit 390 from the buffer position indicated by the signal obtained by decoding the value of the out pointer register 343 by the decoding circuit 345.
・Taken out through 391. The access request taken out from the buffer 39a and the register 39b is sent to the main memory control device 8 as an access request 350a via an AND game 350 unless it is accompanied by conflict information. At the same time, codes, addresses, data, etc. associated with the access request are sent to the main memory control device 8 from the buffer 390a and register 391a'. The sent access request 350a may not necessarily be issued immediately due to the state of the main storage device or conflicts with other access requests.
There is no guarantee that the control device 8 will accept the request. For this reason, the main memory control device 8 includes a priority determining circuit therein, determines the priority, and returns an accept signal 8a notifying the priority.

When the access request sending control circuit 34 receives this accept signal 8a, it increments the value of the out pointer register 343 by "+1" using the adder 344, and also informs the access command control circuit 33 that one access request has been processed. This is notified by directly transmitting the above-mentioned accept signal 8a. On the other hand, when the detection circuit 346 detects that the access request taken out from the buffer 39a and the register 39b is a conflict request, the transmission of the access request 350a is inhibited through the inverting gate 347 and the OR gate 1349. However, even in this case, if the conflict information count register 351 is not "0", the access request 350a is sent. At the same time, the value of the conflict information count register 351 is
“1” is subtracted through adder 352. The value of this conflict information count register 351 is sent to the conflict resolution notification 241a from the instruction activation management circuit, t;
"1" is added.

The above is an overview of the configuration and operation of the vector instruction execution control device and the access instruction processing device according to the present invention. Next, the flow of processing will be explained by citing one vector instruction sequence.

As a vector instruction sequence, the above-mentioned Load ・S
Consider the following instruction sequence that executes two tore instructions.

First, the first load instruction is assigned to the access instruction processing device 3 and executed. The Store instruction uses the same vector register as the preceding Load instruction, but it uses chaining processing (not shown) that defines writing and reading to the vector register as a series of processing.
Accordingly, the access instruction processing device 4 executes writing from the vector register VRO to the main storage device. Next, when attempting to execute the second Load instruction, the management circuit 220 of the pipeline processing mechanism will
In order to indicate that the pipeline processing mechanism 3 is in use, activation of this instruction is performed by the comparison circuit 211 and the NOR gate 21.
4. Inhibited through decoding circuit 215. 1st L
When the processing of the oad instruction is completed and the management circuit 220 indicates that the access instruction processing device 3 is "empty", the inhibiting factor for starting the instruction related to the pipeline processing mechanism is removed. On the other hand, vector register conflicts are not resolved until the processing of the first Store instruction is completed. However, in the case of the above embodiment, it is assumed that the conflicting instruction is being executed at this point. Therefore, the activation signal 215a can be sent to the access command processing device 3 with the conflict presence signal 212a added thereto. Therefore, when the activation signal with the conflict presence signal 212 added is sent to the access command processing device, the flip-flop indicating that the conflict presence instruction is being executed becomes "1".
is set to As a result, subsequent instructions with a conflict will be suppressed until the read operation from the vector register by the first STORE instruction is completed and the conflict is resolved.

The access command control circuit 33 of the access command processing device 3 that receives the activation signal 215a sends the access request through the pipeline. However, conflict existence information is added to the activation signal and is set in the code register 330. Since the access instruction control circuit 33 adds conflict information to the access request at the head of the instruction and does not add it thereafter, it resets the conflict information in the code register 330 with the signal 320a at the same time as sending out the head element.

The access request sending control circuit 34 takes in the access request flowing from the upstream stage into the buffer 39a and the register 39b, and at the same time takes out the access request in the buffer 39a and the register 39b, and checks whether or not there is a conflict interest. .

Conflict information is added to the first access request corresponding to the second load instruction, and at this point, the instruction activation management circuit 21 sends the conflict notification 1 to resolution notification 24.
1a is not sent, that is, if the conflict information count register 351 indicates "0", the sending of the access request 350a is suppressed, and the processing of the access instruction processing device 3 is performed at this access request stage. , will be stopped. On the other hand, when the first store command finishes reading the VRO,
The notification is sent to the instruction activation management circuit 21, and the comparison circuit 2
40, a conflict resolution notification 241a is sent to the access command processing device 3 via the ΔND game 1-241.

When the access transmission control circuit 34 receives this conflict l-resolution notification 241a, the circuit 34 sets the value of the conflict information count register to "1". As a result, the transmission of the suppressed access request 350a is restarted, the 1 shift of the conflict information II count register 351 is decremented by "1", and the stopped processing of the access command processing device is restarted.

Furthermore, the conflict resolution notification 241a is sent to the access sending side j′J earlier than the access request with conflict information.
If the access request with conflict information is retrieved from the buffer 39a and register 39b, the access request 350a is immediately sent to the main memory control device 8, and the conflict information (and count) is sent to the main memory control device 8. The value of the register 351 is decremented by "1" and the conflict-related process is performed.

As described above, it is possible to realize a control method that advances processing to an intermediate stage of the pipeline even for instructions in which a conflict has occurred.

〔Effect of the invention〕

As explained above, according to the present invention, even if the resources (vector registers, pipeline processing mechanism, etc.) used by the instruction to be executed are already in use by the preceding instruction (conflict I/state), Since pipeline processing can be advanced to the stage immediately before the stage that actually uses the resource, it is possible to process instructions without wasting idle time in the pipeline processing mechanism. Furthermore, it is possible to avoid a situation in which an instruction subsequent to the instruction in which a conflict has occurred is made to wait excessively due to the execution of the preceding instruction, and it is possible to suppress the occurrence of wasted idle time in issuing instructions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a vector instruction execution control device and an access instruction processing device according to the present invention, FIG. 2 is a block diagram showing the overall configuration of a hector processing device, and FIG.
4 is a block diagram showing the structure of the vector instruction execution control device, FIG. 4 is a block diagram showing the structure of the access joint capital control circuit, and FIG. 5 is a block diagram showing the structure of the access transmission control circuit. ■・・・・・・Scalar processing unit, 2...
...Hector command execution control device, 3, 4...
...Access command processing device, 5, 6...
...Arithmetic unit, 7...Vector register, 8...Main memory control unit, 9...
...Main storage device, 20...Instruction register, 21...Instruction activation management circuit, 2
2. ......State management circuit, 33...
...Access command control circuit, 34...
・Access request sending control circuit, 213...
・Indication flip-flop when conflicting instruction is being executed,
210°212.219・・・・・・Decoding circuit,
220...Vibeline processing mechanism state management circuit, 221...\Vector register state management circuit, 240...Conflict I
- Comparison circuit for creating canceled signal, 351...
21 conflict information count register, 346...
...Conflict information detection circuit, 353...
・・・・・・Non-blame detection circuit. Figure 2 Figure 4 334: Thrust base 7 length register 335: ・1@Route 338: go calculation

Claims (1)

[Claims] 1. A vector register that holds data of multiple elements;
A vector that includes a plurality of pipeline processing mechanisms that sequentially process multiple elements of data held in the vector register, and that processes the data by assigning individual vector instructions to each pipeline processing mechanism. In a processing device, a conflict detection mechanism detects a conflict state in which a resource specified by an instruction assigned to each pipeline is being used by a preceding instruction, and when the mechanism detects a resource conflict state, a mechanism that adds conflict information indicating a conflict state to an element of the instruction and sends it to the pipeline processing mechanism; and when the conflict detection mechanism detects resolution of the conflict state, this resolution information is sent to the pipeline processing mechanism; 1. A control method for a vector processing device, comprising: a mechanism for notifying a mechanism. 2. When the pipeline processing mechanism detects conflict information added to the instruction, it stops the pipeline processing of the instruction at a specific stage, and when the conflict resolution is notified, the pipeline processing mechanism that had been stopped stops. A control method for a vector processing device according to claim 1, characterized in that processing is restarted. 3. The pipeline processing mechanism is provided with a counter that is controlled by the conflict resolution notification and the completion of processing of instructions with conflict information, and the value of this counter determines the number of times the plurality of messages are sent to the pipeline processing mechanism one after another. A control method for a vector processing device according to claim 1 or 2, characterized in that the method controls execution of an instruction. 4. The counter counts up (or down) in response to the conflict resolution notification, and counts down (or counts down) in response to the processing of the conflict information attached command.
or up), and the pipeline processing mechanism is
If the value of this counter is not a predetermined value, pipeline processing will not be stopped even if an instruction with conflict information reaches a specific stage, and if the value of this counter is a predetermined value, the instruction with conflict information will not be stopped. Claim 3, characterized in that the processing is stopped at a specific stage.
Control method of the vector processing device described in Section 1.