JPH01305551A - Lead frame for semiconductor device and semiconductor device - Google Patents
Lead frame for semiconductor device and semiconductor deviceInfo
- Publication number
- JPH01305551A JPH01305551A JP13686388A JP13686388A JPH01305551A JP H01305551 A JPH01305551 A JP H01305551A JP 13686388 A JP13686388 A JP 13686388A JP 13686388 A JP13686388 A JP 13686388A JP H01305551 A JPH01305551 A JP H01305551A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- plating
- lead frame
- plating layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000007747 plating Methods 0.000 claims abstract description 73
- 229910052718 tin Inorganic materials 0.000 claims abstract description 12
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 11
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 239000003566 sealing material Substances 0.000 claims description 2
- 239000011347 resin Substances 0.000 abstract description 13
- 229920005989 resin Polymers 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 11
- 238000007789 sealing Methods 0.000 abstract description 10
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000035515 penetration Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 26
- 239000010949 copper Substances 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000002585 base Substances 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005238 degreasing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009429 electrical wiring Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000002335 surface treatment layer Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910001096 P alloy Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000012733 comparative method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- PEVJCYPAFCUXEZ-UHFFFAOYSA-J dicopper;phosphonato phosphate Chemical compound [Cu+2].[Cu+2].[O-]P([O-])(=O)OP([O-])([O-])=O PEVJCYPAFCUXEZ-UHFFFAOYSA-J 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005554 pickling Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 208000024891 symptom Diseases 0.000 description 1
- RYCLIXPGLDDLTM-UHFFFAOYSA-J tetrapotassium;phosphonato phosphate Chemical compound [K+].[K+].[K+].[K+].[O-]P([O-])(=O)OP([O-])([O-])=O RYCLIXPGLDDLTM-UHFFFAOYSA-J 0.000 description 1
- VPKAOUKDMHJLAY-UHFFFAOYSA-J tetrasilver;phosphonato phosphate Chemical compound [Ag+].[Ag+].[Ag+].[Ag+].[O-]P([O-])(=O)OP([O-])([O-])=O VPKAOUKDMHJLAY-UHFFFAOYSA-J 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体装置用リードフレームおよびそれを用
いた半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor device and a semiconductor device using the lead frame.
［従来の技術］
従来の半導体装置について、その製造手順に従って説明
する。[Prior Art] A conventional semiconductor device will be explained according to its manufacturing procedure.
従来、半導体装置用リードフレーム材料としては、Ｃｕ
合金やＦｅ−Ｎｉ合金が用いられている。この半導体装
置用リードフレームは、少７２ くとも半導体素子接合
部および半導体素子部より電気接続配線されるインナー
リード部にはＡｇめフきが施され、場合によっては全面
にＡｇめっきか施される。Conventionally, Cu has been used as a lead frame material for semiconductor devices.
alloys and Fe-Ni alloys are used. This lead frame for semiconductor devices has at least 72 Ag plating applied to the semiconductor element junction area and the inner lead part to which electrical connections are made from the semiconductor element part, and in some cases, Ag plating is applied to the entire surface. .
次に、この半導体装置用リードフレームの半導体素子接
合部に、半導体素子を、加熱接合（ダイポンディング）
により接合する。このタイボンデインクは、Ａｇ−５ｉ
共晶、Ａｕ−３ｉ共晶やダイポンディングＡｇベースト
を用い、非酸化性カス７囲気あるいは還元籾、カス７囲
気中において、２００℃〜４５０ｔの温度で行われる。Next, the semiconductor element is heat bonded (die bonding) to the semiconductor element joint part of this semiconductor device lead frame.
Join by. This tie bond ink is Ag-5i
Using a eutectic, an Au-3i eutectic, or a die-ponding Ag base, it is carried out at a temperature of 200° C. to 450 t in an atmosphere of non-oxidizing waste 7 or reduced rice and waste 7.
次いて半導体素子の電極部とリードフレームの間をＡｕ
ワイヤて配線し、その後半導体素子部および電気接続配
線部を樹脂封止する。最後にアウターソート８１３をＳ
ｎあるいはＳｎ合金てめっきし、半導体装置が完成する
。Next, Au was applied between the electrode part of the semiconductor element and the lead frame.
After wiring, the semiconductor element part and the electrical connection wiring part are sealed with resin. Finally, set outer sort 813 to S.
After plating with n or Sn alloy, the semiconductor device is completed.
しかし、この様な従来の半導体装置には、以下のような
問題点かあった。However, such conventional semiconductor devices have the following problems.
■ソー１〜フレームの半導体素子部および配線部をめっ
きする工程、半導体素子を接合し電気接続配ＦＡ後樹脂
封止を行う半導体組立て工程、リードフレームのアウタ
ー９−１・部をめっきする工程等、複４！Ｉｆな工程を
経る必要かあり、コスト高の原因となっていた。■The process of plating the semiconductor element part and the wiring part of the saw 1 to frame, the semiconductor assembly process of joining the semiconductor elements and sealing them with resin after electrical connection FA, the process of plating the outer part 9-1 of the lead frame, etc. , double 4! It may be necessary to go through an additional process, which causes high costs.
■樹脂封止後めっきすることにより、酸、アルカワおよ
び水分が樹脂封止内部に侵入し、＃′−導体装置か動作
不良を起こす場合かあっｔコ。- If plating is performed after resin sealing, acid, alkali, and moisture may enter the resin seal and cause malfunction of the #'-conductor device.
上記の問題を解決するため、あらかじめアウターリード
部のめっきを行ったり−１−フレームを用いて組立てた
半導体装置（特公昭５８−１６３３９）か提案されてい
る。これは、近年グイホンディングペーストを用いるこ
とにｊこりタイボンデイックか２００〜２５０℃の比較
的低い温度でてきるようになったため可能となりたもの
である。In order to solve the above problems, a semiconductor device (Japanese Patent Publication No. 16339/1983) has been proposed in which the outer lead portion is plated in advance and the semiconductor device is assembled using a -1-frame. This has become possible because in recent years, it has become possible to use guihonding paste at a relatively low temperature of 200 to 250°C.
特公昭５８−１６３３９に開示さねた半導体装置は、り
下の構成を採ることを々、！ｌ徴としている。The semiconductor device disclosed in Japanese Patent Publication No. 58-16339 adopted the following structure! It is considered to be a symptom.
■アウターリード部に５１１を含むめ一部き層（第１の
めっき層）が設置、Ｊられていること。■A plating layer (first plating layer) containing 511 is installed on the outer lead part.
■半導体素子か１を賊される部分と、インナーソー１一
部の接続線が配線される部分の、−カまた幻両方に、Ｓ
ｎと合金化する金属を含むめっき層（第２のめっき層）
か設Ｃづらｈでいること。■In both the part where the semiconductor element 1 is stolen and the part where some connection wires of the inner saw 1 are wired,
Plating layer containing metal that alloys with n (second plating layer)
To be in a good position.
■前記第１のめっき層と前記第２のめ−）き層の間に不
連続部、即ち第１のめっき層も第２のめっき層も設ζプ
らねていない部分があること。(2) There is a discontinuous portion between the first plating layer and the second plating layer, that is, a portion where neither the first plating layer nor the second plating layer is provided.
■不連続部の少なくとも一部と、第２のめっき層が、半
導体素子封止材料で覆われていること。(2) At least a portion of the discontinuous portion and the second plating layer are covered with a semiconductor element sealing material.
不連続部を設ける理由は、ＡｇとＳｎの合金化により電
気接続配線部かもろくなり、信頼性か低下することを防
ぐためである。The reason for providing the discontinuous portion is to prevent the electrical connection wiring portion from becoming brittle due to the alloying of Ag and Sn, thereby preventing a decrease in reliability.
しかしこの半導体装置においては、以下のごとき新たな
問題点か発生した。However, in this semiconductor device, the following new problems have arisen.
即ち、第１の表面処理層と第２の表面処理層の間の不連
続部（リードフレーム本体の金属層）の表面が、半導体
組立て工程におけるグイボンディングやワイヤボンディ
ングおよび樹脂封止時の２００〜３５０℃の高温加熱Ｉ
Ａ埋において酸化し、この酸化膜の膜厚のむらにより、
ソートフレームの素地と樹脂封止の樹脂との密着性が悪
化するという問題である。この場合、使用環境において
、半導体装置に水分か侵入し、半導体装置か作動不良を
生しるおそれがある。That is, the surface of the discontinuous portion (metal layer of the lead frame main body) between the first surface treatment layer and the second surface treatment layer is 200 to 350℃ high temperature heating I
Oxidation occurs in the A-build, and due to unevenness in the thickness of this oxide film,
The problem is that the adhesion between the base material of the sorting frame and the resin for resin sealing deteriorates. In this case, there is a risk that moisture may enter the semiconductor device in the usage environment and cause the semiconductor device to malfunction.
このため、酸化を防止するために、非酸化性雰囲気にて
加熱するとの対策が考えられる。しかし、ずへての工程
に非酸化性ガスを使用することは困難であり、またコス
ト高ともなるため、有効な解決策とはいえない。Therefore, in order to prevent oxidation, heating in a non-oxidizing atmosphere may be considered. However, it is difficult to use a non-oxidizing gas in the subsequent steps, and it is also expensive, so it cannot be said to be an effective solution.
し発明か解決しようとする課題］
本発明は、以上説明した従来技術の問題を解決すめため
になされたものであり、低コストて半導体封止樹脂との
密着性を改善し、安価で信頼性の高い、半導体装置用ソ
ートフレームと当該半導体装置用リードフレームを用い
た半導体装置を提供するものである。[Problems to be Solved by the Invention] The present invention has been made in order to solve the problems of the prior art described above. The present invention provides a sorting frame for semiconductor devices that has high performance and a semiconductor device using the lead frame for semiconductor devices.
［課題解決のための手段］
本発明は、アウターリード部およびインナーリード部の
一部にＳｎあるいはＳｎ合金めっき層か設りられ、半導
体素子接合部および接続配線か接続されるリード部にＡ
ｇめっき層が設けられ、前記ＳｎあるいＳｎ合金めっき
層と前記Ａｇめっき層の間には不連続部か設けられた半
導体装置用リードフレームてあって、当該不連続部には
Ａｇを含有するＣｕめっき層か施されていることを特徴
とする半導体装置用リードフレームと、当該半導体装置
用リードフレームを用いた半導体装置に要旨か存在する
。[Means for Solving the Problems] The present invention provides a Sn or Sn alloy plating layer on a portion of the outer lead portion and the inner lead portion, and an A layer on the lead portion to which the semiconductor element bonding portion and the connection wiring are connected.
A lead frame for a semiconductor device is provided with a G plating layer, and a discontinuous portion is provided between the Sn or Sn alloy plating layer and the Ag plating layer, the discontinuous portion containing Ag. The subject matter is a lead frame for a semiconductor device characterized by being provided with a Cu plating layer, and a semiconductor device using the lead frame for a semiconductor device.
「作用］
本発明によれば、半導体装置用り一１〜フレームど封止
樹脂との密着性を良好ならしめることかできるので、該
半導体装［１り用リードフレームおよびこれを用いた半
導体装１１ｔのイ１］頼性を向上ざぜることかてきる。[Function] According to the present invention, it is possible to improve the adhesion between the lead frame for the semiconductor device and the encapsulating resin. 11t A1] Reliability can be greatly improved.
また、このとき、高価な非酸化４」−カスを用いる必要
かないのて、前記半導体装置用ソー１−フレームおよび
前記半導体装置を非常に安価に提供することができる。Further, at this time, since it is not necessary to use expensive non-oxidized scum, the semiconductor device saw frame and the semiconductor device can be provided at a very low cost.
Ａｇを含有するＣｕめっきか、素地との密着性の良好な
酸化皮膜を形成する理由は、種々の確認試験を行った結
果、以下の通り考えられる。As a result of various confirmation tests, the reason why Cu plating containing Ag forms an oxide film with good adhesion to the substrate is thought to be as follows.
Ａｇは酸素どの親和力が小さく、かつ酸化しても１６０
℃以」−の加熱において容易に酸素を放出する性質を有
している。そのため、Ａｇを含有したＣｕによるめっぎ
を２００〜３５０℃の温度範囲で加熱した場合、形成さ
れる酸化皮膜の膜厚は、Ａｇを含有しないＣｕめっきの
場合と比較して１／２程度に抑えれられる。従って酸化
膜の膜厚のむらの影響は小さくおさえられるわ番プであ
る。Ag has a small affinity for oxygen, and even when oxidized, it has a
It has the property of easily releasing oxygen when heated at temperatures below 10°C. Therefore, when Cu plating containing Ag is heated in a temperature range of 200 to 350°C, the thickness of the oxide film formed is about 1/2 that of Cu plating that does not contain Ag. can be suppressed. Therefore, the influence of unevenness in the thickness of the oxide film can be kept small.
／ｌお、Ａｇを含有するＣｕめっきは上記不連続のめな
らずＡｇめっき部分の下地ＩＡ埋として形成され′Ｃも
良い。/l Also, the Cu plating containing Ag is formed as a base layer IA of the discontinuous Ag plating portion.
また、めっきの厚みは、均一な皮膜形成が行われれば良
く、実用的には０１μｍ以上か好ましい。Further, the thickness of the plating is sufficient as long as it forms a uniform film, and from a practical standpoint, it is preferably 0.1 μm or more.
［実施例］
（実施例１）
リードフレームとしては、Ｃｕ−２％Ｓｎ−〇 １％Ｆ
ｅ−０，０３％Ｐ系合金（板厚０．２５ｍｍ）を、一般
的なり一１〜フレーム形状に加工したものを用いた。[Example] (Example 1) As a lead frame, Cu-2%Sn-〇 1%F
An e-0.03% P alloy (plate thickness: 0.25 mm) processed into a general frame shape was used.
ます、通常用いられるめっき前処理（アルカリ脱脂−電
解脱脂−酸洗）を行ったあと、アウターリード部および
インナーリード部の一部に半田スポットめっきを行った
。次いて半田めっき以外の部分にＡｇを含むＣｕスボッ
１−めっきを行い、続いて半導体素子部および電気配線
を行うインナーリード部にＡｇスポットめっきを行うこ
とにより、前記半田めっぎとＡｇめっきの間にＡｇを含
有するＣｕめっきか露出したり一部・フレームを作成し
た。First, after performing a commonly used plating pretreatment (alkaline degreasing, electrolytic degreasing, and pickling), solder spot plating was performed on a portion of the outer lead portion and the inner lead portion. Next, Cu spot plating containing Ag is applied to areas other than the solder plating, and then Ag spot plating is applied to the semiconductor element part and the inner lead part where electrical wiring is performed, thereby separating the solder plating and Ag plating. A part of the frame was created in which the Cu plating containing Ag was exposed.
比較としてＡｇを含有するＣｕめつきを省略したものお
よびＡｇを含まない通常のＣｕめっきを行っためっき処
理リードフレームを各々作成した。For comparison, lead frames were prepared in which Cu plating containing Ag was omitted and lead frames subjected to normal Cu plating without Ag.
これらのめっき処理の条件を以下に示す。The conditions for these plating treatments are shown below.
くめつき条件〉
１） 半田スポットめっき
スポットめっき方法：ノズル噴射およびマスキングバッ
トを用いた部分
めっき
半 １）め っ き 液・市販半田めっき液（上材工業
（株）製リード５Ｂ
−ＨＴ イ谷 ）
半 １） 組 成 ５ｎ９０％−ＰｂｌＯ
％温 度 ２０℃
電 流 密 度： ５０ Ａ ／ ｄ ｍ’め
っ き 厚 み ・ ７ μｍ２）、Ａｇを
含有するＣｕのスポットめ−）＠スポットめりき方ン去
・ノズル噴身Ｊおよびマスキングバットを用いた部分
めつぎ
め っ き 液 ピロりん酸第２銅、１００ｇ／
ｆｌ
・ピロりん酸銀
；５０ｐｐｍ〜
１０．０００ｐｐｍ
：ピロりん酸カリウム
、３５０ｇ／Ｊ２
７晶 度 ５０ ℃
電 流 密 度 ４ Ａ ／ ｄ ｍ’め
っ き 厚 み 。０ ５ μｍ３）、Ａｇスポ
ットめっき
スポットめっき方法 ノズル噴射およびマスキングパッ
ドを用いた部分
めっき
め っ き ７夜 ・ 市販Ａｇ
め っ きン夜（日本エンゲルハルト社製
Ｓ−９３０浴）
温 度＋５０℃
電 流 密 度 ５０ Ａ ／ ｄ ｍ’め
っ き 厚 み ５μｍ４）、Ｃｕスポット
めっき（比較法）
スボッ）〜めっき方法・ノズル噴射およびマスキングバ
ットを用いた部分
めっき
め ツキ／夜 Ｗ１且 成 ：ＣｕＣＮ；３０ｇ
／ ｆｌＮａＣＮ；３０ｇ／ｕ
Ｎａ２ＣＯ：＋
、１５ｇ／ｆｌ
ン晶 度 ： ４０
℃電 流 密 度・ ２ Ａ ／ ｄ ｍ’め
っ ぎ 厚 み ； ０ ５μｍこれらのめつ
き処理フレームについて、半導体組立て工程の熱影響を
想定し、空気中で、２００℃、２５０℃、３００℃、３
５０℃の温度で、各々３０分加熱を行い、Ｃｕめつき部
分に相当する部分の酸化皮膜のセロテープ密着試験を行
った。第１表にセロテープ密着試験結果を示す。Plating conditions> 1) Solder spot plating Spot plating method: Partial plating using nozzle spray and masking bat 1) Plating solution/Commercially available solder plating solution (Lead 5B-HT Itani manufactured by Kamizai Kogyo Co., Ltd.) Half 1) Composition 5n90%-PblO
% Temperature 20℃ Current density: 50 A/dm Plating thickness ・7 μm2), Ag-containing Cu spot-) @ spot milling method, nozzle jet J and masking Partial potting solution using a vat Cupric pyrophosphate, 100g/
fl Silver pyrophosphate; 50ppm to 10.000ppm: Potassium pyrophosphate, 350g/J2 7 Crystallinity 50°C
Current density 4 A/d m'
Thickness. 0 5 μm3), Ag spot plating Spot plating method Selective plating using nozzle spray and masking pad 7 nights ・ Commercially available Ag
Mekkin night (S-930 bath manufactured by Nippon Engelhard) Temperature + 50℃ Current density 50 A / d m'
Thickness: 5 μm4), Cu spot plating (comparative method) - Plating method: Partial plating using nozzle injection and masking bat.
/flNaCN; 30g/u Na2CO:+, 15g/fl Crystallinity: 40
℃Current Density・2 A/dm'
Thickness: 0.5μm These plating frames were heated at 200℃, 250℃, 300℃, and 3℃ in air, assuming the thermal effects of the semiconductor assembly process.
Each sample was heated at a temperature of 50° C. for 30 minutes, and a Cellotape adhesion test was conducted on the oxide film of the portion corresponding to the Cu plating portion. Table 1 shows the cellotape adhesion test results.
第１表において、Ｎｏ、１〜Ｎｏ、６は本発明の実施例
を示し、Ｎ０１７およびＮｏ、８は従来例を示す。In Table 1, No. 1 to No. 6 show examples of the present invention, and No. 17 and No. 8 show conventional examples.
Ｎｏ、７およびＮｏ、８は、共に酸化条件２００℃にお
いて酸化皮膜か￥Ｉ」離し、素地との密着性が悪いとの
結果を示した。In both No. 7 and No. 8, the oxide film separated from the oxide film at 200° C. under the oxidation condition of 200° C., indicating that the adhesion to the substrate was poor.
一方、Ｎｏ、１〜ＮＯ４６ては、Ａｇ含有量の少ないＮ
ｏ、１については３００℃て９１Ｊ離を生し始めるか、
Ｎ００２〜Ｎｏ、６については３５０℃でも剥離は生し
ないとの結果を示した。し”ｔすれも従来例と比較して
良好な結果であった。On the other hand, No. 1 to No. 46 are N with low Ag content.
For o, 1, 91J separation starts to occur at 300℃,
For No. 002 to No. 6, the results showed that no peeling occurred even at 350°C. The results were also better in comparison with the conventional example.
従って本発明の実施態様としては、性能、経済性を考慮
すると、Ａｇ含有量を０１〜１％と１−ることか好まし
い。Therefore, in the embodiment of the present invention, in consideration of performance and economical efficiency, it is preferable that the Ag content is 01 to 1%.
（実施例２）
第１実施例に示した方法にて作成したリードフレームを
用い、半導体素子接合、電気配線、Ｊ５ Ｊ：ひ樹脂封
止等を行って本発明に係る半導体装置を完成した。(Example 2) A semiconductor device according to the present invention was completed by using a lead frame produced by the method shown in the first example, performing semiconductor element bonding, electrical wiring, J5 J: resin sealing, etc.
本発明に係る半導体装置に用いたリードフレームの平面
図を第１図に示す。また、第１図の断面図を第２図に示
す。さらに、本発明に係る半導体装置の断面図を第３図
に示す。FIG. 1 shows a plan view of a lead frame used in a semiconductor device according to the present invention. Further, a sectional view of FIG. 1 is shown in FIG. 2. Furthermore, a cross-sectional view of a semiconductor device according to the present invention is shown in FIG.
図において、銅合金またはＦｅ−Ｎｉ合金からなるリー
ドフレーム１のアウターリード部およびインナーリード
部の一部に通常５〜１５μの厚みを有するＳｎあるいは
Ｓｎ合金めつぎ層２か形成され、半導体素子接合部およ
びインナーリード部の電気接続配線される部分に３〜７
μのＡｇめっき層３か形成されている。更に、Ｓｎある
いはＳｎ合金めつぎ層２とＡｇめっき層３の間には、不
連続部が設けられており、その不連続部にはＡｇを含有
するＣｕめつき層４か設けられている。封止オΔ」脂７
は、前記各めっき層２，３．４の表面の一部あるいは全
面に接着している。In the figure, a Sn or Sn alloy overlay layer 2 having a thickness of usually 5 to 15 μm is formed on a part of the outer lead part and inner lead part of a lead frame 1 made of a copper alloy or Fe-Ni alloy, and a semiconductor element is bonded to the lead frame 1. 3 to 7 on the part where the electrical connection and wiring of the inner lead part and the inner lead part are made.
An Ag plating layer 3 of μ is formed. Further, a discontinuous portion is provided between the Sn or Sn alloy plating layer 2 and the Ag plating layer 3, and a Cu plating layer 4 containing Ag is provided in the discontinuous portion. Sealing oil 7
is adhered to a part or the entire surface of each of the plating layers 2, 3.4.
以上の様に構成されたことにより、不連続部が半導体組
立工程時の加熱において素地との密着性の悪い酸化皮膜
を形成することかなく、従って、使用環境において水分
か侵入し、半導体装置か作動不良を生じるといった問題
を生しることのない半導体装置を得ることかできた。With the structure described above, the discontinuous portion does not form an oxide film with poor adhesion to the base material during heating during the semiconductor assembly process, and therefore moisture can enter in the usage environment and prevent the semiconductor device from forming. It was possible to obtain a semiconductor device that does not cause problems such as malfunction.
［発明の効果コ
以上説明したように、本発明によれは、■不連続部と酸
化皮膜との密着性か良好な半導体装置用リードフレーム
を安価に提供することかできる。[Effects of the Invention] As explained above, according to the present invention, (1) a lead frame for a semiconductor device with good adhesion between the discontinuous portion and the oxide film can be provided at a low cost;
■従って、使用環境において、半導体装置用り−トフレ
ームと封止樹脂との間から水分か侵入し、半導体装置が
作動不良を生しるとい）た問題を生しることのない、即
ち信頼性の高い半導体装置を、安価に提供することかて
きる。■Therefore, in the usage environment, there is no problem such as moisture entering between the semiconductor device board frame and the sealing resin, causing malfunction of the semiconductor device. This makes it possible to provide highly functional semiconductor devices at low cost.
第１表 セロテープ密着試験結果
評価基４（○ 酸化皮膜のｑＩＪ離なし△６ 〃 が
一部分ヱリ離 （剥れ面積１０％未満）× 〃 が
広範囲に剥ｌ！１ｌＩ（〃１０％以上）Table 1 Cellotape adhesion test results evaluation group 4 (○ No qIJ separation of oxide film△6 〃 Partially peeled off (Peeling area less than 10%) × 〃 Extensive peeling! 1lI (〃10% or more)
第１図は本発明に係る半導体装置用リードフレームの平
面図、第２図は第１図の断面図、第３図は本発明に係る
半導体装置の断面図。
１・・・リードフレーム本体、２・・・ＳｎあるいはＳ
ｎ合金によるめっき層、３・・・Ａｇめっき層、４・・
・Ａｇを含有するＣｕによるめっき層、５・・・半導体
素子、６・・・電気接続配線、７・・・封止樹脂。
第１図
第２図
第３図FIG. 1 is a plan view of a lead frame for a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view of FIG. 1, and FIG. 3 is a cross-sectional view of the semiconductor device according to the present invention. 1...Lead frame body, 2...Sn or S
plating layer made of n alloy, 3...Ag plating layer, 4...
- Plating layer made of Cu containing Ag, 5... semiconductor element, 6... electrical connection wiring, 7... sealing resin. Figure 1 Figure 2 Figure 3
Claims (2)
にＳｎあるいはＳｎ合金によるめっき層が設けられ、半
導体素子接合部および接続配線が接続されるリード部に
Ａｇめっき層が設けられ、前記ＳｎあるいＳｎ合金めっ
き層と前記Ａｇめっき層との不連続部が設けられた半導
体装置用リードフレームであって、当該不連続部がＡｇ
を含有するＣｕによりめっきされていることを特徴とす
る半導体装置用リードフレーム。(1) A plating layer made of Sn or Sn alloy is provided on a part of the outer lead part and the inner lead part, an Ag plating layer is provided on the semiconductor element joint part and the lead part to which the connection wiring is connected, and A lead frame for a semiconductor device provided with a discontinuous portion between a Sn alloy plating layer and the Ag plating layer, the discontinuous portion being Ag plating layer.
A lead frame for a semiconductor device, characterized in that it is plated with Cu containing.
にＳｎあるいはＳｎ合金によるめっき層が設けられ、半
導体素子接合部および接続配線が接続されるリード部に
Ａｇめっき層が設けられ、前記ＳｎあるいＳｎ合金めっ
き層と前記Ａｇめっき層との不連続部か設けられ、当該
不連続部がＡｇを含有するＣｕによりめっきされている
半導体装置用リードフレームの、前記ＳｎあるいはＳｎ
合金めっき層、前記Ａｇめっき層および前記Ａｇを含有
するＣｕめっき層の一部が、半導体封止材料で覆われた
ことを特徴とする半導体装置。(2) A plating layer made of Sn or Sn alloy is provided on a part of the outer lead part and the inner lead part, an Ag plating layer is provided on the semiconductor element joint part and the lead part to which the connection wiring is connected, and The Sn or Sn of a lead frame for a semiconductor device is provided with a discontinuous portion between the Sn alloy plating layer and the Ag plating layer, and the discontinuous portion is plated with Cu containing Ag.
A semiconductor device, wherein a part of the alloy plating layer, the Ag plating layer, and the Ag-containing Cu plating layer are covered with a semiconductor sealing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13686388A JPH01305551A (en) | 1988-06-03 | 1988-06-03 | Lead frame for semiconductor device and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13686388A JPH01305551A (en) | 1988-06-03 | 1988-06-03 | Lead frame for semiconductor device and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01305551A true JPH01305551A (en) | 1989-12-08 |
Family
ID=15185281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13686388A Pending JPH01305551A (en) | 1988-06-03 | 1988-06-03 | Lead frame for semiconductor device and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01305551A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0730296A2 (en) * | 1995-03-02 | 1996-09-04 | Dai Nippon Printing Co., Ltd. | Leadframe for plastic-encapsulated semiconductor device, semiconductor device using the same, and manufacturing method for the leadframe |
| US5561320A (en) * | 1992-06-04 | 1996-10-01 | Texas Instruments Incorporated | Silver spot/palladium plate lead frame finish |
| WO2004064154A1 (en) * | 2003-01-16 | 2004-07-29 | Matsushita Electric Industrial Co., Ltd. | Lead frame for a semiconductor device |
| US7547581B2 (en) * | 2005-09-15 | 2009-06-16 | Renesas Technology Corp. | Manufacturing method of a semiconductor device to suppress generation of whiskers |
| JP2010212691A (en) * | 2009-03-10 | 2010-09-24 | Lg Innotek Co Ltd | Light emitting element package |
-
1988
- 1988-06-03 JP JP13686388A patent/JPH01305551A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5561320A (en) * | 1992-06-04 | 1996-10-01 | Texas Instruments Incorporated | Silver spot/palladium plate lead frame finish |
| EP0730296A2 (en) * | 1995-03-02 | 1996-09-04 | Dai Nippon Printing Co., Ltd. | Leadframe for plastic-encapsulated semiconductor device, semiconductor device using the same, and manufacturing method for the leadframe |
| EP0730296A3 (en) * | 1995-03-02 | 1998-07-01 | Dai Nippon Printing Co., Ltd. | Leadframe for plastic-encapsulated semiconductor device, semiconductor device using the same, and manufacturing method for the leadframe |
| SG106554A1 (en) * | 1995-03-02 | 2004-10-29 | Dainippon Printing Co Ltd | Leadframe for plastic-encapsulated semiconductor device, semiconductor device using the same, and manufacturing method for the leadframe |
| WO2004064154A1 (en) * | 2003-01-16 | 2004-07-29 | Matsushita Electric Industrial Co., Ltd. | Lead frame for a semiconductor device |
| US7692277B2 (en) | 2003-01-16 | 2010-04-06 | Panasonic Corporation | Multilayered lead frame for a semiconductor light-emitting device |
| US7994616B2 (en) | 2003-01-16 | 2011-08-09 | Panasonic Corporation | Multilayered lead frame for a semiconductor light-emitting device |
| US8541871B2 (en) | 2003-01-16 | 2013-09-24 | Panasonic Corporation | Multilayered lead frame for a semiconductor light-emitting device |
| US7547581B2 (en) * | 2005-09-15 | 2009-06-16 | Renesas Technology Corp. | Manufacturing method of a semiconductor device to suppress generation of whiskers |
| JP2010212691A (en) * | 2009-03-10 | 2010-09-24 | Lg Innotek Co Ltd | Light emitting element package |
| US8987775B2 (en) | 2009-03-10 | 2015-03-24 | Lg Innotek Co., Ltd. | Light emitting device package |
| US9318677B2 (en) | 2009-03-10 | 2016-04-19 | Lg Innotek Co., Ltd. | Light emitting device package |
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