JPH01304515A - Resetting circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a resetting circuit by deciding a normal mode or non-normal mode according to the state of a reset terminal in case these two modes are available and resetting a circuit in the non-normal mode. CONSTITUTION:A resetting circuit consists of a mode switching latch 1, a transistor TR2 and a reset releasing circuit 3 applying a pull-down resistance. In a normal mode, the Q output of the latch 1 is set at an Lo (low) level and then set at an Hi (high) level with the gate input of the TR2. Thus the TR2 is turned off and never reset. When a non-normal mode is required, a reset terminal is set at an Lo level from outside together with the Q output of the latch 1 is set at a Hi level respectively. Thus the TR2 is turned on. As a result, the reset terminal is kept at a Lo level and therefore never reset. Then the normal mode is reset when the reset terminal is opened.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a reset circuit, and in particular, when there are multiple non-normal modes in addition to the normal mode, it is possible to automatically reset the circuit if the non-normal mode is accidentally entered. The present invention relates to such a reset circuit.

[Conventional technology]

There is no conventional reset circuit technology that automatically resets the circuit when it malfunctions.

Therefore, measures are taken to prevent malfunctions, such as adding a mode setting terminal.

[Problem to be solved by the invention]

As mentioned above, conventional reset circuits do not have any countermeasures against malfunctions, so if the circuit malfunctions, it is necessary to activate the reset pin externally or provide a mode setting pin to prevent malfunctions. The disadvantage is that it does not.

[Differences between the invention and the prior art]

As described above, conventional reset terminals do not have a function to automatically reset the terminal in the event of a malfunction. In order to perform the same operation, another mode setting terminal was provided, and if an incorrect operation occurred due to the state of this terminal, a reset was applied to prevent the malfunction. However, in the present invention, the mode setting terminal is The difference is that if a malfunction occurs without the provision of such a device, a reset is automatically applied to prevent the malfunction.

[Means to solve the problem]

The reset circuit of the present invention includes a mode switching latch that switches between normal mode and non-normal mode, a transistor that activates the reset terminal when the mode switching latch is in the non-normal mode, and a transistor that attempts to release the reset terminal from the active state. It has a reset release circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The mode switching latch 1 is a D-F/F, the transistor 2 is a Pch transistor, and the output signal of the mode switching latch is used as a gate input.

The reset release circuit 3 is a pull-down resistor.

In this embodiment, the RESET terminal is active Hi. Further, as a condition for realizing the present invention, it is necessary that the pull-down resistance of the reset release circuit 3 is sufficiently large with respect to the ○N resistance of the transistor 2.

First, the operation in normal mode will be explained.

In normal mode, the Q output of mode switching latch 1 is L.
O level, and the gate input of transistor 2 is Hi.
level, so transistor 2 is turned off. In this case, the reset terminal is always set to Lo level by the reset release circuit 3, and unless the RESET terminal is set to Hi level from the outside, RESET will not be applied.

Next, the operation in non-normal mode will be explained. To operate in non-normal mode, first enter RESET from the outside.
Set the terminal to low level. In the non-normal mode, the Q output of the mode switching latch 1 is at Hi level, and the gate input of the transistor 2 is at Lo level and turned ON. Here, if the RESET terminal is 0PEN, the RESET
Although the T signal is overloaded, the RESET is not applied because it is set to Lo level from the outside in advance. That is, when operating in a non-normal mode, the RESET terminal is externally set to Lo level, and when operating in a normal mode, the RESET terminal is set to 0PEN. By doing so, if the mode switching latch is mistakenly set to the non-normal mode side during normal operation (RESET terminal is 0PEN), RESET is applied and malfunction can be prevented.

〔Effect of the invention〕

As explained above, in the case where there are several non-normal modes in addition to normal mode operation, the present invention can determine whether it is normal mode or non-normal mode by determining the state of the reset terminal without providing a mode setting terminal. This has the effect of preventing malfunctions by resetting the circuit if it accidentally enters a non-normal mode.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention. 1...Mode switching latch, 2...Pc
h) Transistor, 3... Reset release circuit. Agent: Patent Attorney Shinshu Uchihara

Claims (1)

[Claims] It is characterized by having a mode switching latch that switches between normal mode and non-normal mode, and a transistor that activates the reset terminal when the mode switching latch is in the non-normal mode, and a reset release circuit that releases the reset terminal from the active state. Reset circuit.