JPH01303731A - Wiring substrate with microlead and manufacture thereof - Google Patents

Abstract

PURPOSE:To facilitate the mild structural connection of an LSI chip by a method wherein the LSI chip is connected resiliently in the perpendicular direction. CONSTITUTION:A microlead 11 connecting a through hole 8 of a wiring substrate 7 and an LSI chip 9 is composed of a junction part 12 arranged in a distant position as well as connecting parts taking curved shape to absorb the shifting of the junction part 12. Consequently, the microlead 11 can absorb the shifting in two orthogonal directions. Through these procedures, even if the wiring substrate 7 and the LSI chip 9 with both ends 12 connected to each other are notably different in the thermal expantion coefficients, the thermal stress imposed on the junction part 12 of a solder 14 can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a wiring board for connecting electronic components such as LSI chips and a method for manufacturing the same, and particularly relates to a wiring board for connecting electronic components such as LSI chips, and particularly to a wiring board for connecting electronic components such as LSI chips. The present invention relates to a wiring board with micro leads suitable for flexible connection on the same wiring board, and a method for manufacturing the same.

[Conventional technology]

Recently, in the field of high-performance electronic devices such as electronic computers, there has been a demand for the development of flexible structure chip connection technology for mounting LSI chips.

The reason why the LSI nap connection method with a flexible structure is required as described above is related to the calculation speed, which is one of the most important performance characteristics of an electronic computer. In other words, when looking at the computing speed on the computer node (device) side, L
It is determined by the performance of the SI and the performance of the wiring board on which it is mounted.

Looking at recent trends in wiring boards, multilayer wiring boards made of ceramics (alumina, mullite, etc.) using W (tungsten) and Mo (molybdenum) as wiring materials have been developed and put into practical use.

This is effective in packaging LSIs at high density and shortening the increasing total wiring length. However, in terms of electrical signal transmission performance, there were the following unsatisfactory points.

(l) Ceramic substrates generally have a high electrical permittivity (alumina ε: 9 to 10), so parasitic charges are generated at the interface where the ceramic substrate and wiring come into contact, causing a delay in the transmission speed of electrical pulse signals. .

(2) Wiring conductor materials such as W and No have higher electrical resistance than other metal conductors, such as Cu (copper).

Therefore, the waveform of the electric pulse signal is deteriorated.

As a result, in order to shorten the time between transmitted pulses,
In turn, this becomes a cause of impeding an increase in the transmission capacity and speed of pulse signals.

Therefore, in order to eliminate the above-mentioned drawbacks, recently, wiring boards have been developed that use Cu as the wiring material and organic materials with low electric permittivity, such as polyimide resin (εta3), as the substrate material. There is a tendency to use and try.

However, in the above-mentioned high-performance wiring board, the linear thermal expansion coefficient is thicker than that of ceramics such as alumina (LSI
The difference in thermal expansion coefficient (hereinafter referred to as α difference) with Si, which is the main component of the f-nip, is as large as 100 to 130 x 10-7/'O (
A.

For this reason, unlike the conventional LSI connection method, L
Direct soldering of the SI chip causes the following inconveniences. In other words, L is applied to a wiring board using organic matter and Cu.
When the SI chip is fixed, the α difference is large, so thermal stress is generated in the solder connection, and the solder connection cannot respond to the strain caused by the thermal stress and breaks, resulting in the connection being disconnected.

Therefore, as mentioned above, L
When connecting SI chips, a method is required that can absorb or alleviate the thermal stress strain caused by the α difference between the two, that is, a method for connecting LSI chips with a flexible structure.

Furthermore, even if a conventional ceramic wiring board is used,
Thermal expansion coefficient of ceramic wiring board (60~65X 1
0-'/'O) is the coefficient of thermal expansion of the LSI chip (sox
1o-'/°c). In particular, with the recent increase in the size of LSI nappies (iow' → 16■0), thermal stress distortion due to the α difference tends to increase, and it is already difficult to withstand the thermal stress distortion with solder-only connections. It is in. For this reason, L
When connecting SIs, there is also a need for an LSI chip connection method that has a structure that can absorb or alleviate strain caused by thermal stress.

In response to this demand, for example, Japanese Patent Application Laid-Open No. 61-11044
The one described in Publication No. 1 has been proposed.

[Problem to be solved by the invention]

The conventional flexible structure chip connection method has the following problems.

It does not have deformation or elastic force in the vertical CZ direction (at the connection portion between the 11LSI chip and the wiring board).

This means that after connecting the LSI chip to the wiring board,
An inconvenience occurs at the contact portion between the back surface (non-electrical connection surface) of the LSI chip and the cooling body. That is, the LSI chips (plurality) connected to the wiring board are usually connected individually with some unevenness or inclination (not completely horizontal).

Therefore, a gap (or poor contact) may occur at the contact interface between the chip and the cooling body. To prevent this, the back of the chip is usually pressed from the cooling body side with a rod (heat dissipation stud) equipped with a spring mechanism (Reference example: Ninikkei Electronics, 19B5, 6, 17, p.
256).

However, this method reduces the cooling effect and complicates the cooling structure.

On the other hand, by connecting the LSI chip so that it has elastic force in the vertical (Z) direction, good contact properties can be obtained and the conventional cooling body described above can be simplified.

However, the conventional solder-only connection method and the above-mentioned Ehrfelt connection method do not have sufficient elasticity.

(2) Ehrfeld's connection method requires two connections for each terminal on the chip.

As described in Japanese Unexamined Patent Publication No. 110441/1983 and shown in FIG. leaf spring 100
This protruding part is inserted into the insertion hole of the board 3 and connected to the board 3 by the connecting member 6, and the other
The two pins 100α are connected to the connecting portion 5 of the nap 2 with solder 4.

However, in Ehrfeld's subjunctive method as mentioned above, 2
Since multiple connections are required, chip connection operations and electrical connection characteristics (eg, electrical resistance) are unfavorable.

Therefore, it is desirable to complete the chip connection at one location, as in the conventional connection using only solder.

In addition, the Ehrfeld connection method requires high energy (synchrotron radiation is used in the above-mentioned Japanese Patent Application Laid-Open No. 61-110441) to create a leaf spring, making the entire process complicated and difficult to perform. was there.

An object of the present invention is to provide a wiring board with micro leads and a method for manufacturing the same, which solves the problems of (11) and (21) above, and allows easy flexible structure connection of LSI chips in a simplified process. be.

[Means to solve the problem]

In order to achieve the above object, the wiring board with micro leads of the present invention has a plurality of joints each connected to a through-hole conductor of the wiring board and an electronic component and arranged at positions spaced apart from each other, and The connecting part is formed of copper and has at least a gold layer on the joint part on the side connected to the electronic component. , and the surface other than the gold layer is covered with a metal oxide film.

Further, the connecting portion of the micro lead and the electronic component side bonding portion are arranged so as to have a gap with respect to the wiring board.

Further, the electronic component side joint portion of the micro lead is composed of another metal interposed between the upper surface of the micro lead and the gold layer.

Further, the other metal is made of nickel.

Further, the other metal is composed of platinum.

In addition, the method for manufacturing a wiring board with micro leads of the present invention includes a step of forming a lift-off layer on the wiring board, and drilling holes in the portion of the lift-off layer to be bonded to the through-hole conductor previously formed on the wiring board. , a step of forming a copper film of the micro-lead material in the hole and on the lift-off layer, and forming at least a gold layer on the copper film of the micro-lead material at a position away from the hole (a position facing the electronic component to be connected). a step of forming a micro lead consisting of a hole in the copper film, a gold layer, and a curved connection between the hole and the gold layer; and a step of removing the lift-off layer and removing the layer other than the gold layer. This method includes a step of oxidizing the surface of the microlead.

Further, the step of forming the gold layer includes the step of forming a nickel layer.

Further, the step of forming the gold layer includes a step of forming a platinum layer.

[Effect]

Since the wiring board with micro leads of the present invention is configured as described above, the problems of the prior art fi+ (2+
can be solved.

In other words, the microleads are arranged in at least two perpendicular directions (
For example, the structure is designed to absorb movement in two horizontal directions (for example, two horizontal directions), so even if the thermal expansion coefficients of the wiring board and the electronic component that are connected at both ends are greatly different, thermal stress will occur in the solder joint. can be reduced, thereby solving problem (1) of the prior art. In addition, the micro lead connects the solder joint at one end to the through-hole conductor of the wiring board, and the solder joint at the other end connects the chip to one connection terminal of the electronic component or chip. , the chip connection operation and the electrical connection characteristics (eg, electrical resistance) can be improved, thereby solving the problem (2) of the prior art.

In addition, since the micro-lead has a gap between it and the top surface of the wiring board, it can also absorb the direction in which the micro-lead connects to the top surface of the wiring board (vertical direction). The chip can be completely attached to the cooling body installed on the back side (upper side), and as a result, the LSI chip cooling effect can be sufficiently ensured, and the heat dissipation stud of the conventional technology can be omitted. Since the method for manufacturing a wiring board with micro leads of the invention includes the steps described above, micro leads can be easily created through a simplified process.

That is, regardless of the micro-lead, it is usually necessary to provide a metal called a solder dam near the part to be soldered to prevent solder from flowing out.

This is because, if this solder dam were not provided, molten solder would flow out and stick to unnecessary areas during soldering, thereby causing misalignment.

In contrast, the present invention can achieve the above-mentioned prevention of solder leakage by oxidation treatment applied to the surface of the micro-lead main body without newly providing a metal that performs the solder dam function.

This point will be explained in further detail. In the present invention, a gold layer is formed on the copper film at the solder joint portion of one end of the micro lead connected to the LSI chip. The purpose of this gold layer is to improve wettability with solder and to prevent surface oxidation when solder is provided on the upper surface for connection to an LSI chip. If this gold layer is not formed, when the surface of the copper film forming the micro-lead is oxidized in the air at high temperatures, the solder and the copper film will not get wet, making solder bonding impossible.

On the other hand, after providing the gold layer as described above, all surfaces of the microleads other than the gold layer surface are oxidized to form a thin film, making it impossible for solder to adhere. Therefore, it is possible to omit the provision of metal for solder dams, and to prevent incorrect solder connections and short connections due to solder scattering in areas where a large number of fine micro leads are closely arranged. As a result, particularly effective results can be achieved when soldering multiple minute parts at the same time. In other words, in the present invention, solder does not adhere to any part other than the gold layer of the micro lead due to the oxidation treatment, which can improve the yield in the solder connection work of the micro lead, and also prevents solder from adhering to any part other than the gold layer of the micro lead. Oxidizing the surface can be carried out very easily.

That is, the oxidation treatment of the microleads other than the gold layer can be performed simply by heating the wiring board in a mixed flow of air and oxygen, and can be performed very easily. In addition, in order to form a gap between the micro-leads and the top surface of the wiring board, materials that are more easily dissolved by chemicals than the copper that forms the micro-leads (for example, Al1.
f6yO, etc.) or a lift-off is formed, making it easy to remove the lift-off.

Additionally, since a nickel or platinum layer is interposed between the copper film that forms the micro leads and the gold layer that forms the solder joints that connect to electronic components, the gold layer does not penetrate into the copper film depending on the temperature. can be prevented.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A wiring board with micro leads and a manufacturing method thereof, which are an embodiment of the present invention, will be explained below with reference to FIGS. 1 to 4.

First, the structure of the wiring board with micro leads according to the present invention will be explained with reference to FIG.

As shown in FIG. 1 (α), between a wiring board 7 on which through-hole conductors 8 are formed in advance and an LSI chip 9 having a cooling body of 1° on the upper surface, these through-hole conductors 8 and LS
Micro leads 11 are inserted for bonding with the I-chip 9. This micro lead 11 is a flat plate made of copper and is formed into a circular shape with both ends spaced apart from each other as shown in FIG.
A through-hole conductor joint 12α is formed to be joined to the other end, and a gold layer 13 is formed directly on the other end, or a nickel 1
A gold layer 13α is formed through the gold layer 6b, and a solder joint portion 12h is configured to join the gold layer 15α to the LSI nap 9 through the solder 14. Further, between the through-hole conductor joint portion 12α and the solder joint portion 12A, the upper surface of the wiring board 7 is arranged with a gap therebetween, together with the solder joint portion 12h. It is formed in the shape of Further, the surface of the microlead 110 other than the gold layer 15α is covered with a metal oxide film (not shown).

Since the wiring board with micro leads according to the present invention is configured as described above, both grade portions 12α.

12.6 in two horizontal directions (J and Y directions), and even when there is a large difference in thermal expansion coefficient between the wiring board 7 and the LSI chip 9, the solder joint In addition, since the solder joint connects the nap to one connection terminal of the electronic component or chip at one place, it reduces the chip connection work and the electrical connection characteristics (e.g. electrical resistance). can be made preferable.

Furthermore, since the micro-leads 11 have sufficient elasticity in the Z direction, the LSI chip 9 and the cooling body 10 can be brought into close contact with each other, and as a result, a sufficient cooling effect for the LSI chip 9 can be ensured. At the same time, the structure of the cooling body 10 can be simplified.

Next, a method for manufacturing a wiring board with micro leads according to the present invention will be explained with reference to FIGS. 2 to 4.

1. Regarding the formation of micro leads on the wiring board, the second
As shown in the figure, polyimide resin 7h is multilayered as an insulating material on PACE 7α, which is made of alumina ceramics and has input/output bins 7 for electrical signals and power supply on the bottom surface, and copper is wired inside. A multilayer wiring board 7 on which a horizontal copper wiring 7c and a vertical through-hole conductor (made of copper) 8 are formed is prepared in advance, and a micro lead 11 is formed on its upper surface 7d. do.

As shown in FIG. 3(α), this micro lead 11 is formed by sputtering on the entire upper surface 7d of the wiring board 7 formed as described above, as shown in FIG. 3(b). An M film 15 is formed as a lift-off material with a thickness of about 5 μm.

Next, apply an alkali-resistant resist (not shown) to the M film 15.
After coating and drying the resist on the upper surface of the through-hole conductor 8 and removing the resist on the M film 15α portion on the through-hole conductor 8, the through-hole conductor 8 is coated with a sodium hydroxide (NaOH) solution whose pH has been adjusted to approximately 10.5. Upper M membrane 15
α is removed, washed with water, and dried to form a contact hole 16 as shown in FIG. 3(c). Note that the diameter of this contact hole 16 is approximately 110 μm.

Next, after removing the remaining resist on the wiring board 70M film 15, the copper film 17 is deposited to a thickness of approximately 20 μm by electroplating, as shown in FIG. It is formed thickly over the entire surface of the M film 15.

At this time, the through-hole conductor 8 in the contact hole 16
and the copper film 17 are bonded to each other at a bonding surface 8α.

After washing and drying the wiring board 7 on which the copper film 17 has been formed in this way, a positive resist 18 is applied on the copper film 17 while the copper film 17 is not oxidized, and the non-under bonding of the micro leads 11 is performed. A portion of the resist 18 corresponding to the position of the portion 12A is removed in a circular shape with a diameter of approximately 110 μm.

Next, as shown in FIG. 3(-), an N1 layer 13A with a thickness of about 1 μm is first formed on the exposed portion of the copper film 17 by the usual electroplating method after the resist is removed, and then a gold layer 13α is formed. is formed with a thickness of 1 μm.

Next, in order to form the micro leads 11 shown in FIG. 4, after removing the remaining resist film on the copper film 17 on the wiring board 7, a new negative resist is applied and dried.
After exposing a plurality of micro lead patterns having the shape shown in FIG. 4, the resist in other parts is removed.

Here, one solder joint 12α is made to coincide with the circle center of the through-hole conductor 8, and the other solder joint 12h is made to coincide with the circle center of the gold layer 15.

Next, the copper film 1 other than that protected by the negative resist
The exposed part of 7 was treated with ferric chloride aqueous solution (pact, , ct-
35,/Z) using an etching solution as shown in Fig. 3(f).
A micro lead 11 is formed by etching as shown in FIG.

Next, the M film 15 is dissolved and removed using an aqueous sodium hydroxide solution to form a void 19 between the micro lead 11 and the wiring board 7, as shown in FIG. 3 (!1).
Remove the etching residue that remains in some places with 2 liters of hydrochloric acid aqueous solution.
Clean, wash and dry.

Then, the wiring board 7 is heated for about 2 hours in a mixed air flow of air and oxygen.
DO'O is heated for 13 minutes to oxidize all of the surface 20 of the micro lead 11 other than the gold 1i13α as shown in FIG. 3(A). At this time, the gloss on the surface of the copper film faded, indicating that the surface of the copper film was oxidized, and thus a wiring board with micro leads was formed. Further, the specifications of the wiring board with micro leads formed in this manner are as follows.

1. Dimensions of micro lead Lead band width ・・・・・・・・・・・・・・・50μm
Lead band thickness: 20μm Pitch between leads: 400μm 11. Number of micro leads per chip connection: 529 pieces per board. ...529
X 4 = 2116 pieces (4 chips can be connected) Micro lead array shape 1 chip connection area...Square (1 span) on 1 board...・・・・・・・・・
4 square spans (2 x 2 spans) 2. Regarding the connection of the LSI chip, the lead ends of the wiring board with micro leads formed as described above (
Align the solder joint part 12b) and the solder pole 14 already provided at the connection terminal part of the LSI chip 9 using a half mirror, and connect it to 5 as shown in FIG. 3(1) using the usual face-down bonding method. do. The connection temperature at this time is 630° from the melting point of the solder 14 provided on the LSI chip 9.

The module formed in this way is shown in Figure 1 (α).
As shown in FIG. 2, a cooling body 10 and an LSI chip 9 are provided inside the casing. At this time, the Z (vertical) of micro lead 11
Since it also has elastic force in the direction, the back surface of the LSI chip 9 is completely pressed against the wall surface of the cooling body 7 and is in close contact with it.

5. Other Application Examples (1) A wiring board with micro leads was prepared on an alumina multilayer wiring board in the same manner as in the above embodiment. This example was carried out to solve the thermal stress problem that occurs when a large-sized LSI chip (16w'') is connected to a conventional alumina wiring board. Specifications of the fabricated wiring board with micro leads is as follows.

(1) Dimensions of micro lead Lead band width ・・・・・・・・・・・・・・・50μm
Lead band thickness: 20 μm Pitch between leads: 450 μm (11) Number of micro leads per chip connection: 1156 pieces per board
・・・－・・・・Song・・・・・・1156 X 4
= 4624 pieces (110 micro-lead array shape, 1 chip connection part... Square (1 span), 1 board...)・・・
- Square 4 spans (2 x 2 spans) A 16W''' LSI chip was connected to the above alumina array substrate with micro leads in the same manner as in the previous example.

4. Other Application Examples (2) A micro-lead-equipped wiring board was prepared using the same method as in the previous example on an alumina-based wiring board in which the electrical wiring was made of one layer and a through-hole conductor.

An LSI chip was connected to the above-mentioned wiring board with micro leads as a carrier (in the same manner as a film carrier), and the whole was covered with a metal cap for packaging, and placed in a module casing. In this example, one LSI chip and a plurality of LSI chips were packaged.

This example shows that the wiring board with micro leads of the present invention is LS.
This is an implementation of the fact that one or more I-chips can be used in a compact package.

Therefore, the method for manufacturing a wiring board with micro-leads of the present invention allows micro-leads to be easily produced in a simplified process.

Furthermore, according to the experimental results by the inventors of the present invention, the wiring board with micro leads according to the present invention can be used even when the difference in thermal expansion coefficient between the LSI chip and the wiring board is as large as 130×10-7/"C. , a module equipped with an LSI chip can sufficiently withstand a thermal cycle test of -50 to +150'O, and can prevent disconnection accidents at solder joints.

The table below shows a comparison between the conventional method using only soldering and the case where the wiring board with micro leads according to the present invention is used.

8 Blue thermal expansion coefficient (x 1o-'/'O) Arrow 50~+150'0, 10' cycle★+mα
Experimental results with a difference of 40 x 10-''/'O [Effects of the invention] Since the present invention configures a wiring board with micro leads as described above, the difference in thermal expansion coefficient between the wiring board and the electronic component is large. It can reduce the thermal stress generated in the solder joints even in cases where the chip is connected, improve chip connection work and electrical connection characteristics, ensure sufficient cooling effect for electronic components, and simplify the structure of the cooling body. and the conventional heat dissipation studs can be omitted.

Furthermore, in the method for manufacturing a micro-lead wiring board, micro-leads can be easily produced in a simplified process.

Furthermore, since nickel or platinum is inserted between the copper and gold in the solder joint, it is possible to prevent gold from penetrating into the steel due to temperature.

[Brief explanation of the drawing]

FIG. 1(α) is a sectional view showing the main parts of the wiring board with micro leads of the present invention, FIG. 1(h) is a perspective view of the micro leads, FIG. 2 is a sectional view of the wiring board, and FIG. Diagrams for explaining the manufacturing process of the micro-lead wiring board of the present invention, FIG. 4 is a top view of the micro-lead group, and FIG. 5 shows the conventional Ehrfurt connection method. A perspective view showing the lead; (b) is a plan view of the leaf spring type lead;
7. Wiring board 8, tapping, through-hole conductor 9... ...... LSI chip 10
...Rule...Cooling body 11...Micro lead 13α...Metal 13b...Nickel layer 14...Solder 15.・・・・・・
...M film 17. Song...Copper film 1st
0 (α) '7' LSI Nasoa 121e? 5. 74 Hanzo 7 wire board 8 through claw - 1 lead 30 b sword - small - JL41 not included 16] Mewat claw - 1B
Resist tail 4 Figure 11 Micro lead 12b Hang book 8 evil 1267J, -m-) *i'X'=H8BB(α
) Figure 5(b)

Claims (1)

[Claims] 1. A plurality of joints each connected to a through-hole conductor of a wiring board and an electronic component and arranged at positions apart from each other, and elastically absorbing movement of the plurality of joints. In order to make a connection, at least a gold layer is formed on the joint part on the side that is made of copper and connected to the electronic component, and other than this gold layer. A wiring board with micro leads, in which a wiring board is provided with micro leads whose surfaces are covered with a metal oxide film. 2. The wiring board with micro leads according to claim 1, wherein the connecting part of the micro leads and the joining part on the electronic component side are arranged so as to have a gap with the wiring board. 3. The wiring board with micro leads according to claim 1, wherein the electronic component side joint portion of the micro leads is comprised of another metal interposed between the upper surface of the micro leads and the gold layer. 4. The wiring board with micro leads according to claim 1 or 3, wherein the other metal is nickel. 5. Claim 1 or 3, wherein the other metal is platinum.
Wiring board with micro leads as described. 6. Step of forming a lift-off layer on the wiring board, making a hole in the part of this lift-off layer that will be bonded to the through-hole conductor previously formed on the wiring board, and forming a copper film of micro-lead material in this hole and on the lift-off layer. a step of forming at least a gold layer at a position away from the hole on the copper film of the micro-lead material (a position facing the electronic component to be connected); A wiring board with micro-leads comprising a step of forming a micro-lead consisting of a curved connection portion between a metal layer and a gold layer portion, and a step of removing a lift-off layer and oxidizing the surface of the micro-lead other than the gold layer. manufacturing method. 7. The method for manufacturing a wiring board with micro leads according to claim 6, wherein the step of forming the gold layer comprises a step of forming a nickel layer between the copper film and the gold layer. 8. The method for manufacturing a wiring board with micro leads according to claim 6, wherein the step of forming the gold layer comprises a step of forming a platinum layer between the copper film and the gold layer.