JPH0130335B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to digital data transmission, and more particularly to an automatic channel arrangement device that multiplexes and combines a plurality of digital data channels for transmission within a single transmission path. The present invention provides an apparatus for automatically changing channel alignment and is particularly useful in conjunction with digital data modems. Conventionally, there are digital data modems that interface with data processing equipment at the end of a transmission channel, such as a telephone line. There are also multi-port modems. This constitutes multiple channels for transmission by multiple similar channels of cooperating data processing devices. Multi-channel information is multiplexed for transmission on individual lines. This multiplexing is normally performed by interlacing channels bit by bit using TDM (time division multiplexing). Of course, there are other multiplexing methods that can also be used with the present invention. To begin transferring information between modems over a transmission line, an initial signal sequence is conventionally sent out.
This is also called a "handshake" motion. This type of signal indicates that the data source actually wishes to transmit data, or that it is seeking a transmission channel. An example of the former, currently in use, is RTS (Request to Send or Ready to Send). An example of the latter is DTR (data terminal preparation)
Or there is DSR (data set preparation). RTS exists only while a transmission is in progress, whereas DTR exists for the time the data source is engaged in interactive transmission with a device such as a CPU. Also, DCD (data conveyance detection) and RLSD (receiving line signal detection)
It is also known to use signals. Also, when there is data transmission from a transmission modem, DCD is used,
It is known to immediately set the DCD low upon reception of a coded inverse RTS signal (). One modem that incorporates the use of signals as described above and has been commercialized is the Mirgo 96MM. This type of signal is particularly effective in the present invention. Conventional multi-port modems contain the necessary circuitry to switch between various port arrangements in response to commands manually set by an operator.
Such channel allocation and port reordering is useful when data transport patterns sometimes differ.
Useful. It is also possible to set the modem switching schedule so that the operator can change the mode many times during the modem switching schedule. Of course, the actions of two operators manually operating the modem at each end of the transmission line must be accommodated. Additionally, to make more efficient use of costly telephone channels, data processors and modem systems work together to quickly and automatically rearrange ports without operator intervention. It is desirable to have a dynamic port reordering capability. It is therefore an object of the present invention to rearrange the modem port array without manual intervention. Another object of the present invention is to automatically perform relevant mode switching between two modems connected by a transmission line. Another object of the present invention is to dynamically perform port reordering. This allows the modem or multiplexer to adapt flexibly and unpredictably to changing transport patterns and to make best use of the frequency range at any given time. That is, an object of the present invention is to automatically and quickly convert one channel arrangement to another in response to an accidental requested channel arrangement signal in a data transmission system capable of multiple channel arrangements, that is, multiple framing configurations. The purpose is to propose a device that can be used for this purpose. In order to achieve the above objects of the present invention, a control signal is provided that automatically detects a request to change the multiplexing arrangement (port or channel arrangement) from a cooperating device and causes the multiplexing device to make the desired change. A circuit is provided to automatically output the . Furthermore, according to the invention, when a device comprising a port with a data input/output channel to a first data modem requests a change in port (channel) configuration, this request is detected and maintained, and this indication is It is sent over the transmission line and serves as a port reordering request to the second cooperating modem. After an appropriate delay to put the second modem into the proper port configuration, the first modem is switched to the new port configuration by a port reordering request from the previously added data processing device. Also, the line-end data modem or multiplexer that is the source of new port arrangement requests becomes the master device;
The multiple modem at the other end of the line becomes a slave device. Port configuration mode switching occurs on command, and when a data source does not request a channel, the channel is allocated to an active data source. According to another feature of the invention, a modem operator takes advantage of a master clock when controlling data processing devices in two modem settings to synchronize operation between two modems. I can do it. This provides direct software synchronization and eliminates the need to transmit synchronization information. Another important point of the present invention is to provide a sequence technique for switching from one port configuration to the next port configuration using the handshake signal currently used in communication systems using modems. This results in
The hardware is greatly simplified and the problems associated with adding and deleting channels are resolved. In the present invention, channels are assigned such that the number of channels to be multiplexed increases as the rank decreases, so it is possible to easily set a new channel arrangement by dropping channels as appropriate. In other words, when the channel array with the lowest rank is set, all channel settings are performed at the same time, so the time and operations required for this are concentrated at that point, while the channel arrays with other ranks are This is done by shedding only. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In FIG. 1, a pair of modems 11 and 13 are connected via a transmission channel 15. Each modem 11 and 13 interfaces with a data processing device, such as a central processing unit, data terminal, or other peripheral device. For example, modem 11 may interface with multiple ports of central processing unit (CPU) 12, and modem 13 may interface with data terminal equipment (DTE) 14.
interface with multiple ports of some kind. Conventionally, multi-port modems multiplex multiple channels output by associated processing devices for communication over transmission lines. For example, a multi-port modem multiplexes four ports 16 transmitting 2400 bits per second individually and 9600 bits per second collectively. A modem that works with it separates out a single channel of information. Generally, a two-way transmission system using four wires is used, with multiplexing and demultiplexing operations occurring at both ends of the transmission line. In practice, it may be desirable to reconfigure channel or port locations. For example, in a 4-port device, if two channels are not needed for data transmission, it is desirable to be able to disable these two channels and allocate the frequency band to the channel that is transmitting data. . This method provides more efficient data transmission. Also, as mentioned above, conventional multi-port modems include circuitry that switches between various port configurations in response to manually set commands.
A general method of encoding data for a multi-port transmission device is shown in FIG. Although FIG. 2 is somewhat simplified, those skilled in the art will readily understand how to implement this network. As shown in FIG.
A multiple clock selection circuit 101 selects the clock signal to be applied to the clock signal. Clock selection circuit 101 is operated by clock 105. The clock selection circuit 101 has a frequency divider and a logic circuit, and has a periodic four-phase clock order φ ₁ ,
A clock signal which is interlaced with each other at φ ₂ , φ ₃ and φ ₄ and divided into four is output. Conventionally, the clock phases are selectively gated and applied to the multiplex/separate circuit 103 in response to manually set codes. The phase outputs of each multiplex/separate circuit 103 are combined onto a single line by an OR gate 104 at 9600 bits per second.
OR gate 104 provides 9600 bits of data per second to modem transmission circuit 106 where the data is modulated in a known manner. For example, if only two channels A, B out of four channels A, B, C, D are needed to transmit data, then two clock phases correspond to channels A, B. gated to double the bit rate output to the two channels A and B, disabling the other two channels C and D. The manner in which data bits are interlaced at various rates is shown in the following table.

[Table] In the embodiment of the present invention, the modem 11 operating as a master modem receives a coded port configuration/channel allocation request from a cooperative data processing device such as the CPU 12. This port configuration is controlled by code provided by mode shift register 17 or other storage. The code from shift register 17 selects the port configuration, similar to the manually selected code in conventional multi-port modems. Comparator 19 is
The port components from CPU 12 and the code pointed to by mode shift register 17 are continuously compared. Here, the CPU shifts to shift register 1.
If a port configuration different from the code indicated by 7 is requested, comparator 19 outputs a shift register control signal indicating that register 17 is to prepare a new code. The shift register control information, after being appropriately delayed by timing device 21, is used to change the mode indication code in shift register 17, thereby causing multi-port modem 11 to assume a new port configuration. The delay in timing device 21 provides sufficient time for second or slave modem 13 to responsively set a port configuration corresponding to the newly requested port configuration at master modem 11. Served. During this delay time, the master modem 11
transmits a signal to the slave modem 13, which is interpreted as a transmission port configuration request by the modem 13. A device that operates similarly to master modem 11 is used for modem 13 to configure the slave modem 13 port configuration. In particular, the comparator 23
A new port configuration request is detected by comparing the request code and the mode instructed by the shift register 25. Comparator 23 generates shift register control information in response to the detection. After an appropriate delay, this information is sent to the modem 13 in order to change its port configuration.
Adjust the mode indication provided by shift register 25. Here, when implementing the apparatus described with reference to FIG. 1, it is very advantageous to define channel priority and reordering rules in order to simplify the circuit network and make use of existing modem line rules. It turns out that it is. Therefore, the port configuration mode selection sequence, according to an embodiment of the invention,
Defined as shown in the figure and table below.

TABLE The table shows exemplary port configurations at various data rates. As an example, the following description is per second
This is for the case of 9600 bits. The table represents four ports, namely channels A, B, C, D.
Indicates a mode code consisting of two bits. The code consists of "1", "0", and "no involvement" indicated by the letter "X". The port array corresponding to a particular mode code is in the same column as that mode code. Furthermore, each mode is displayed with an arbitrary number from 1 to 5. As shown in the table, mode 3 has the highest priority.
In , each channel A, B, C, and D transmits at a rate of 2400 bits per second. In mode 5, which has the fifth priority, channel D is missing, as indicated by "0" in the "D" column of the port request in the table. In mode 5, channels B and C transmit 2400 bits per second and channel A operates at 4800 bits per second.
Modes 4 and 2 have the third priority, and one of them is actually selected. Mode 4
In the case of , channels A and B are each per second.
Selected to operate at 7200 bits and 2400 bits, and in mode 2, channels A and B
are both chosen to operate at 4800 bits per second. Finally, in mode 1, which has a priority of 4, the mode selection code indicates that only channel A is active, and channel A is
Works with bits. Therefore, according to the embodiment shown in the table, channel A is preferentially transferred to channel D. The lowest priority channel in operation defines the mode. For example, mode 3 depends only on whether channel D is active or not, not whether channels B and C are active or inactive. Channel A is a re-priority channel and its transmission rate increases according to the loss of closure of other channels. Also, as described above, the automatic port alignment circuitry of embodiments of the present invention compares the channel requested by the new request code with the channel operation signal.
Here, if you need to add or delete ports,
Appropriate signals are generated to switch the remote (slave) modem in the same manner as the local (master) modem. The master and slave modems are controlled along the same sequence to achieve the desired port configuration. In this embodiment, the sequence is determined by the flow shown in FIG. According to this sequence, mode 5, mode 4 or 2 or mode 1
A modem operating in one of the modes
Add the necessary channels to return directly to mode 3. However, to transition the sequence to another mode, for example from mode 1 to mode 5, mode 5
Before switching to Mode 3, it is necessary to return to Mode 3. Furthermore, transitioning the sequence from a high level mode to a low level mode requires jumping between intermediate modes. It has been found that this sequencing technique is advantageous in simplifying the signaling techniques used to communicate mode changes to the slave or remote modem. This signaling technique is used in the DCD (data carrying detection) drop to the slave modem, which allows the slave's port array circuit to drop the channel to achieve the new mode. In addition, in the above configuration, the missing channel is always
The amount that determines when a slave retires is also an unimportant port. Also, the missing channel is no longer used at all, and it is not easy to directly return it to a mode in which it is operational again. This is because the time division slot for the channel has already been set. Therefore, in order to make the channel operational again in the embodiment,
The port array circuit returns to mode 3 where all channels are active, and the circuit continues to operate to remove active channels until the desired state is reached. Here, channel A is always active, so the DCD closure code () for this channel is
Used to initiate a return to the highest mode, Mode 3. From mode 3 onwards, the normal DCD channel missing sequence is used to establish the appropriate configuration. An example of the above sequence technique is shown in FIGS. 4 and 5. In this example, DTR (Data Terminal Ready) is used as the control code at the master installation location. Note that DTR was originally configured as mode 3, then changed to mode 1, and then changed to mode 5. FIG. 4 shows the loss of channels from mode 3 to mode 1. Initially, the master modem is in the normal idle state of mode 3, where the DTR signals for channel A and channel D are logic signals according to the logic rules in the table. Similarly, the slave modem is in the normal idle state of mode 3, with the DCD levels of channels A and D representing logic signals.
To change to mode 1, change channels B, C, and D.
Initiated by the master when the DTR level simultaneously drops to zero. It is then delayed for 200ms (milliseconds), during which time the
A DCD missing code is transmitted to the slave modem.
There is a 100ms (millisecond) delay in the slave modem, which causes the slave to detect the missing DCD and start changing modes through modes 5 and 4 and finally to mode 1. Here, it is desirable that the intermediate modes such as modes 5 and 4 are passed at a high speed as shown at 0.416 ms in FIG. Also, a relatively long delay in the master causes the slave to go to mode 1 before the master returns to mode 1. In this way, the slave prepares for a new master configuration operation. Similarly, multiple operational ports may be missing. When the master returns to mode 1, normal transmission at 9600 bits per second resumes on the single A channel. FIG. 5 shows the port passage process as the device transitions from mode 1, where only channel A is active, to mode 5, where channels A, B, and C are active. Initially, the master modem is in mode 1 with the DTR signal for channel A being positive. Similarly, the slave modem is set to mode 1 with the DTR signal for channel A being positive. To change to mode 5, channels B and C
Starts when the DTR signal for the device goes high. A 200ms delay is then applied at the master, during which it transmits all marks to the slave, indicating that the DCD signal for channel A is missing. Also, after detecting the loss, there is a 100ms delay in the slave, during which time the slave switches to mode 3 in which all four channels operate. That is, due to the delay time, the slave switches to mode 3 before the master switches to mode 3. Once the master is in mode 3, the D channel
A low DTR signal detects that mode 3 is still inappropriate. The process of FIG. 4 is then repeated, dropping channel D and returning to mode 5. Also, the DCD missing code for channel D is transmitted to the slave, which becomes mode 5 after a delay. Also, a longer delay is performed on the master, which causes it to switch to mode 5 following the slave, with a rate of 4800 bits per second through channel A, a rate of 2400 bits per second through channel B, and a rate of 2400 bits per second through channel C.
Start normal transmission at a rate of 2400 bits. That is, FIG. 5 shows a technique for returning to a mode in which all channels are activated to add a port. In addition, since DTR and DCD signals are general signals used for transmission between modems,
DTR and DCD are used. It should be noted that other signals may be used to provide mode codes to master and slave modems. For example, in addition to the above DTR level, an RTS (request to send) signal is used by the master to indicate the mode code. Also, as mentioned above, the command signal indicates when the data source desires to transmit data, ie, when it desires a transmission channel. The example currently used is RTS
It is. Another example is DTR (data terminal preparation)
This signal is used as a command signal from the data source and is highly dependent on the nature of the data source. If the data source is, for example, a tape reader, and priority is given to transmitting for several minutes, alternating with periods of rest, it is usually desirable to use RTS as a command signal. RTS exists only as long as the transmission is taking place, and by using RTS,
Bandwidth redistribution is effectively performed during times when data sources are not transmitting and there is no RTS. In other words, clock allocation is performed effectively. The above process is generally not suitable when the data sources are mutually influencing sources such as data processing terminals. This is because mutual influence sources tend to switch quickly between transmitting and resting states, and this fast mode switching is undesirable. In this case, the command signal may be a DTR, which is present during the time the data source is communicating with a device such as a CPU (Central Processing Unit) at the slave end of the line. Bandwidth redistribution depends on the data source.
This only happens when DTR is missing. This is because the data source no longer wants to communicate with the CPU. Also, as mentioned above, it is known in the art to prepare the DCD during the presence of data transmission from the master modem and to immediately set the DCD low upon reception of the encoded RTS. The conventional format for coded RTS is a predetermined period of all 1's, which is a predetermined period of time for channels B, C, and D.
200ms, but the format may be a predetermined digital codeword left to the encoding RTS. The slave modem detects coded RTS on channels B, C, and D. As mentioned above, this sensing operation is delayed to provide reliable sensing (otherwise false positives could occur due to the relatively long string of all 1's during normal data transmission). FIG. 6 shows a simplified block diagram of a general circuit for controlling port configuration in a master or slave modem using the sequence and code techniques described in conjunction with FIGS. 3-5. This circuit consists of a magnitude comparator 31, two timers 3
3, 35, and a mode indication shift register 37. The magnitude comparator 31 receives the inverse channel activity signals B, C, and D from the mode indication shift register 37 and the port DTR signal (master).
Or compare with the inverse of the port DCD signal (slave). The channel activity signal is supplied by converting the output code of the shift register by a decoder 36. The inputs of the magnitude comparator 31 are collectively shown as X and Y, respectively. X and Y are for each of modes 1 to 5,
The channel array signal specified by () is input. For example, at the speed of 9600 bits/second shown in the table, the channel array signal for mode 3 is 0000, the channel array signal for mode 5 is 0001, and the channel array signal for mode 4 is 0000.
Or, the channel arrangement signal of mode 2 is 0011, and the channel arrangement signal of mode 1 is 0111. Thereby,
Modes 3, 5, 4, or 2 and 1 are given a ranking by the channel arrangement signal. In the present invention, the order of the channel arrangement signal representing the current channel arrangement and the order of the channel arrangement signal representing the newly requested channel arrangement are compared, and the current channel arrangement is changed based on the difference, and the order of the channel arrangement signal representing the newly requested channel arrangement is changed. This point will be described in more detail below. The relationship between X and Y indicates the nature of the desired channel reconstruction. For example, if it is necessary to transition from mode 1 to mode 5, input to
ABCD is 0111 and input to Y is 0001
It is. In this case, X>Y, and the return signal from the comparator 31 is sent to the shift register 3 via the timer 35.
7, and mode 3 having the youngest channel arrangement signal is automatically stored in the shift register. The mode 3 storage signal is activated by a timer 35 which delays the period as described in conjunction with FIGS. 4 and 5.
delayed by On the other hand, if X is smaller than Y, the advance signal from the comparator 31 is sent to the shift register 37 via the timer 33, and the shift register is set to a mode having a channel array signal of the next lower order. This advance signal indication indicates that the channel is to be deleted. In this case as well, the shift register 37 is appropriately delayed by the timer 33. After one step, ie, if the channel arrangement signal is lowered by one and the comparison still holds X<Y, the shift register 37 steps again to the next mode. When X finally equals Y, the desired mode is active channel configuration (channel active mode).
The ideal state is equal to . Of course, the importance of the comparison function is in determining whether channels should be added or removed. It should be noted that, without departing from the purpose of the present invention, various logical rules may be considered from appropriate channel codes to provide the above instructions. FIG. 7 is an embodiment of the present invention, and shows a circuit operating as a master or slave reconfiguration control. Master/slave selection is accomplished by a control strap controlling the multiplexer, as described below. In master mode, control signals, such as DTR signals from the four ports 16, are provided to a four-bit latch 39. The contents of this latch are multiplexer 4.
1 to the least significant port control logic 43 and then to the comparator 45. The comparator compares the channel activity signal at input Shift timer 47 and storage timer 49 are connected via multiplexer 51 and control mode indicating shift register 53. Output when X=Y, i.e. comparator 45
The idle output of latch 39 is fed back to latch control logic 55 which controls the operation of latch 39. Control strap 57 selects master and slave modes of circuit operation. In master mode, when a change in state is detected such that the idle output of 4-bit unit 45 no longer indicates to hold or hook. Latch control logic 55 includes AND gate 59, NAND gate 61, and delay/flip-flop 63. AND gate 59 receives an input indicating that X≠Y and an input indicating that the master mode has been selected. Assuming this condition is met, the output of AND gate 56 will be as high as the output of normally reset delay flip-flop 63. In this case, NAND gate 61
generates a low output, which indicates a latched condition and causes the output of latch 39 to be transferred to the least significant port control logic 43. In slave mode, multiplexer 4
1 gates the DCD signal from the bus and sends it to the minimum major port control logic 43. In addition, in the master mode, the multiplexer 51 is controlled by the control strap.
The 200 ms output of the shift timer 47 and the 200 ms output of the storage timer 49 are gated and supplied to the shift register 53. In the slave mode, the multiplexer 51 selects 100 ms output from the storage timer and shift timer. The multiplexer functions as a gate switch, as is well known in the art. In master mode, latch 39 is normally sampled at high speed. However, the sample clock output from comparison AND gate 65 is eliminated. If X≠Y, that is, if the master mode is not selected, NAND gate 61 will be at a high level, indicating the sample mode of latch 39. Delay flip-flop 63 is provided for appropriate operation when Mode 3 is selected. In this case, ADTR changes (lowers as above) and sends a signal to the slave modem. Here, to prevent the comparator from falsely detecting an imbalance and hooking the low level ADTR signal,
The delay flip-flop responds to the memory command by
Prohibits hooking until ADTR returns to its original state (high). As shown in FIG. 7, this operation is accomplished by clocking a delay flip-flop at board speed and applying the store command to its D input and the ADTR signal to its reset input. Thus, latch 39 prevents interruptions or input changes until the port configuration circuitry has completely processed the preceding change. That is, a control signal is generated and sent to the slave, and this signal generation is completed before a new interrupt for a new port configuration request is given. The code selected by multiplexer 41 is then sent to least significant port control logic 43 where priority is given to the least significant channel. The presence of the least major channel causes the more major channel information to become active, filling the "idle" state of the table. Channel A information is not affected by this circuit. The operation and configuration of the minimum main logic gate is shown in the table below.

[Table] *Note: Negative logic As mentioned earlier, the magnitude comparator is
Standard digital comparator, X>Y, X<Y,
and outputs X=Y output. These outputs each indicate the desired channel mode of the actual configuration. Idle output of comparator 45, that is, X=
The Y output is returned to hook latch control logic 55. The hooking operation starts when X≠Y. X
The <Y output reaches the shift timer 47, and the shift timer 47 gives a shift command to the mode shift register 53 after the time selected by the multiplexer 51 has elapsed, as described above. The storage instruction for X<Y triggers the storage timer 49, which causes the mode 3 code to be stored in the shift register 53 after a period of time selected by the multiplexer 51. Both the shift timer and storage timer are conventional counter circuits. Upon receiving a shift command from shift timer 47, the shift register rapidly shifts its output state until equality is detected by comparator 45. This function is logically represented by AND gate 50 in FIG. AND gate 50 gates the clock into the shift register in response to a shift signal from timing device 47 until the IDLE output is output by comparator 45. In storage mode 3, if they are not equal, the X<Y output of comparator 45 is activated to perform the above shift sequence. When not in a shift or store state, mode shift register 53 simply holds the mode support at its output. This mode support is added to the appropriate strap to select either Mode 2 or Mode 4. Therefore, in the overall operation of master mode,
When a new channel configuration is requested, comparator 4
5 outputs either a shift command or a storage command. These commands are delayed by timers 47 and 49 as appropriate. During this delay, the signal is sent through the channel to the slave modem. In particular, missing channels are detected by the output of the 4-bit latch 39, and the appropriate missing code is sent out. The device for delivering this missing code is supplied with a latch output via line 40. This device is well known in the art. When mode 3 needs to be stored, line 42 from comparator 45
As soon as the above storage instruction is detected, the code is sent to the slave modem. Also, timers 47 and 49
At the end of the timing cycle determined by
An appropriate shift or store command is sent to shift register 53. The mode of the shift register then returns to comparator 45 to determine whether another change in the shift register contents is required or whether an equal condition has been achieved. In the slave configuration, latch 39 is connected to multiplexer 4
It can be switched by 1. The basic circuit operation is
DCD signal is minimum significant bit logic and comparator 45
They are the same except that they are supplied to Timer multiplexer 51 selects a shorter period and the DCD command is present for the duration of the timing cycle and the circuit is operational again. According to the present invention, in order to synchronize port configuration switching at physically separated modem installation locations,
Other methods may also be used. One method is to provide a second FSK (Frequency Shift Keyed) channel or an entirely unrelated data path to transmit the synchronization information. This type of current channel path may be built into the data set or provided by an external device. Alternatively, a modem user can synchronize two devices by synchronizing the port configurations at predetermined times. For example, at the end of the day, a device such as a computer or data terminal (DTE) that cooperates with each physically separate modem is responsible for a special channel for the special transport of data. Here, since the modem control device at each installation location has a master clock, synchronization according to these master clocks is a simple matter.
Since the master clocks at each modem location are synchronized, no signaling is required between the two data sets. The data sets are each strapped to serve a request at the location where the data terminal equipment (DTE) interfaces. Also, because each modem is under master control, this synchronization technique is called master/master. Operating in master/master mode allows the operator to have direct software control of the port arrangement by supplying the operator's own synchronization code. As will be apparent from the foregoing, various modifications may be made to the embodiments described above without departing from the purpose and spirit of the invention. It will therefore be appreciated that, within the scope of the appended claims, the invention may be practiced otherwise than as described above.

[Brief explanation of drawings]

FIG. 1 is a schematic block system diagram of a device according to an embodiment of the present invention, FIG. 2 is a block diagram of a channel allocation circuit, FIG. 3 is a diagram showing the port rearrangement selection order of an embodiment of the present invention, and FIG. 4 is a channel diagram. FIG. 5 is a flowchart showing the operation of the embodiment of the present invention when the channel is changed from the operating state to the non-operating state; FIG. FIG. 6 is a block diagram showing a port arrangement selection circuit according to an embodiment of the invention, and FIG. 7 is a schematic diagram of a port rearrangement circuit used in a master or slave modem according to an embodiment of the invention. 11... Master modem, 12... Central processing unit, 13... Slave modem, 14... Data terminal equipment, 15... Transmission channel, 16... Four ports, 17... Mode shift register, 19
... Comparator, 21 ... Timing device, 23 ...
Comparison device, 25...shift register, 31...magnitude comparator, 33, 35...timer, 3
7...Mode instruction shift register, 39...4 bit latch, 41...Multiplexer, 43...Minimum major port control logic, 45...Comparator, 47...Shift timer, 49...Storage timer, 51... Multiplexer, 53...Mode instruction shift register, 57...
...Control strap, 59...And gate, 61
... NAND gate, 63 ... Delay/flip-flop, 65 ... Comparison and gate, 101 ... Clock selection circuit, 103 ... Multiplexing/separating circuit, 1
04...Or Gate, 105...Clock, 10
6...Modem transmission circuit.

Claims (1)

[Claims] 1 Channel arrangement of N ways of multiple channel communication is multiplexed using all or part of N channels, using ranks from 1st to Nth, with the younger the rank, the more multiplexing is performed. In an automatic channel arrangement device that automatically switches to a new channel arrangement using a channel arrangement signal that allocates channels such that the number of channels increases and the number of multiplexed channels decreases as the ranking goes lower, the current channel arrangement is holding means for holding and outputting a current channel arrangement signal representing a new channel arrangement; means for outputting a requested channel arrangement signal representing a newly requested channel arrangement; and the current channel arrangement signal and the requested channel arrangement signal. If the order of the requested channel arrangement signal is lower than that of the current channel arrangement signal, a return signal is output, while the order of the current channel arrangement signal is lower than that of the requested channel arrangement signal. a comparison means for outputting an advance signal if the current channel arrangement signal is the same as that of the requested channel arrangement signal, and outputting a continuation signal when the order of the current channel arrangement signal is the same as that of the requested channel arrangement signal; After returning to the array, the channel array sequentially moves to lower channel arrays, and when the channel array has the same order as the requested channel array signal, that channel array is set, while the advance signal causes the channel array to sequentially shift to lower channel arrays from the current channel array. When the channel arrangement is shifted to the channel arrangement and becomes the channel arrangement of the same order as the requested channel arrangement signal, that channel arrangement is set, and furthermore, the control means controls so that the current channel arrangement is maintained as it is by the continuation signal, clock output means for outputting N types of clocks; and at least one type of clock for each channel to be multiplexed, so that the bit rate of multichannel communication is kept constant even when the channel arrangement changes. or allocating means for allocating one or more types of clocks. 2. In the device according to claim 1, the return signal is sent to the holding means via the first delay means, while the advance signal is sent to the holding means via the first delay means.
An automatic channel alignment device, characterized in that it is sent to said holding means via delay means. 3. The automatic channel arrangement device according to claim 1, further comprising switching means that operates in either a master configuration or a slave configuration. 4. The automatic channel arrangement device according to claim 1, wherein the requested channel arrangement signal is obtained by a standard modem handshake signal. 5. In the device according to claim 1, the allocation means drops the channels one by one as the ranking becomes lower, and transfers the clock assigned to the dropped channel to the clock assigned to the dropped channel as the ranking becomes lower. An automatic channel arrangement device characterized in that it is configured to additively allocate channels to channels that remain even after aging.