JPS60143043A - Data multiplex system - Google Patents

Abstract

PURPOSE:To improve the line utilizing rate by minimizing the change in the channel number in a data transceiver transmitting/receiving data with multiplex. CONSTITUTION:In switching a transmission/reception signal speed to a low speed, the data speed of the lowest channels CH-B-CH-D is brought into the low speed. When the data speed of all the channels CH-A-CH-D is set to the minimum data speed, the use of the channel of the lowest order is stopped and the transmission signal speed is brought into the low speed. That is, when the number is set to a combination number 2 and the multiplex signal speed is switched from 9,600bit/sec to 7,200bit/sec, the data speed of the channel A is brought into 4,800bit/sec and the data speed of the channel B is brought into 2,400bit/sec and the number of channels is unchanged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a data transmitting/receiving device that multiplexes and transmits/receives digital data signals. In particular, it relates to the relationship between channels and data rates of data transmitting/receiving devices.

[Description of prior art]

2. Description of the Related Art Data transmitting/receiving devices that multiplex digital data signals and transmitting/receiving them are known to have a function of switching the transmission/reception signal speed to a lower speed when there is quality deterioration in a line. In such a device, for example, 9600
(bits/second) is switched to 7,200 (bits/second) or 4,800 (bits/second).This improves transmission characteristics by lowering the transmission speed of the line, and it remains constant even when the line deteriorates. The purpose is to transmit signals with the above quality, that is, with an error rate below a certain level.

The maximum number of channels that can be multiplexed by such a data transmitting/receiving device is determined by the signal speed, and the combination of channel data speeds is also limited by the signal speed.

Table 1 shows an example of conventional multiplexing. This conventional example is C
(This is based on the multiplexing example shown in ITT Recommendation V29.) Combination numbers O to 4 in Table 1 are set at the time of device installation.

The case where combination number 2 is set will be explained as an example. If the multiplexing signal rate is 9600 (bits/second), the data rate of channel A (CH-A) is 4800 (bits/second) and the data rate of channel B (CH-B) is 4800 (bits/second). If you switch the multiplexing signal rate to 7200 (bits per second), the data rate to the channel is 2400 (bits per second).
bit/sec], the data rate of channel B is 2400
The data rate of channel C (CH-C) is set to 2400 (bits/second) and multiplexed.

In this example, if the multiplexing signal rate is 9600 (bits/second), channel A and channel B are multiplexed, and if the multiplexing signal rate is 7200 (bits/second), channel A and channel B are multiplexed. Channel B and channel C are multiplexed, where channel C has a multiplexed signal rate of 7200
(bits per second). Therefore, channel C is not normally used and is used only when switching signal speeds when the line deteriorates. There are bad drawbacks.

[Purpose of the invention]

An object of the present invention is to minimize the change in the number of multiplexed channels when switching the multiplexed signal speed, and to improve line usage efficiency.

[Features of the invention]

The data multiplexing method of the present invention is characterized in that when the multiplexing signal speed is switched to a low speed, the change in the number of channels is minimal and there is no increase in the number of channels.

[Explanation based on examples]

In the data multiplexing system of the present invention, the maximum number of channels that can be multiplexed and the combination of channel data rates are determined by the transmission and reception signal rates, as in the conventional example. However, when the transmission/reception signal speed is switched to a low speed, the data speed of the channel set to the highest speed is reduced to cope with the change.

The channel set to the highest speed is generally channel A, but there may be other channels with the same speed. In this case, the data rate of the lowest channel is reduced.

If the data rate of all channels is set to the lowest data rate, use of the lowest channel is discontinued and the transmission/reception signal rate is reduced. In this case, unused channels occur, but this occurs only when the line deteriorates, and can be avoided by selecting the multiplexing combination number.

Table 2 shows a multiplexing example of the first embodiment of the present invention.

The case where combination number 2 is set will be explained as an example.

If the multiplexing signal rate is 9600 (bits/second), the data rate of channel A is 4800 (bits/second).
, the data rate of channel B is set to 4800 (bits per second) and multiplexed.The multiplexed signal rate is set to 72
00 (bits/second), channel A
The data rate for channel B is 4800 bits/second, and the data rate for channel B is 2400 bits/second.

In this way, the number of channels does not change when the multiplexing signal rate is switched.

FIGS. 1 and 2 are block diagrams of an example of a data rate receiving apparatus for multiplexing according to the first embodiment of the present invention.

FIG. 1 is a block diagram of the transmitting circuit. The shift register 10 includes an input signal line, a clock generation circuit I6,
It is connected to the flip-flop 11.

Flip-flop 11 is connected to shift register 1o, multiplexer 12, and clock generation circuit 16. The multiplexer 12 includes a flip-flop 11 and
It is connected to the read-only memory and the transmitter 15. Read-only memory 13 is connected to multiplexer 12 and counter I4. The counter 14 is connected to the read-only memory 13, the transmitter 15, and the clock generation circuit 16. The transmitter 15 is connected to the multiplexer 12, the counter 14, the clock generation circuit 16, and the transmission line IIO. Clock generation circuit 16 is connected to shift register 10 , flip-flop 11 , and transmitter 15 . Furthermore, the read-only memory 13 and the clock generation circuit 16 are connected to a device (not shown) that stores combination number information.

The shift register 10 is synchronized with a clock signal supplied by a clock generation circuit 16 and receives a register selection signal 1.
8, the transmission data 17 of each channel is input.

Further, the shift register 1o performs serial-to-parallel conversion on the input serial data and outputs parallel outputs Ql and Q2-.

The flip-flop 11 receives these parallel outputs Q1, Q2-.
and stores the data of each channel in parallel.

The flip-flop 11 is initialized by the transmission signal block signal 112 sent out by the transmitter 14 .

The multiplexer 12 refers to the corresponding number of the flip-flop 11 according to the address specification of the read-only memory order,
The 1-bit data is sent to the transmitter 15.

The read-only memory 13 specifies an address to the multiplexer 12 according to the modulation timing information from the counter 14 and the combination number information % 113.

The counter 14 counts the number of bits of data based on the transmission timing signal 111 of the transmitter 15 and provides data transfer bit information to the read-only memory 13. Furthermore, the counter I4 is initialized by the transmission signal block signal 112 sent out by the transmitter 15.

The transmitter I5 outputs the transmission data 19 of the multiplexer 12 to the transmission path 110, and outputs a transmission timing signal 111 and a transmission signal block signal 112. This transmission signal block signal 112 is, for example, a symbol clock in multilevel code transmission, and provides the timing for modulating the transmission data 19.

The clock generation circuit 16 generates a clock signal for input.

FIG. 2 is a block diagram of the receiving circuit. Receiving section 20
is connected to the counter 14, the clock generation circuit I6, and the addressable launch circuit 21. The addressable circuit 21 is connected to the receiving section 20, the read-only memory IJ13, and the flip-flop 11. flip flop 1
1 is connected to the addressable launch circuit 2I, the receiving section 20, and the parallel-to-serial conversion circuit 22.

The parallel-to-serial conversion circuit 22 is connected to the flip-flop 11, the receiving section 20, and the clock generation circuit 16.

The read-only memory register is connected to the addressable launch circuit 21, the counter 14, and the clock generation circuit 16.

The receiving unit 20 receives data from the transmission path 110 and sends the received data 114 to the addressable wireless circuit 21 . Furthermore, the receiving section 20 outputs a transmission timing signal 111 and a transmission signal block signal 112.

The addressable launch circuit 21 serially receives the received data 114 according to the address given by the read-only memory.
is accumulated and sent to the flip-flop 11 as parallel data. The timing of data accumulation is provided by a transmission timing signal. The parallel-to-serial conversion circuit 22 serially converts the data of each channel and sends it out.

The other parts have the same function as the transmitter circuit, so they will not be explained here.

FIG. 3 is a time chart showing the operation of the transmitting circuit. This example shows a combination number 4 at a multiplexing signal rate of 9600 (bits/second), where Dn is the nth data bit, ADn is the nth bit of channel A, and BDn is the channel CDn indicates the n-th bit of channel C, and DDn indicates the n-th bit of channel D.

Tables 3 to 5 show multiplexing examples of the second embodiment of the present invention.

These tables list the minimum data rate for each channel at 2400
(bits/second), the multiplexing signal rate is 14
．． Examples of multiplexing when switching between 4 C kilobits/second (Table 3), 12 kilobits/second (Table 4) and 9600 bits/second (Table 5) are shown.

In this way, according to the present invention, as the number of multiplexed combinations increases, line usage efficiency is less likely to decrease.

(Hereinafter, the main margin) (Effects of the Invention) As explained above, the data multiplex communication system of the present invention has the effect of minimizing unused channels and not reducing line usage efficiency.

[Brief explanation of drawings]

FIG. 1 shows a transmitting circuit of a data transmitting/receiving device that performs multiplex combination according to a first embodiment of the present invention. FIG. 2 is a receiving circuit of a data transmitting/receiving device that performs multiplexing and combination according to the first embodiment of the present invention. FIG. 3 is a time chart showing the operation of the transmitting circuit. 10... Shift register, 11... Flip-flop, 12... Multiplexer, 13... Read-only memory, 14... Counter, 15... Transmission section, 16
... Clock generation circuit, 20... Receiving section, 21...
-Addressable Lanochi circuit, 22...Parallel-serial conversion circuit. Patent applicant: NEC Corporation Representative Patent attorney: Naotaka Ide

Claims (1)

[Scope of Claims] A data transmitting/receiving device having a plurality of channels for multiplexing digital data signals and transmitting/receiving them, and having means for switching the transmitting/receiving signal speed to a lower speed when there is quality deterioration in the line, the above means is characterized in that when switching the transmitting/receiving signal speed to a low speed, the data speed is sequentially switched to a low speed for channels having lower speeds starting from the channel set to the highest speed, and the number of channels after switching does not exceed the number of channels before switching. data multiplexing method.