JPH01302824A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01302824A JPH01302824A JP63132973A JP13297388A JPH01302824A JP H01302824 A JPH01302824 A JP H01302824A JP 63132973 A JP63132973 A JP 63132973A JP 13297388 A JP13297388 A JP 13297388A JP H01302824 A JPH01302824 A JP H01302824A
- Authority
- JP
- Japan
- Prior art keywords
- recognition pattern
- area
- bonding
- pellet
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000008188 pellet Substances 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 description 6
- 238000003909 pattern recognition Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
Description
【発明の詳細な説明】
［発明の目的コ
（産業上の利用分野）
本発明は半導体装置に関するもので、特に単体素子用ペ
レットに形成されるバイポーラトランジスタまたはＭＯ
Ｓトランジスタに使用されるものである。Detailed Description of the Invention [Objective of the Invention (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a bipolar transistor or MO
This is used for S transistors.
（従来の技術）
従来、この様な半導体装置では、半導体素子ペレット上
において、ベース電極及びペースボンディング領域と、
エミッタ電極及びエミッタボンディング領域が、半導体
素子ペレット上の仮想中心線を軸とし点対称で、かつ電
極形状が似ていた。(Prior Art) Conventionally, in such a semiconductor device, a base electrode and a paste bonding region are formed on a semiconductor element pellet,
The emitter electrode and the emitter bonding region were point symmetrical about the virtual center line on the semiconductor element pellet, and the electrode shapes were similar.
第５図はこのことを示す素子平面図で、図中１は半導体
素子ペレットであり、半導体素子ペレット１上に、ベー
ス電極２及びベースボンディング領域３と、仮想中心線
Ａ、Ｈに対し点対称な位置にあり形の似たエミッタ電極
４及びエミッタボンディング領域５が、ＡＩ等の金属に
より配線されている。FIG. 5 is a device plan view showing this. In the figure, 1 is a semiconductor device pellet. On the semiconductor device pellet 1, a base electrode 2 and a base bonding region 3 are placed symmetrically with respect to virtual center lines A and H. Emitter electrodes 4 and emitter bonding regions 5, which are located at similar positions and have similar shapes, are wired using metal such as AI.
（発明が解決しようとする課題）
この様に構成された半導体装置では、電極形状が対称形
状であるため、ボンディングマシンのパターン認識が困
難で、認識精度不足による不良、例えば半導体素子ペレ
ット１上のペースボンディング領域３と外囲器エミッタ
端子をボンディングしてしまう等の問題がしょうじるこ
とがあった。(Problems to be Solved by the Invention) In the semiconductor device configured in this way, since the electrode shape is symmetrical, it is difficult for the bonding machine to recognize the pattern. Problems such as bonding between the pace bonding region 3 and the envelope emitter terminal may occur.
そのため全面的なボンディングの自動化ができず、人手
にたよらざるをえず、効率が悪く、コスト的に不利であ
った。またボンディング領域のボンディングマシンの上
記パターンの認識不足があり、かつ電極形状がボンディ
ングマシンに認識させるに充分良好な形状とは云いがた
いため、ボンディングのずれが生じ、信頼性の面におい
ても不利であった。さらにボンディング領域からはみだ
した部分が帰還容量（例えばバイポーラトランジスタの
コレクタ、ベース間容量）の増加の原因となり、特性的
にもバラツキが生じるなどの問題点があった。For this reason, it was not possible to fully automate bonding, and it had to be done manually, which was inefficient and disadvantageous in terms of cost. In addition, there is insufficient recognition of the above-mentioned pattern by the bonding machine in the bonding area, and it is difficult to say that the shape of the electrode is good enough for the bonding machine to recognize, resulting in bonding misalignment, which is disadvantageous in terms of reliability. there were. Furthermore, the portion protruding from the bonding region causes an increase in feedback capacitance (for example, capacitance between the collector and the base of a bipolar transistor), resulting in problems such as variations in characteristics.
本発明は、半導体素子ペレット上の各ボンディング領域
の側にそれぞれ形の異なる認識パターンを導入する等に
より、ボンディングマシンのパターン認識精度を向上さ
せボンディング不良を無くし、ボンディングを自動化す
ることにより、信頼性の向上を図ることを目的とする。The present invention improves the pattern recognition accuracy of the bonding machine by introducing recognition patterns of different shapes on the side of each bonding area on the semiconductor element pellet, eliminates bonding defects, and improves reliability by automating bonding. The purpose is to improve the
［発明の構成］
（課題を解決するための手段と作用）
本発明は、半導体ペレットの仮想中心線に対し対称的に
電極が配置される半導体装置において、前記ペレット表
面の互に対称となる一方の領域に或る認識パターンを配
置し、他方の領域に前記酸る認識パターンとは異なるこ
とが識別可能な他の認識パターンを配置したことを特徴
とする半導体装置である。[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a semiconductor device in which electrodes are arranged symmetrically with respect to a virtual center line of a semiconductor pellet. A semiconductor device is characterized in that a certain recognition pattern is arranged in a region, and another recognition pattern that can be identified as being different from the acidic recognition pattern is arranged in the other region.
即ち本は発明は、例えば半導体素子ペレット主表面で、
ペース電極とペースボンディング領域はペレットの中心
を軸に点対称の位置にありかつ形の似ているエミッタ電
極とエミッタボンディング領域を有し、半導体素子ペレ
ット上のペースボンディング領域の側に例えば凹形部を
有する認識パターンを設け、又エミッタボンディング領
域の側に、例えば凸形部ををする認識パターンを設ける
ことにより、似ているパターンを確実に認識できるよう
にして、上記目的を達成するものである。That is, the present invention is based on, for example, the main surface of a semiconductor element pellet,
The emitter electrode and the emitter bonding area are located in point-symmetrical positions with respect to the center of the pellet and have similar shapes, and there is a concave portion, for example, on the side of the paste bonding area on the semiconductor element pellet. By providing a recognition pattern having a convex shape, for example, on the side of the emitter bonding region, similar patterns can be reliably recognized, thereby achieving the above object. .
（実施例）
以下、本発明の実施例について、図面を参照して説明す
る。第１図、第２図は本発明の実施例のパターン平面図
で、第１図は電極対称方向がペレット側面に傾斜してい
る場合の例、第２図は電極対称方向がペレット側面に平
行の場合の例である。これら図において１は半導体素子
ペレット、２は半導体素子ペレット上に形成したベース
電極、３はペースボンディング領域、４はベース電極２
と点対称の位置にあり、かつ形が似ているエミッタ電極
、５はペースボンディング領域３と点対称の位置にあり
、かつ形が似ているエミッタボンディング領域であるこ
とは第５図の場合と同様である。また６はペースボンデ
ィング領域領域３の側にあり凹形をしたペースボンディ
ング用認識パターン、７はエミッタボンディング領域５
の側にある凸形をしたエミッタボンディング用認識パタ
ーンで、これらそれぞれの電極及びボンディング領域は
ＡＩ等の金属により配線されている。又上記認識パター
ン６．７の形成は、ＡＩ等の金属により、電極及びボン
ディング領域を形成する際に同時にバターニングすると
よい。他にポリＳｉやＳｉＮのような膜により、上記認
識パターンを形成することもある。Ａ、Ａ’ 、Ｂ、Ｂ
’ は仮想中心線である。上記認識パターンの大きさの
設定は例えば第３図の如くであるが、半導体素子ペレッ
ト１上の中心を軸に仮想的に４分割した（第１図に対応
）時にボンディング領域のあるエリア、ここでは斜線部
９のペースボンディングエリアにて説明する。８はペレ
ット１上の絶縁膜、斜線部１０はエミッタボンディング
エリアであるが、ペースボンディングエリア９において
、このエリア９内で占めるＡノ等の金属電極２，３．６
の面積と、絶縁膜８等のＡノ金属以外の部分の面積の割
合が、１：１になるように、ペースボンディング用認識
パターン６の大きさを調整する。斜線部１０のエミッタ
ボンディングエリアの認識パターン７の大きさの設定に
ついても同様である。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. Figures 1 and 2 are pattern plan views of examples of the present invention. Figure 1 is an example where the electrode symmetry direction is inclined to the side surface of the pellet, and Figure 2 is an example where the electrode symmetry direction is parallel to the pellet side surface. This is an example of the case. In these figures, 1 is a semiconductor element pellet, 2 is a base electrode formed on the semiconductor element pellet, 3 is a paste bonding region, and 4 is a base electrode 2.
The emitter electrode 5 is located in a point symmetrical position to the paste bonding region 3 and has a similar shape, and is an emitter bonding region 5 that is located in a point symmetrical position to the paste bonding region 3 and has a similar shape. The same is true. Further, 6 is a concave pace bonding recognition pattern located on the side of the pace bonding area 3, and 7 is the emitter bonding area 5.
This is a convex recognition pattern for emitter bonding on the side, and the respective electrodes and bonding regions are wired with metal such as AI. Further, the recognition pattern 6.7 is preferably formed by patterning a metal such as AI at the same time as forming the electrode and bonding region. Alternatively, the recognition pattern may be formed using a film such as poly-Si or SiN. A, A', B, B
' is the virtual center line. The size of the recognition pattern described above is set as shown in FIG. 3, for example. When the semiconductor element pellet 1 is virtually divided into four parts around the center (corresponding to FIG. Now, the pace bonding area shown in the shaded area 9 will be explained. 8 is an insulating film on the pellet 1, and the shaded area 10 is the emitter bonding area.In the paste bonding area 9, the metal electrodes 2, 3, 6, etc.
The size of the recognition pattern 6 for pace bonding is adjusted so that the ratio between the area of the insulating film 8 and the area of the portion other than the metal A is 1:1. The same holds true for setting the size of the recognition pattern 7 in the emitter bonding area of the shaded area 10.
上記実施例によれば、ペースボンディングエリア内のＡ
Ｊ！等の金属の面積とＡ、ｆ？金属以外の部分の面積の
割合を１：１に近づけることにより、ボンディングマシ
ンのパターン認識精度を向上するとともに、凹型形状及
び凸型形状の異なる認識パターンをそれぞれの電極近傍
に挿入配置することにより、ボンディングの誤認識を無
くすことができた。これにより、ボンディングの自動化
を行うことができ、コストを低減させることができた。According to the above embodiment, A in the pace bonding area
J! The area of metal such as A, f? By bringing the area ratio of non-metal parts closer to 1:1, the pattern recognition accuracy of the bonding machine is improved, and by inserting and arranging different recognition patterns of concave and convex shapes near each electrode, We were able to eliminate misrecognition of bonding. This made it possible to automate bonding and reduce costs.
又パターン認識精度の向上、つまり上記１：１の面積比
による認識精度の向上、と、異なる認識パターン（凸形
と凹形）を認識できることによる誤認識解消とにより、
ボンディングのずれが無くなり、特性のバラツキもなく
、又高信頼性の半導体装置を可能にした。In addition, by improving pattern recognition accuracy, that is, by improving recognition accuracy due to the above-mentioned 1:1 area ratio, and by eliminating recognition errors by being able to recognize different recognition patterns (convex and concave shapes),
This eliminates bonding misalignment, eliminates variations in characteristics, and enables highly reliable semiconductor devices.
なお本発明は実施例のみに限られず種々の応用が可能で
ある。例えば本発明でいう「対称」とはマシンがパター
ン認識する能力の範囲内でのことである。第４図は前実
施例よりも更に実際化したもののパターン平面図で、こ
こではエミッタ電極４．５が、ペース電極２，３より太
くなっていて完全対称とは云いがたい。これは電流量の
相異に寄因するが、マシンのパターン認識能力に応じて
第４図の電極パターンも対称形と見なされることが多々
ある。また実施例ではバイポーラトランジスタを例にし
たが、電界効果トランジスタ等の素子の場合にも適用で
きる。この場合コレクタがドレイン、エミッタがソース
、ペースがゲートに対応する。また実施例では、前記ペ
レット上の中心番軸に前記ペレット表面を仮想４分割し
た時に、該分割されたペレット表面のボンディング領域
のあるエリア内の前記認識パターンを含む電極面積とそ
れ以外の部分の平面積の割合が、前記４分割領域中の１
領域ににおいて、好適な１：１の場合を説明したが、両
面積比が１ ： ０．７〜１．５の範囲がパターン認識
しやすい範囲であり、このような範囲としてもよい。ま
た実施例ではペレット表面に、ボンディングマシンが認
識するパターンのみを図示したが、ペレット表面にマシ
ンが認識しない他のパターンがあっても可である。Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, "symmetrical" in the present invention is within the ability of a machine to recognize patterns. FIG. 4 is a plan view of a pattern that is more practical than the previous embodiment, in which the emitter electrode 4.5 is thicker than the pace electrodes 2 and 3, and it cannot be said that they are completely symmetrical. Although this is due to the difference in the amount of current, the electrode pattern in FIG. 4 is often considered to be symmetrical depending on the pattern recognition ability of the machine. Further, in the embodiment, a bipolar transistor is used as an example, but the present invention can also be applied to elements such as field effect transistors. In this case, the collector corresponds to the drain, the emitter corresponds to the source, and the pace corresponds to the gate. Further, in the embodiment, when the pellet surface is virtually divided into four parts along the center axis on the pellet, the electrode area including the recognition pattern in an area of the bonding region of the divided pellet surface and the other part are divided. The proportion of the plane area is 1 in the quadrant area.
In the area, a preferable case of 1:1 has been described, but a range where the ratio of both areas is 1:0.7 to 1.5 is a range in which pattern recognition is easy, and such a range may also be used. Further, in the embodiment, only the patterns recognized by the bonding machine on the pellet surface are illustrated, but it is also possible that there are other patterns on the pellet surface that are not recognized by the machine.
［発明の効果コ
以上説明した如く本発明によればボンディングマシンの
パターン認識精度を向上させ、ボンディング不良をなく
し、ボンディングを自動化することにより、信頼性の向
上が図れる等の利点を有した半導体装置が提供できるも
のである。[Effects of the Invention] As explained above, the present invention provides a semiconductor device that has advantages such as improving the pattern recognition accuracy of a bonding machine, eliminating bonding defects, and automating bonding to improve reliability. can be provided.
第１図ないし第４図は本発明の各実施例のパターン平面
図、第５図は従来装置のパターン平面図である。
１・・・半導体素子ペレット、２・・・ベース電極、３
・・・ペースボンディング領域、４・・・エミッタ電極
、５・・・エミッタボンディング領域、６・・・ペース
ボンディング用認識パターン、７・・・エミッタボンデ
ィング用認識パターン、８・・・絶縁膜、９・・・ペー
スボンディングエリア、１０・・・エミッタボンディン
グエリア。
出願人代理人 弁理士 鈴 江 武 彦ｊｌ！１図
第２図
第３図
第４ｒｌＡ
第５図1 to 4 are pattern plan views of each embodiment of the present invention, and FIG. 5 is a pattern plan view of a conventional device. 1... Semiconductor element pellet, 2... Base electrode, 3
... Pace bonding area, 4... Emitter electrode, 5... Emitter bonding region, 6... Recognition pattern for pace bonding, 7... Recognition pattern for emitter bonding, 8... Insulating film, 9 ... Pace bonding area, 10... Emitter bonding area. Applicant's agent Patent attorney Takehiko Suzue! Figure 1 Figure 2 Figure 3 Figure 4 rlA Figure 5
Claims (4)
が配置される半導体装置において、前記ペレット表面の
互に対称となる一方の領域に或る認識パターンを配置し
、他方の領域に前記或る認識パターンとは異なることが
識別可能な他の認識パターンを配置したことを特徴とす
る半導体装置。(1) In a semiconductor device in which electrodes are arranged symmetrically with respect to the virtual center line of a semiconductor pellet, a certain recognition pattern is arranged in one mutually symmetrical region of the surface of the pellet, and the recognition pattern is arranged in the other region. What is claimed is: 1. A semiconductor device characterized in that another recognition pattern that can be identified as being different from the recognition pattern is arranged.
識パターンが平面凹形状をしていることを特徴とする請
求項１に記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the one recognition pattern has a convex planar shape, and the other recognition pattern has a concave planar shape.
タまたはソース、他方がトランジスタのベースまたはゲ
ートであることを特徴とする請求項１に記載の半導体装
置。(3) The semiconductor device according to claim 1, wherein one of the symmetrical electrodes is an emitter or a source of a transistor, and the other is a base or gate of a transistor.
仮想４分割した時に、該分割されたペレット表面のボン
ディング領域のあるエリア内の前記認識パターンを含む
電極面積とそれ以外の部分の平面積の割合が、前記４分
割領域中の１領域において、１：０．７〜１．５である
ことを特徴とする請求項１に記載の半導体装置。(4) When the pellet surface is virtually divided into four parts with the center of the pellet as an axis, the electrode area including the recognition pattern in the bonding area area of the divided pellet surface and the planar area of the other parts 2. The semiconductor device according to claim 1, wherein a ratio of 1:0.7 to 1.5 in one of the four divided regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63132973A JPH01302824A (en) | 1988-05-31 | 1988-05-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63132973A JPH01302824A (en) | 1988-05-31 | 1988-05-31 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01302824A true JPH01302824A (en) | 1989-12-06 |
| JPH0533822B2 JPH0533822B2 (en) | 1993-05-20 |
Family
ID=15093821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63132973A Granted JPH01302824A (en) | 1988-05-31 | 1988-05-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01302824A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316735B1 (en) | 1996-11-08 | 2001-11-13 | Ricoh Company, Ltd. | Semiconductor chip mounting board and a semiconductor device using same board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52115177A (en) * | 1976-03-24 | 1977-09-27 | Hitachi Ltd | Semiconductor device |
| JPS58152432A (en) * | 1982-03-05 | 1983-09-10 | 早瀬 政志 | Moving float with line winder |
-
1988
- 1988-05-31 JP JP63132973A patent/JPH01302824A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52115177A (en) * | 1976-03-24 | 1977-09-27 | Hitachi Ltd | Semiconductor device |
| JPS58152432A (en) * | 1982-03-05 | 1983-09-10 | 早瀬 政志 | Moving float with line winder |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316735B1 (en) | 1996-11-08 | 2001-11-13 | Ricoh Company, Ltd. | Semiconductor chip mounting board and a semiconductor device using same board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0533822B2 (en) | 1993-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH01302824A (en) | Semiconductor device | |
| JP2621420B2 (en) | Bonding pads for semiconductor devices | |
| JPS6086851A (en) | Resin sealed type semiconductor device | |
| JPS63114224A (en) | Semiconductor device | |
| JPH02308563A (en) | Lead frame | |
| JPS5844593Y2 (en) | Beam lead type semiconductor device | |
| JPS63192258A (en) | Semiconductor device | |
| JPH01276635A (en) | Semiconductor device | |
| JPS5851526A (en) | Semiconductor element pellet and semiconductor device with said pellet | |
| JPS6127178Y2 (en) | ||
| JP3363639B2 (en) | Integrated circuit device and method of manufacturing the same | |
| JPH01283948A (en) | Resin sealed semiconductor device | |
| JPH0462942A (en) | Semiconductor device | |
| JPS63197354U (en) | ||
| JPH02111929U (en) | ||
| JPS62261163A (en) | Lead frame for cerdip type semiconductor device | |
| JPH05152587A (en) | Mis diode | |
| JPH03181158A (en) | Ic package | |
| JPH01176930U (en) | ||
| JPH03229450A (en) | Semiconductor package | |
| JPH0546702B2 (en) | ||
| JPH0499339A (en) | Tool for wire bonder | |
| JPH022615A (en) | Manufacture of semiconductor device | |
| JPH032660U (en) | ||
| JPH0483355A (en) | Packaging method of semiconductor element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |