JPH01302773A - Semiconductor tension sensor - Google Patents

Semiconductor tension sensor

Info

Publication number
JPH01302773A
JPH01302773A JP13308188A JP13308188A JPH01302773A JP H01302773 A JPH01302773 A JP H01302773A JP 13308188 A JP13308188 A JP 13308188A JP 13308188 A JP13308188 A JP 13308188A JP H01302773 A JPH01302773 A JP H01302773A
Authority
JP
Japan
Prior art keywords
layer
insulating layer
semiconductor layer
single crystal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13308188A
Other languages
Japanese (ja)
Other versions
JPH0716014B2 (en
Inventor
Yuji Hase
長谷 裕司
Mikio Bessho
別所 三樹生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13308188A priority Critical patent/JPH0716014B2/en
Publication of JPH01302773A publication Critical patent/JPH01302773A/en
Publication of JPH0716014B2 publication Critical patent/JPH0716014B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Pressure Sensors (AREA)
  • Measuring Fluid Pressure (AREA)

Abstract

PURPOSE:To form a highly precise diaphragm part, and increase breakdown voltage by forming a first single crystal semiconductor layer on an etching stopper layer, followed by forming thereon, an intermediate insulating layer, and a second single crystal semiconductor layer on the insulating layer and a first single crystal semiconductor layer. CONSTITUTION:On a semiconductor substrate 11, an etching stopper layer 12 composed of an insulating layer formed on a diaphragm region. A first single crystal semiconductor layer 13 is formed on both the substrate 11 and the stopper layer 12. An intermediate insulating layer 16 is formed in the diaphragm region on the semiconductor layer 13. A second single crystal semiconductor layer 15 is formed on both the insulating layer 16 and the semiconductor 13. A piezo resistor 18 is formed in the surface of the semiconductor layer 15. The substrate 11 is etched from the lower part to the central part, and a recessed part 19 with a depth reaching the stopper layer 12 is formed. The upper part is formed in the diaphragm part 20. Thereby, the diaphragm part 20 is formed with high precision, and breakdown voltage is increased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体基板上部にピエゾ抵抗を形成した半
導体圧力センサに関し、特にダイヤフラム部を厚くした
改良にかかわる。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor pressure sensor in which a piezoresistor is formed on the upper part of a semiconductor substrate, and particularly relates to an improvement in which the diaphragm portion is thickened.

〔従来の技術〕[Conventional technology]

第4図は例えば特開昭62−288679号公報に示さ
れた従来の半導体圧力センサの直面図である。図におい
て、1は単結晶シリコンからなる半導体基板で1表面上
に絶縁層(810J 2>らなるエツチングストッパ層
(以Frストンバ層Jと称する)2が。
FIG. 4 is a front view of a conventional semiconductor pressure sensor disclosed in, for example, Japanese Unexamined Patent Publication No. 62-288679. In the figure, reference numeral 1 denotes a semiconductor substrate made of single-crystal silicon, and an etching stopper layer (hereinafter referred to as Fr-stone layer J) 2 made of an insulating layer (810J2) is formed on the surface of the semiconductor substrate 1.

ホトエツチングによりダイヤフラム部領域に形成されて
いる。3は基板l上及びストッパR2上にエピタキシャ
ル法により形成され、再結晶化された単結晶シリコン層
、4はこのシリコンWJ3土に形成された絶縁層(Si
n@)で、拡散用窓4aが形成されている。5は基板1
下面に形成された絶縁層(810m)、 6はシリコン
層3内にボロン注入により形成されたとニジ抵抗、7は
絶縁層5にエツチングにより#夫された中央穴から、エ
ツチングにより基板lに形成され、ストッパJ7J 2
に達した深ざにされた凹部で、上部に薄肉部のダイヤフ
ラム部8か形成されている。
It is formed in the diaphragm region by photo-etching. 3 is a single crystal silicon layer formed on the substrate l and stopper R2 by an epitaxial method and recrystallized, and 4 is an insulating layer (Si) formed on this silicon WJ3 soil.
n@), a diffusion window 4a is formed. 5 is board 1
An insulating layer (810 m) formed on the bottom surface, 6 is a resistor formed by implanting boron into the silicon layer 3, and 7 is a resistor formed in the substrate 1 by etching from a central hole etched in the insulating layer 5. , stopper J7J 2
It is a recessed part which has reached a depth of 100 cm, and a thin diaphragm part 8 is formed at the upper part.

こうして、ダイヤフラム部8が精度高い厚さの簿肉邪に
されている。
In this way, the diaphragm portion 8 is made to have a precise thickness.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記のような従来の半導体圧力センサでは、ストッパ層
2土の半導体層3は、多結晶シリコンを単結晶化処理し
ているため、余り厚くはできなく。
In the conventional semiconductor pressure sensor as described above, the semiconductor layer 3 of the stopper layer 2 cannot be made very thick because polycrystalline silicon is subjected to a single crystallization process.

例えば厚さ0.5μ倶程度で薄く、破壊耐圧が高くでき
ないという問題点があった。
For example, it is thin, with a thickness of about 0.5 μm, and has a problem in that it cannot have a high breakdown voltage.

この発明は、このような問題点を解決するためになされ
たもので、ダイヤフラム部が精度高い所要厚さに形成さ
れ、破壊耐圧を高くした半導体圧力センサを得ることを
目的としている。
The present invention has been made to solve these problems, and an object thereof is to obtain a semiconductor pressure sensor in which a diaphragm portion is formed to a required thickness with high precision and has a high breakdown voltage.

〔課題を解決するための手段〕[Means to solve the problem]

この発明にかかる半導体圧力センサは、半導体基板上に
絶縁層からなるエツチングストッパ層ヲダイヤフラム部
領域に形成し、このストッパ層上及び基板上に第1の単
結晶半導体層を形成し、この半導体層上に中間絶縁層を
形成し、この中間絶縁層上及び第1の半導体層上に第2
の単結晶子導体層を形成し、この第2の半導体層表面内
か、又はこの第2の半導体層上に形成した上層絶縁層上
にピエゾ抵抗を形成し、基板を下面から中央部にエツチ
ングにより上記ストッパ層に達する凹部を形成し、上部
を所要厚さのダイヤフラム部にしたものである。
In the semiconductor pressure sensor according to the present invention, an etching stopper layer made of an insulating layer is formed on a semiconductor substrate in a diaphragm region, a first single crystal semiconductor layer is formed on the stopper layer and the substrate, and the semiconductor layer An intermediate insulating layer is formed on the intermediate insulating layer, and a second semiconductor layer is formed on the intermediate insulating layer and the first semiconductor layer.
A single crystalline conductor layer is formed, a piezoresistor is formed in the surface of this second semiconductor layer or on an upper insulating layer formed on this second semiconductor layer, and the substrate is etched from the bottom surface to the center part. A recessed portion reaching the stopper layer is formed, and the upper portion is a diaphragm portion having a required thickness.

〔作用〕[Effect]

この発明においては、エツチングストッパ層上に第1の
単結晶半導体層を形成し、この半導体層の薄肉を補い所
要の厚さにするため、ざらに第1の半導体層上に中間絶
縁層を形成し、この絶縁層上及び第1の半導体層上に第
2の単結晶半導体層を形成しており、ダイヤフラム部が
所要の厚さに精度高く形成でき、破壊耐圧が高められる
In this invention, a first single crystal semiconductor layer is formed on an etching stopper layer, and an intermediate insulating layer is roughly formed on the first semiconductor layer in order to compensate for the thinness of this semiconductor layer and achieve a desired thickness. However, since a second single crystal semiconductor layer is formed on this insulating layer and on the first semiconductor layer, the diaphragm portion can be formed to a desired thickness with high precision, and the breakdown voltage can be increased.

〔実施例〕〔Example〕

第1図はこの発明による半導体圧力センサの一実施例の
町面図である。肉において、11は単結晶シリコンから
なる半導体基板、12はこの基板11上にダイヤフラム
部領域に形成された絶縁層(810sなどンからなるエ
ツチングストッパ層(以下「ストッパ層」と称する)、
13はストッパ層しよ及び基板l上に形成された第1の
単結晶シリコン層で。
FIG. 1 is a top view of one embodiment of a semiconductor pressure sensor according to the present invention. 11 is a semiconductor substrate made of single-crystal silicon; 12 is an etching stopper layer (hereinafter referred to as "stopper layer") made of an insulating layer (such as 810S) formed on the substrate 11 in the diaphragm region;
Reference numeral 13 denotes a stopper layer and a first single crystal silicon layer formed on the substrate l.

単結晶化のため例えば0.5μmと薄くなっている。1
4はシリコン層氏上にダイヤフラム部領域に形成された
中間絶縁層(810sなど)、bはこの中間絶縁層上及
び第1のシリコン層13上に形成された第2の単結晶シ
リコン層%16はこの第2のシリコン層15上に形成さ
れた上部絶縁層(810sなど)で、拡散用窓16&が
あけられている。17は基板UのF面に形成された′F
部絶縁層(810意などンで、中央部にダイヤフラム領
域に対応する開口部17aがあけられている。
Due to single crystallization, the thickness is, for example, 0.5 μm. 1
4 is an intermediate insulating layer (such as 810s) formed on the silicon layer in the diaphragm region, and b is a second single crystal silicon layer formed on this intermediate insulating layer and on the first silicon layer 13. is an upper insulating layer (810s, etc.) formed on this second silicon layer 15, in which a diffusion window 16& is opened. 17 is 'F formed on the F side of the substrate U.
An opening 17a corresponding to the diaphragm region is formed in the center of the insulating layer (810).

18は第2のシリコン層迅表向内に形成された拡散によ
るピエゾ抵抗、19は基板11に下方からエツチングに
よりストッパ層νに達する深さに形成された凹部で、こ
れにより、上部が所要厚さのダイヤフラム部加にされて
いる。なお、各ピエゾ抵抗迅を接続する電極配線及び上
部を覆う保護膜が施されているが1図示は略する。
18 is a piezoresistance formed by diffusion in the surface of the second silicon layer; 19 is a recess formed in the substrate 11 by etching from below to a depth reaching the stopper layer ν; The diaphragm part is added. Note that electrode wiring connecting each piezoresistor and a protective film covering the upper part are provided, but illustration thereof is omitted.

次に、上記圧力センサの製造を、第2図により説明する
。ます、第2図(IL)のように、単結晶シリコンから
なる半導体基板11の上面に絶縁層(例えば810−を
全面に形成してから、ダイヤフラム部領域を残し他を除
去し、実線で示すストッパ層成を形成する。
Next, the manufacture of the above pressure sensor will be explained with reference to FIG. First, as shown in FIG. 2 (IL), an insulating layer (for example, 810-) is formed on the entire upper surface of the semiconductor substrate 11 made of single crystal silicon, and then the diaphragm region is left and the rest is removed, as shown by the solid line. Forming a stopper layer.

つづいて、第2図(b)のように、ストッパ層化上と基
板11上にエピタキシャル法などにより多結晶シリコン
層を形成し、これをレーザアンニールなどにより第1の
単結晶シリコン層Bにする。
Subsequently, as shown in FIG. 2(b), a polycrystalline silicon layer is formed on the stopper layer and the substrate 11 by an epitaxial method or the like, and this is formed into a first single crystal silicon layer B by laser annealing or the like. do.

第2図(o)のように、第1のシリコン層B上に絶縁M
(例えば810m )を全面に形成してから、ダイヤフ
ラム領域を残し他を除去し実線で示す中間絶縁層14を
形成する。
As shown in FIG. 2(o), an insulating layer M is formed on the first silicon layer B.
(for example, 810 m 2 ) is formed over the entire surface, and then the diaphragm region is left and the rest is removed to form the intermediate insulating layer 14 shown by the solid line.

第26((1)のように、中間絶縁層14上と第1のシ
リコン層m上にエピタキシャル法などにより多結晶シリ
コン層を形成し、これをレーザアンニールナトニより第
2の単結晶シリコン層正にする。
26th (As in (1), a polycrystalline silicon layer is formed on the intermediate insulating layer 14 and the first silicon layer m by an epitaxial method, etc., and this is laser annealed to form a second single crystal silicon layer. Make it correct.

ついで、第2図(e)のように、上面及び下向に上部絶
縁層(例えば810處) 16及び下部絶縁層(例えば
810m ) 17を全面に形成してから、エツチング
により拡散窓16&と開口部17aとをあける。
Next, as shown in FIG. 2(e), an upper insulating layer (for example, 810 m) 16 and a lower insulating layer (for example, 810 m) 17 are formed on the upper surface and downward, and then the diffusion window 16 and the opening are formed by etching. Open the part 17a.

′Pj2図(r)のように、第2のシリコン層15表向
内に拡散などによりピエゾ抵抗用を形成する。
'Pj2 As shown in FIG. 2(r), a piezoresistor is formed in the surface of the second silicon layer 15 by diffusion or the like.

さらに、第1[dに示すように、基板11を下方からエ
ツチングし、ストッパ層12iC達する深ざの回想 部を形成する。
Furthermore, as shown in the first step d, the substrate 11 is etched from below to form a recessed portion with a depth that reaches the stopper layer 12iC.

次に、各ピエゾ抵抗用を接続し外部に引出す電極配線を
既知の方法により形成するか1図示は略する。
Next, electrode wiring for connecting each piezoresistor and extending it to the outside is formed by a known method (not shown).

このように、ストッパfil 1,2上に第1のシリコ
ン層13、中間絶縁層14及び第2のシリコン會15が
重ねられ、正確な厚さに形成されており、下方の基板1
1に凹部]9を形成することにより、上部が所要厚さの
ダイヤフラム部美にされる。
In this way, the first silicon layer 13, the intermediate insulating layer 14, and the second silicon layer 15 are stacked on the stoppers fil 1 and 2, and are formed to have an accurate thickness.
By forming the recessed part 9 in the upper part of the diaphragm part 1, the upper part can be made into a diaphragm part having the required thickness.

第8Nはこの発明の半導体圧力センサの他の実施例を示
すl?r血向である。半導体基板11上にストッパ層り
、第1のシリコン層13を形成し、このシリコン層13
上に中間絶に#14%第2のシリコン層15?形成し、
′F部絶縁層17を形成し、凹部19を形成した構造は
、上記第1図の場合と同様である。
No. 8N shows another embodiment of the semiconductor pressure sensor of the present invention. I'm really into it. A stopper layer is formed on the semiconductor substrate 11 and a first silicon layer 13 is formed.
#14% second silicon layer 15 in the middle on top? form,
The structure in which the F section insulating layer 17 is formed and the recess 19 is formed is the same as that shown in FIG. 1 above.

しかし、次の手段が異なる。However, the following methods are different.

nは第2のシリコン層15上にダイヤフラム領域に形成
された上部絶縁層(例えIf 5ins ) 、ρはこ
の絶縁層上に、エピタキシャル法などで形成され単結晶
シリコンにされ、エツチングにより形成されたピエゾ抵
抗である。
n is an upper insulating layer (for example If 5ins) formed on the second silicon layer 15 in the diaphragm region, and ρ is an upper insulating layer formed on this insulating layer by an epitaxial method or the like to form single crystal silicon, and then etched. It is a piezo resistance.

(発明の効果〕 以上のようにこの発明によれば、半導体基板上に絶縁層
からなるエツチングストッパ層を形成し、この上と基板
上に第1の単結晶半導体層を形成し、この半導体層上に
中間絶縁層を形成し、この絶縁層上と第1の半導体層上
に第2の単結晶半導体層を形成し、この第2の半導体層
衣面円か、又はその半導体層上に形成した上部絶縁層上
かにピエゾ抵抗を形成し、基板?下部から中央E’tl
S kエツチングし、上記ストッパ層に達する凹部を形
成し、上部をダイヤフラム部としたので、ダイヤフラム
部か精度高い所要厚さにされ、破壊耐圧を筒くすること
ができ、測定圧力範囲が広められる。
(Effects of the Invention) As described above, according to the present invention, an etching stopper layer made of an insulating layer is formed on a semiconductor substrate, a first single crystal semiconductor layer is formed on this and on the substrate, and the etching stopper layer is formed on the semiconductor substrate. forming an intermediate insulating layer thereon; forming a second single crystal semiconductor layer on the insulating layer and the first semiconductor layer; and forming an intermediate insulating layer on the second semiconductor layer or the semiconductor layer; A piezoresistor is formed on the upper insulating layer, and the center E'tl is formed from the bottom of the substrate.
S k is etched to form a recess that reaches the stopper layer, and the upper part is the diaphragm part, so the diaphragm part can be made to the required thickness with high accuracy, the breakdown pressure can be made cylindrical, and the measurement pressure range can be expanded. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明による半導体圧力センサの一実施例の
断面図、第2図は第1図の圧力センサの製造方法を工桿
順に示す説明図、第8図はこの発明の″P導体圧カセン
サの他の実施例の断面図、第4図は従来の半導体圧力セ
ンサの断面図である。 M中、11は半導体基板、12はエツチングストッパ層
、13は第1の単結晶半導体層(単結晶シリコン層)、
14は中間絶縁層、15は第2の単結晶半導体層(単結
晶シリコン層)、摺はピエゾ抵抗、 19は凹部、頭は
ダイヤフラム部、21は上部絶縁層。 nはピエゾ抵抗である。 なお、図中同一符号は同−又は相当部分を示す。
FIG. 1 is a sectional view of an embodiment of a semiconductor pressure sensor according to the present invention, FIG. 2 is an explanatory diagram showing the manufacturing method of the pressure sensor of FIG. 4 is a sectional view of a conventional semiconductor pressure sensor. In M, 11 is a semiconductor substrate, 12 is an etching stopper layer, and 13 is a first single crystal semiconductor layer (single crystal semiconductor layer). crystalline silicon layer),
14 is an intermediate insulating layer, 15 is a second single-crystal semiconductor layer (single-crystal silicon layer), the slide is a piezoresistor, 19 is a recessed portion, the head is a diaphragm portion, and 21 is an upper insulating layer. n is a piezoresistance. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims]  絶縁層からなるエッチングストッパ層が上面にダイヤ
フラム領域に形成された半導体基板、この基板上と上記
エッチングストッパ層上に形成された第1の単結晶半導
体層、この半導体層上にダイヤフラム領域に形成された
中間絶縁層、この絶縁層上と上記第1の半導体層上に形
成された第2の単結晶半導体層、この第2の半導体層表
面内か、又はこの第2の半導体層上にダイヤフラム領域
に形成された上部絶縁層上かに形成されたピエゾ抵抗を
備え、上記基板を下方から中央部をエッチングし上記エ
ッチングストッパ層に達する深さの凹部を形成し、上部
をダイヤフラム部にしたことを特徴とする半導体圧力セ
ンサ。
A semiconductor substrate having an etching stopper layer formed on the upper surface thereof in a diaphragm region, a first single crystal semiconductor layer formed on this substrate and the etching stopper layer, and a first single crystal semiconductor layer having a diaphragm region formed on the semiconductor layer. a second single crystal semiconductor layer formed on the insulating layer and the first semiconductor layer; a diaphragm region within the surface of the second semiconductor layer or on the second semiconductor layer; A piezoresistor is formed on the upper insulating layer formed on the substrate, and the center portion of the substrate is etched from below to form a recessed portion deep enough to reach the etching stopper layer, and the upper portion is a diaphragm portion. Features of semiconductor pressure sensor.
JP13308188A 1988-05-30 1988-05-30 Semiconductor pressure sensor Expired - Lifetime JPH0716014B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13308188A JPH0716014B2 (en) 1988-05-30 1988-05-30 Semiconductor pressure sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13308188A JPH0716014B2 (en) 1988-05-30 1988-05-30 Semiconductor pressure sensor

Publications (2)

Publication Number Publication Date
JPH01302773A true JPH01302773A (en) 1989-12-06
JPH0716014B2 JPH0716014B2 (en) 1995-02-22

Family

ID=15096404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13308188A Expired - Lifetime JPH0716014B2 (en) 1988-05-30 1988-05-30 Semiconductor pressure sensor

Country Status (1)

Country Link
JP (1) JPH0716014B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5672551A (en) * 1994-03-18 1997-09-30 The Foxboro Company Method for manufacturing a semiconductor pressure sensor with single-crystal silicon diaphragm and single-crystal gage elements

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5672551A (en) * 1994-03-18 1997-09-30 The Foxboro Company Method for manufacturing a semiconductor pressure sensor with single-crystal silicon diaphragm and single-crystal gage elements

Also Published As

Publication number Publication date
JPH0716014B2 (en) 1995-02-22

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