JPH01295445A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01295445A
JPH01295445A JP63124912A JP12491288A JPH01295445A JP H01295445 A JPH01295445 A JP H01295445A JP 63124912 A JP63124912 A JP 63124912A JP 12491288 A JP12491288 A JP 12491288A JP H01295445 A JPH01295445 A JP H01295445A
Authority
JP
Japan
Prior art keywords
layer
barrier metal
substrate
ccd
pda
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63124912A
Other languages
Japanese (ja)
Inventor
Shigeru Osawa
滋 大澤
Susumu Kimijima
君島 進
Shoichi Inoue
正一 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63124912A priority Critical patent/JPH01295445A/en
Publication of JPH01295445A publication Critical patent/JPH01295445A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

PURPOSE:To improve the yield of devices, by forming a barrier metal layer between an In layer and a Cu layer when a bump electrode is formed on a substrate, and forming a mushroom shape for the shape of the Cu layer and the barrier metal layer after plating. CONSTITUTION:When a bump electrode is formed on a substrate 1, a barrier metal layer 12 is inserted between a Cu layer 11 and an In layer 13. The shape of the Cu layer 11 and the barrier metal layer 12 is formed in a mushroom shape when the layers 11 and 12 are plated. Therefore, alloy reaction between the In layer and the Cu layer 11 does not occur when the In layer 13 is fused. Therefore, the In layer 13 sufficiently remains. After a charge transfer device (CCD) and a photodiode array(PDA) undergo pressure welding, the PDA and the CCD are not separated when they are cooled. Since the In layer 13 is not lowered when the In layer 13 is fused, the pressure welding with the PDA is carried out positively, and electric short circuits are eliminated. In this way, the yield of the devices is improved.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、基板上に形成した多数の赤外線検知素子と、
前記基板とは別の基板」二に形成した信号処理素子とを
結合した赤外線撮像装置における接続部のバンプ電極の
形成方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention provides a method for detecting infrared rays, which includes a large number of infrared sensing elements formed on a substrate,
The present invention relates to a method for forming a bump electrode at a connecting portion in an infrared imaging device in which a signal processing element formed on a substrate other than the substrate is bonded.

(従来の技術) 赤外線撮像素子には数種類のものが提案されているが、
ここでは赤外線を赤外線検知素子としてフォトダイオー
ド・アレイ(以下PDAと略す)で受光し、その光電変
換機能により生じた電気信号を電荷転送素子(以下CO
Dと略す)で処理する赤外線電荷転送素子(以下IR−
CODと略す)を用いて説明する。
(Prior art) Several types of infrared imaging devices have been proposed, but
Here, infrared rays are received by a photodiode array (hereinafter referred to as PDA) as an infrared detection element, and an electric signal generated by the photoelectric conversion function is transferred to a charge transfer element (hereinafter referred to as CO).
An infrared charge transfer element (hereinafter referred to as IR-
(abbreviated as COD).

IR−CODでは、赤外線センサーとして良好な半導体
材料である、たとえばInSb (インジウムアンチモ
ン)やHgCdTe (水銀カドミウムテルル)などの
基板に、フォトダイオードを格子状に形成したものを受
光部とし、この受光部で発生する電子を、各セルごとに
COD素子に転送して画像を得る。この方法はPDA、
及びCODの特性を各々最適化出来るので、最も一般的
に用いられる方法である。
In IR-COD, the light-receiving section is a substrate made of semiconductor materials that are good for infrared sensors, such as InSb (indium antimony) or HgCdTe (mercury cadmium telluride), and photodiodes formed in a grid pattern. The electrons generated in each cell are transferred to a COD element to obtain an image. This method uses PDA,
This is the most commonly used method because it can optimize the characteristics of and COD.

これらPDAとCODとの接続は、フォトダイオードの
数が多いこと、及びその配置からみて、ワイヤボンディ
ング法では困難である。そこで、検知素子およびCCD
の双方、あるいは一方に金属突起(バンプ)電極を設け
、検知素子とCCDとを対向させバンプ電極を利用して
接続させる方法が採られる。
Due to the large number of photodiodes and their arrangement, it is difficult to connect these PDAs and CODs by wire bonding. Therefore, the detection element and CCD
A method is adopted in which a metal protrusion (bump) electrode is provided on one or both of the two, and the detection element and CCD are faced to each other and connected using the bump electrode.

IR−CCDは冷却して用いられるので、PDAの構成
物質とCCDの構成物質であるSiとの膨張率が異なる
ために歪みを生じる。その歪みを吸収するために、バン
プ電極金属としては、軟らかいIn (インジウム)が
接続部の金属の一つとして用いられる。これは、Inが
塑性変形することにより、歪みを吸収させるものである
Since the IR-CCD is used after being cooled, distortion occurs because the expansion coefficients of the constituent material of the PDA and Si, which is the constituent material of the CCD, are different. In order to absorb the strain, soft In (indium) is used as one of the metals for the connection portion as the bump electrode metal. This allows In to absorb strain by plastically deforming.

バンプ電極を利用してPDAとCCDとを接続させる方
法には各種提案されている0例えば特許公開公報、昭6
1−210656号公報において、第3図、及び第4図
に示されている。第3図は、バンプ電極を形成したCC
D基板100であり、第4図は、筆者らが提案した。バ
ンプ電極の高さの均一化工程の一例である。
Various methods have been proposed for connecting a PDA and a CCD using bump electrodes.
1-210656, shown in FIGS. 3 and 4. Figure 3 shows a CC with bump electrodes formed.
The D substrate 100, shown in FIG. 4, was proposed by the authors. This is an example of a process of making the height of bump electrodes uniform.

即ち、第3図において、101はCODが形成されたS
L基板、102はCCDの入力部、103は絶縁膜、1
04はAQ電極、105はバリヤメタルのTi膜、10
6はメッキのときの電極として用いたCu膜、107は
メッキで形成したCu層、108は同じくメッキで形成
したIn層である。この5L−CODlooと平坦基板
、たとえばSi基板109とを第4図に示すように、圧
接・加熱してInを溶融させた後、Si基板109を分
離することにより、メッキにおいてばらつきのあった複
数のバンプ電極表面の高さを均一にした後、  PDA
と圧接して接続させていた。第4図における108a。
That is, in FIG. 3, 101 is S where COD is formed.
L substrate, 102 is an input part of CCD, 103 is an insulating film, 1
04 is the AQ electrode, 105 is the barrier metal Ti film, 10
6 is a Cu film used as an electrode during plating, 107 is a Cu layer formed by plating, and 108 is an In layer also formed by plating. As shown in FIG. 4, this 5L-CODloo and a flat substrate, for example, a Si substrate 109, are pressure-welded and heated to melt the In, and then the Si substrate 109 is separated. After making the height of the bump electrode surface uniform on the PDA
The connection was made by pressure contact. 108a in FIG.

108bは上記溶融後に分離したIn層を夫々示す。108b shows the In layers separated after the above melting.

(発明が解決しようとする課題) 叙上の従来の方法によるIR−CCDの製造には、以下
に述べる二つの課題がある。
(Problems to be Solved by the Invention) There are two problems described below in manufacturing an IR-CCD using the conventional method described above.

(i)Inを溶融させたときに、InとCuとが反応し
て金属間化合物を生成し、Inが かなり消費されてしまうことである。Inが少なくなる
と、先に述べたように、冷却したときに生じる歪みをI
nの塑性変形だけでは吸収出来なくなってInが切断し
てしまい、その結果としてPDAとCODとが剥離する
こともある。
(i) When In is melted, In and Cu react to form an intermetallic compound, and a considerable amount of In is consumed. As mentioned earlier, when In decreases, the strain that occurs when cooling is reduced by I
The plastic deformation of n alone cannot be absorbed and the In may be cut, resulting in separation of the PDA and COD.

(ii)  第4図に示すように、Inを溶融させたと
きにInがCODの表面に垂れてしまう ことがあった。その部分ではCODとPDAとが接続さ
れず、また、ときにはその部分で電気的にショートして
しまうこともあった。
(ii) As shown in FIG. 4, when In was melted, the In sometimes dripped onto the surface of the COD. The COD and PDA were not connected at that part, and sometimes electrical short-circuits occurred at that part.

この発明は上記従来の方法における課題を解決するため
になされたもので、バンプ電極を有する半導体装置の改
良された製造方法を提供するものである。
The present invention was made to solve the problems in the conventional methods described above, and provides an improved method for manufacturing a semiconductor device having bump electrodes.

〔発明の構成〕[Structure of the invention]

(課題を解決するための手段) 上記目的を達成するために1本発明では、基板上にバン
プ電極を形成するときに、Cu層とIn層の合金反応を
防止するために、Cu層とInJllの間にバリヤメタ
ル層を挿入し、またIn層がCCDの表面に垂れるのを
防ぐために、Cu層及びバリヤメタル層をメッキで形成
したときの形を「きのこ」形に形成する。すなわち、半
導体基板上に金属膜を形成する工程と、前記金属膜上に
フォトレジスト膜を形成する工程と、前記フォトレジス
ト膜に対し電極形成予定域に開口部を形成する工程と、
前記開口部に露出した前記金属膜上に選択メッキ法によ
りCu層、バリヤメタル層、およびIn層を順次積層さ
せ形成するとともにこのCu層とバリヤメタル層とで形
成される積層金属層の上部を前記フォトレジスト膜上に
一部延在させて「きのこ」形になるバンプ電極を形成す
る工程を含むものである。
(Means for Solving the Problems) In order to achieve the above object, in the present invention, when forming a bump electrode on a substrate, in order to prevent an alloy reaction between the Cu layer and the In layer, the Cu layer and the InJll A barrier metal layer is inserted between them, and in order to prevent the In layer from dripping onto the surface of the CCD, the Cu layer and barrier metal layer are formed into a "mushroom" shape when formed by plating. That is, a step of forming a metal film on a semiconductor substrate, a step of forming a photoresist film on the metal film, and a step of forming an opening in the photoresist film in an area where an electrode is to be formed.
A Cu layer, a barrier metal layer, and an In layer are sequentially laminated on the metal film exposed in the opening by a selective plating method, and the upper part of the laminated metal layer formed of the Cu layer and the barrier metal layer is exposed to the photo film. This includes the step of forming a "mushroom"-shaped bump electrode that partially extends on the resist film.

(作 用) この発明は、複数個形成されたバンプ電極表面を平坦基
板で圧接・加熱して溶融させた後、この平坦基板を分離
して複数のバンプ電極表面の高さを均一にするときに、
InとCuとの反応を防止してIn層が消費されるのを
防ぎ、またIn層がCCDの表面に垂れることを防ぐこ
とができる。すなわち、本発明により形成したバンプ電
極は、Cu層とIn層との間にバリヤメタル層が挿入さ
れているために。
(Function) The present invention is capable of applying pressure to a flat substrate on the surface of a plurality of bump electrodes, heating them and melting them, and then separating the flat substrate to make the heights of the surfaces of the plurality of bump electrodes uniform. To,
It is possible to prevent the In layer from being consumed by preventing the reaction between In and Cu, and also to prevent the In layer from dripping onto the surface of the CCD. That is, the bump electrode formed according to the present invention has a barrier metal layer inserted between the Cu layer and the In layer.

In層を溶融したときにIn層がCu層と合金反応を起
こさない。そのために、In層が十分残ることになり、
CCDとPDAとを圧接した後、冷却したときに。
When the In layer is melted, no alloy reaction occurs between the In layer and the Cu layer. Therefore, a sufficient amount of In layer remains,
When the CCD and PDA are pressed together and then cooled down.

PDAとCODとが剥離することがほとんどなくなって
信頼性が増す。また、同じ<In層を溶融したときにI
n層が垂れることがなくなるので、PDAとの圧接が確
実に行われ、また電気的にショートすることがなくなり
、歩留りが向上する。
Peeling of the PDA and COD is almost eliminated, increasing reliability. Also, when the same <In layer is melted, I
Since the n-layer does not sag, pressure contact with the PDA is ensured, and there is no electrical short-circuit, which improves yield.

(実施例) 以下、本発明の一つの実施例を図面を参照して説明する
(Example) Hereinafter, one example of the present invention will be described with reference to the drawings.

第1図(a)はバンプを形成する前の5i−CCDの要
部断面で、Si基板101の表面には信号入力コンタク
ト部102が80μsピツチで64 X 64個形成さ
れ、表面上には、例えば5i02等の絶縁層103と、
AQ電極104が形成されている。次に、この表面にT
i膜105゜次いでCu膜106を蒸着法によって形成
する。Ti膜105はバリヤメタルであり、Cu膜10
6はメッキ用の電極膜である。次いで、フォトレジスト
膜10を全面に形成し、次に、バンプ電極を形成する部
分に、2Ja++X20μsの開口部10aを設ける(
第1図(b))。
FIG. 1(a) is a cross section of a main part of a 5i-CCD before bumps are formed. On the surface of a Si substrate 101, 64×64 signal input contact portions 102 are formed at a pitch of 80 μs, and on the surface, For example, an insulating layer 103 such as 5i02,
An AQ electrode 104 is formed. Next, on this surface
The i film 105 and the Cu film 106 are then formed by vapor deposition. The Ti film 105 is a barrier metal, and the Cu film 10
6 is an electrode film for plating. Next, a photoresist film 10 is formed on the entire surface, and then an opening 10a of 2 Ja++×20 μs is provided in the part where the bump electrode is to be formed (
Figure 1(b)).

次に、この開口部10aに、まずCu層11を選択メッ
キ法で形成する。このCu層11は、例えば基板を硫酸
銅浴のCuメッキ液中に浸し、室温にて下地金属膜の前
記膜106を電極とし、所定電流にて十数分間分メッキ
を行なって形成する。これにより、フォトレジスト膜上
に一部延在した十数μmの厚さの「きのこ」形をしたC
u層11が形成される。なお、従来は次いでIn層をメ
ッキにて形成していたが。
Next, a Cu layer 11 is first formed in this opening 10a by selective plating. This Cu layer 11 is formed, for example, by immersing the substrate in a Cu plating solution in a copper sulfate bath, and plating at room temperature using the underlying metal film 106 as an electrode for ten minutes at a predetermined current. As a result, a “mushroom”-shaped C with a thickness of more than ten μm partially extending on the photoresist film is formed.
A u layer 11 is formed. Note that conventionally, an In layer was then formed by plating.

本発明ではその前にバリヤメタル層12をメッキする。In the present invention, a barrier metal layer 12 is plated before that.

バリヤメタルとしては、たとえばNiが推奨される。ま
た、ここで本発明のもう一つの特徴として、CuとNu
のメッキのあとの形を、「きのこ」形にする(第1図(
c)) 、 Cuを「きのこ」形にして。
For example, Ni is recommended as the barrier metal. In addition, as another feature of the present invention, Cu and Nu
The shape after plating is made into a "mushroom" shape (see Figure 1 (
c)), Cu is made into a “mushroom” shape.

そこにNiをメッキしても良いし、あるいは、柱状にメ
ッキしたCuのうえにNiをメッキして「きのこj形に
しても良い。どちらの方法でも同じ効果が得られる。こ
こでは先の方法で説明した。Ni層12は、たとえばワ
ット浴にて、所定の温度、所定の電流にて約十分メッキ
を行って形成する。厚さは、数ミクロンである。 N1
Jlをメッキしたのち、引続きIn層13をメッキする
。このIn層13は、基板をホウフッカ(硼弗化)浴に
浸し、所定の電流値にて数十分メッキを行うことにより
、杓子−の厚のIn層13を形成する。次にフォトレジ
スト膜10を除去し。
You can plate Ni there, or you can plate Ni on top of Cu that has been plated in a pillar shape to form a mushroom J shape. Either method will give you the same effect. Here, we will use the first method. The Ni layer 12 is formed by plating approximately enough at a predetermined temperature and a predetermined current in a Watts bath, for example.The thickness is several microns.N1
After plating Jl, an In layer 13 is subsequently plated. This In layer 13 is formed as thick as a ladle by immersing the substrate in a borofluoridation bath and plating at a predetermined current value for several minutes. Next, the photoresist film 10 is removed.

続いてバンプ電極部以外のCu膜106、及びTi1i
105をエツチングで除去して本発明にかかるCCD基
板1のバンプ電極が完成する(第1図(d))。
Subsequently, the Cu film 106 other than the bump electrode part and the Ti1i
105 is removed by etching to complete the bump electrode of the CCD substrate 1 according to the present invention (FIG. 1(d)).

以上述べたような製造方法によれば、In層とCu層と
の間にバリヤメタルとしてNi層が挿入されているので
、第2図に示すように、今までと同じくバンプ電極を形
成したCCD基板里と、 CCD基板上に対向してSi
基板109とを、所定の圧力で圧接し、加熱してIn層
108を溶融させた後、CCD基板よとSi基板109
を分離するプロセスでInとCuとが反応しない。この
ため、CCDとPDAとのバンプ結合に寄与するInの
量が多くなるので、信頼性が高くなる。
According to the manufacturing method described above, the Ni layer is inserted as a barrier metal between the In layer and the Cu layer, so as shown in FIG. and Si facing on the CCD substrate.
After pressing the substrate 109 with a predetermined pressure and heating to melt the In layer 108, the CCD substrate and the Si substrate 109 are bonded together.
In and Cu do not react in the process of separating In and Cu. Therefore, the amount of In that contributes to bump bonding between the CCD and PDA increases, resulting in higher reliability.

またNiをメッキした後の形状が、「きのこj形になっ
ているので、In層108が溶融したときにCCD表面
に垂れることがほとんどなくなり歩留りも向上する。ま
た、このプロセスで先に提案した方法の特徴であるバン
プ電極の高さの均一化も問題なく同時に達成出来る。こ
の様にしてInの量が十分残っており、またバンプ電極
の高さを均一にしたCCD基板とPDAとを、対応する
端子電極を突合わせ 4て一体化することにより多数の
端子電極の接続が確実に行われ、信頼性のあるIR−C
CDを歩留り良く得ることが出来る。
In addition, since the shape after Ni plating is mushroom-shaped, when the In layer 108 is melted, it hardly drips onto the CCD surface, which improves the yield. Uniform bump electrode heights, which is a feature of this method, can be achieved at the same time without any problems.In this way, a sufficient amount of In remains, and a CCD substrate and PDA with uniform bump electrode heights can be used. By butting and integrating the corresponding terminal electrodes, the connection of multiple terminal electrodes is ensured, resulting in reliable IR-C.
CDs can be obtained with a high yield.

本発明は上記実施例に限られるものでなく、その趣旨を
逸脱しない範囲で種々変形実施することが出来る5例え
ば上記説明では、バリヤメタルとしてNi層を用いて説
明したが、Niの他の金属、例えばpt層、Zn層等を
用いても同様の効果を得ることが出来る。
The present invention is not limited to the above-described embodiments, and can be modified in various ways without departing from the spirit of the invention.5For example, in the above explanation, a Ni layer is used as the barrier metal, For example, the same effect can be obtained by using a PT layer, a Zn layer, or the like.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、基板上にバンプ電極
を形成するときに、 In層とCu層との間にバリヤメ
タル層を形成するので、CCDとPDAとを圧接した後
、冷却したときPDAとCCDとが剥離することがほと
んどなくなり信頼性が増す。
As described above, according to the present invention, when forming bump electrodes on a substrate, a barrier metal layer is formed between an In layer and a Cu layer. Peeling between the PDA and CCD is almost eliminated, increasing reliability.

また、Cu層とバリヤメタル層をメッキした後の形状が
「きのこ」形になっているので、In層が溶融したとき
にCCD面に垂れることがほとんどなくなり、歩留りも
向上する。
Furthermore, since the Cu layer and the barrier metal layer are plated into a "mushroom" shape, when the In layer is melted, it hardly hangs down on the CCD surface, improving the yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(d)はこの発明にかかる半導体装置の
製造方法を工程順に示すいずれも断面図、第2図はこの
発明にかかるバンプ電極高さの均一化工程を説明するた
めの断面図、第3図は従来の半導体装置の製造方法を説
明するための断面図、第4図は従来のバンプ電極高さの
均一化工程を説明するための断面図である。 1 ・CCD基板     10・・・フォトレジスト
膜10a・・・(フォトレジスト膜の)開口部11・・
・Cu層      12・・・バリヤメタル層13・
・・In層      101・・・Si基板104・
・・AQ電極(金属膜) 代理人 弁理士  大 胡 典 夫 弓や
FIGS. 1(a) to (d) are cross-sectional views showing the method of manufacturing a semiconductor device according to the present invention in order of process, and FIG. FIG. 3 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device, and FIG. 4 is a cross-sectional view for explaining a conventional step of making bump electrode heights uniform. 1 - CCD substrate 10... Photoresist film 10a... (Photoresist film) opening 11...
・Cu layer 12...Barrier metal layer 13・
...In layer 101...Si substrate 104.
・・AQ electrode (metal film) Agent: Patent attorney Norihiro Ogo Yumiya

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上に金属膜を形成する工程と、前記金属膜
上にフォトレジスト膜を形成する工程と、前記フォトレ
ジスト膜に対し電極形成予定域に開口部を形成する工程
と、前記開口部に露出した前記金属膜上に選択メッキ法
によりCu層、バリヤメタル層、およびIn層を順次積
層させ形成するとともにこのCu層とバリヤメタル層と
で形成される積層金属層の上部を前記フォトレジスト膜
上に一部延在させて「きのこ」形になるバンプ電極を形
成する工程を含む半導体装置の製造方法。
a step of forming a metal film on a semiconductor substrate; a step of forming a photoresist film on the metal film; a step of forming an opening in the photoresist film in an area where an electrode is to be formed; and exposing in the opening. A Cu layer, a barrier metal layer, and an In layer are sequentially laminated on the metal film formed by selective plating, and the upper part of the laminated metal layer formed of the Cu layer and the barrier metal layer is placed on the photoresist film. A method for manufacturing a semiconductor device, including a step of forming a bump electrode in a "mushroom" shape by extending a portion of the bump electrode.
JP63124912A 1988-05-24 1988-05-24 Manufacture of semiconductor device Pending JPH01295445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63124912A JPH01295445A (en) 1988-05-24 1988-05-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63124912A JPH01295445A (en) 1988-05-24 1988-05-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01295445A true JPH01295445A (en) 1989-11-29

Family

ID=14897192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63124912A Pending JPH01295445A (en) 1988-05-24 1988-05-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01295445A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234841A (en) * 2006-02-28 2007-09-13 Kyocera Corp Wiring board, mounting component, electronic apparatus, manufacturing method of wiring board, and manufacturing method of electronic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234841A (en) * 2006-02-28 2007-09-13 Kyocera Corp Wiring board, mounting component, electronic apparatus, manufacturing method of wiring board, and manufacturing method of electronic apparatus

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