JPH0129455B2 - - Google Patents

Abstract

PURPOSE:To eliminate the need for a power switching by optimizing the battery saving period of a receiver according to the state of system operation and reducing the power consumption. CONSTITUTION:When a previous signal is sent out of a base station, a previous signal detector 420 outputs a detection pulse to a line 901. The pulse of the line 901 resets an FF760 to turn an AND gate 780 on and an AND gate 770 off, switching the battery saving period. Resetting to battery saving is performed by a time-out signal from a timer 600 unless a synchronizing signal is detected within said period. When the synchronizing signal is detected, reception is started.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a personal selection call receiver that employs a battery saving method to reduce battery power consumption.

Conventionally, as a battery saving method of this type, there is a method disclosed in Japanese Patent Application No. 112052/1988 entitled "Radio Individual Paging Receiver". In this battery saving method, the receiver is made to operate intermittently at a predetermined first cycle. When the receiver receives and detects a battery saving cancel signal transmitted from the base station and set to a time width longer than the first cycle, the receiver transmits the signal for a certain period of time (this time is (The time width is set to be longer than the time width of the signal string consisting of the release signal and the call code sent from the call code.) After the predetermined period of time has ended, the receiver returns to the intermittent operation of the first cycle.

In this conventional method, the first cycle of each receiver is generally set on the premise of processing during the busiest time on the system. Therefore, even in conditions such as nighttime, when the number of calls to the receiver is smaller than during the day, and therefore the base station rarely transmits useful receiver calling numbers, each receiver Since each receiver repeatedly operates intermittently in the first cycle, each receiver has the disadvantage of wasting battery power. For this reason, conventionally, an operation was performed to turn off the power to the receiver at night or the like using a power switch.

SUMMARY OF THE INVENTION An object of the present invention is to provide a personal selection call receiver that can further reduce battery power consumption.

A specific object of the present invention is to configure a system that can set a plurality of battery saving cycles, and to transmit a battery saving cycle selection signal from a base station according to the receiver call frequency to set the battery saving cycle of the receiver. An object of the present invention is to provide a small-sized personal selection call receiver that is optimized according to system operating conditions and reduces power consumption, thereby making it possible to eliminate a power switch.

According to the present invention, in a personal selection calling receiver having a battery saving function that receives radio waves modulated with a battery saving switching signal or an individual selection signal (calling number signal), the battery and the radio waves are received and demodulated. a receiving section, a signal selection circuit connected to the output of the receiving section, a pulser circuit having at least two battery saving cycles connected to an output terminal of the signal selection circuit, and a pulser circuit connected to the output of the pulser circuit and the battery. a switch means connected to another output terminal of the signal selection circuit; Upon receiving and detecting a saving cycle switching signal, the switching means outputs a detection signal to the pulser circuit to switch the battery saving cycle of the pulser circuit to a second cycle longer than the first cycle, and the switching means:
There is obtained a personal selection call receiver characterized in that the battery power, which is intermittent by the output of the pulser circuit, is supplied to at least the receiver section.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a base station of the present invention. The subscriber telephone 1 is connected via a telephone exchange 2 to a trunk 31 within the encoding device 3 . The register 33 counts the dial pulses input from the trunk 31 and converts the personal calling receiver calling number sent by the subscriber telephone 1 into a BCD (Binary).
Coded Decimal) number. Further, the call setting switch 32 allows an operator to manually input a receiver number into the register 33. The storage circuit 35 stores the BCD number from the register 33. Code converter 3
6 converts the BCD number from the storage circuit 35 into a binary number. Then, the encoding circuit 41 adds parity check bits to the output signal from the code converter 36 and outputs a cyclic code.

The pre-signal generator 37 generates a predetermined first time (9 repetition time in this example) as a pre-signal.
Or, for a second time (1025 repetition time in this example), a unique word is repeatedly generated. A synchronization signal generator 38 generates a synchronization signal following the unique word. The battery saving cycle switching signal generator 39 generates a battery saving cycle switching signal following the synchronization signal. Termination signal generator 4
0 generates a termination signal. timing circuit 34
are circuits 35, 36, 37, 38, 39, 40,
41, OR gates 42, 43 and NAND gate 4
4 and 45 individually to cause the NAND gate 46 to output the encoder output signal.

The transmitter 5 includes an FSK modulator 51, a frequency converter 52, a power amplifier 53, and an antenna 54.

Here, the operation of the base station will be explained in detail with reference to FIG.

When a regular telephone subscriber calls a personal calling receiver (described later with reference to FIG. 3; hereinafter referred to as the receiver), the calling number assigned to the receiver is dialed from the telephone subscriber's telephone 1. . The dial signal is input to the trunk 31 via the converter 2, and further input to the register 33. By manually operating the call setting switch 32, the operator can enter the call number into the register 33. When the register 33 receives a predetermined number of calls (for example, 4 calls), the register 33 stores the memory circuit 35.
, transfer all the calling numbers converted to BCD numbers. The storage circuit 35 stores the calling number until a read signal from the timing circuit 34 is received. The capacity of the memory circuit 35 is 80 calls in this example.

When the number is input to the storage circuit 35, the timing circuit 34 activates the pre-signal generator 37 and sends the pre-signal to the transmitter 5 via the OR gate 42, NAND gates 44 and 46. The transmission time of the prefix signal is 9 words (i.e. 155m _SEC x 9 = 1395m _{SEC), as shown by P in Figure 2 A and B, and each word (hereinafter referred to as a unique word) is 9 words (i.e. 155m SEC x 9 = 1395m SEC} ), and each word (hereinafter referred to as a unique word) is It consists of a 31-bit code pattern as shown by D.
The pre-signal generator 37 includes a 31-bit counter activated by the output signal of the timing circuit 34;
A unique word sending counter and a ROM (Read-Only-
Memory, for example μPD501D manufactured by NEC),
The contents of the ROM are read out using the output signal of the 31-bit counter, and the contents of the ROM are read out repeatedly the number of times set by the unique word sending counter. When the sending of the prefix signal P (9 words) is completed, the timing circuit 34 starts the synchronization signal generator 38,
The synchronization signal consisting of the code pattern shown in Fig. 2E is
It is sent at the #1 word position in Figure B. Further, the timing circuit 34 sends out a read signal to the storage circuit 35 following the completion of the synchronization signal, and at the same time,
The code converter 36, encoding circuit 41, and NAND gate 45 are operated. This time is for a maximum of 80 words (155 m _SEC x 80 = 12.4 _SEC or less) as shown in Fig. 2B. If a call number is currently stored in the memory circuit 35, the call number is transferred number by number to the code converter 36 in the order in which it was stored, by the read signal from the timing circuit 34, until the memory circuit 35 is empty. . A code converter 36 converts the BCD number to a 21-bit pure binary code. The encoding circuit 41 adds a 10-bit parity check bit to the 21-bit information code and converts it into a cyclic code.
A one-word receiver calling number (hereinafter referred to as address number) consisting of BCH (31, 21) is sent to the transmitter 5 via NAND gates 45 and 46. An example of the address number code pattern is shown in FIG. 2G.
As shown in FIG. 2B, address numbers of up to 80 words are successively transmitted in the order from word #2 to word #81. This encoding circuit 41 is a Wesley Peterson
Author “Error Correcting Codes” pp149-152,
It is composed of a circuit using a shift register and an adder disclosed by The MITPress in 1961. When the storage circuit 35 becomes empty, it sends an output signal to the timing circuit 34. timing circuit 34
In response to this signal, it stops the operation of circuits 35, 36, and 41, and at the same time activates termination signal generator 40 to generate termination signal E as shown in FIGS. 2A and 2B.
, OR gates 42, 43 and NAND gate 4
4 and 46, and then sent to the transmitter 5. The code pattern of one word of the end signal E is shown in FIG. 2H. This code pattern is a PN pattern consisting of 31 bits. The termination signal generator 40 is configured in the same manner as the pre-signal generator 37 described above, and terminates signal transmission after two words (155m _SEC x 2 = 310m _SEC ).

The timing circuit 34 starts a built-in timer when the end signal generator 40 finishes sending the signal. In this example, the timer setting time is 2 minutes.
It took 38.72 seconds (1024 words x 155m _SEC ). If there is a new number storage signal from the storage circuit 35 within this time, the timing circuit 34 repeats the series of operations described above in response to this signal. The signal train at this time is shown in FIG. 2A.

On the other hand, when the timer within timing circuit 34 times out, timing circuit 34 activates pre-signal generator 37 and activates 9, similar to P in FIG. 2B.
1, as shown in FIG.
Send word synchronization signal. Continuing further,
The timing circuit 34 activates the battery saving switching signal generator 39 to transmit a battery saving switching signal consisting of at least one word of the 31-bit pattern shown in FIG. Sends 2 words of the end signal H in the figure. timing circuit 34
does not generate any output signal unless a new number is input to the memory circuit 35.

When the storage circuit 35 receives a new number input, the timing circuit 34 activates the prefix signal generator 37 and at the same time supplies a unique word sending counter switching signal to the prefix signal generator 37 via the connection line 47. The unique word sending counter in the pre-signal generator 37 is switched from 9 to 1025, and the 1025-word unique word (second
P') in Figure c is sent. timing circuit 34
After that, stops the signal transmission for 9 words, starts the pre-signal generator 37 again, and at the same time supplies the unique word sending counter switching signal to start the unique word sending counter in the pre-signal generator 37.
1025 to 9, and the series of signal strings shown in FIG. 2B described above are sent out. The signal sequence described above is illustrated in FIG. 2c.

The transmitter 5 transmits a radio carrier wave modulated by the output signal sequence received from the encoding device 3 from the antenna 54.

FIG. 3 is a circuit diagram of the receiver of the present invention. Fourth
The operation of this receiver will be explained with reference to the time chart shown in the figure.

The modulated carrier wave sent out from the base station transmitter 5 is picked up by the antenna 100 and sent to the receiver 20.
0 and demodulates the reception and converts it to a baseband signal. This baseband signal is waveform-shaped into a rectangular wave by the waveform shaping circuit 300 and supplied to the signal selection circuit 400. Of course, the above operation is a battery saving operation in which the receiver synchronizes a battery saving OFF time of 2t and a battery saving ON time of 5t (here, t is 1 word) as shown in FIG. 4b.
Executed when in OFF time.

Now, when the receiver receives the modulated wave at the timing shown in FIG. 4a, the bit synchronization circuit 410
reproduces a clock signal bit-synchronized with the demodulated signal and passes it through line 900 to pre-signal detector 42.
0, synchronization signal detector 430, end signal detector 44
0 and address signal detector 450. The output signal of waveform shaping circuit 300 is provided to the input of pre-signal detector 420 via AND gate 486 . The other input of this AND gate 486 is connected to the output of a flip-flop (F/F) 730 within the pulser circuit 700. This F/F 730 is "H" only in the battery saving operation mode, and is "L" in the battery saving non-operation mode as will be described later. Therefore, a signal is sent to the front signal detector 420 only in the battery saving operation mode.

When the pre-signal detector 420 detects the pre-signal, it outputs the detection pulse shown in FIG. 4c onto the line 901. This detection pulse causes the pulser circuit 7
00 F/F730 is set, and this F/F7
The Q output of 30 holds switching transistor 750 ON via NOR gate 740.
On the other hand, the output of the F/F 730 becomes "L", and the AND gate 486 is inhibited. The pulse on line 901 shown in FIG. 4c also starts timer 460, and the clock signal from line 900 causes timer 460 to begin counting time. The set time (third time) of this timer 460 is 9t shown in FIG. 4b.

Now, if the synchronization signal (#1 in FIG. 4a) is not detected within this 9t time, a timeout signal is output to line 902 and resets F/F 730 via OR gate 490. As a result, F/
The Q output of F730 becomes “L” and this signal
The switching transistor 750 is turned off via the NOR gate 740 to return to the battery saving operation mode. On the other hand, F/F730
Since the output of the AND gate 48 becomes “H”,
6 is in contact state.

During the above 9t, when the synchronization signal (a#1 in FIG. 4) is detected by the synchronization signal detector 430, the line 9
03, a detection pulse is output as shown in FIG. 4d. This pulse is passed through line 903 to timer 460.
At the same time, the timer 470 is started and the timer 470 starts counting time. The set time (fourth time) of the timer 470 is 80t in FIG. 4b. The operation when the timer 470 times out is the same as that of the timer 460, and the switching transistor 750
Turn off.

Here, the circuit configurations of the pre-signal detector 420, the synchronizing signal detector 430, and the end signal detector 440 are the same, and the synchronizing signal detector 430 will be described as a representative. The synchronization signal of FIG. 2E is input to a 31-bit shift register 434. Of the 31 bits output from the shift register 434, only the bits corresponding to the "L" level of the synchronizing signal are passed through the inverters 431, 432, 433, etc., and the bits corresponding to the "H" level of the synchronizing signal are directly transmitted. It is connected to the input AND gate 435. Only when the shift register 434 takes in all 31 bits of the synchronizing signal, the AND gate 435 outputs an "H" level detection pulse (FIG. 4d) to the line 903. Pre-signal detector 420, synchronization signal detector 43
The only difference between the 0 and end signal detectors 440 is the position of the inverter provided in accordance with the "L" level of the signal patterns shown in FIG. 2D, E, and H.

Next, if the address signal of this receiver (assumed to be the one in FIG. 2 G) is sent from the base station at word #81 in FIG. 4 a, then the address signal detector 4
50, the detection pulse shown in FIG.
04 and is supplied to the alarm sound generator 500 to start it. The alarm sound generating circuit 500 operates to continuously generate an alarm output as shown in FIG. Figure 4 f
α is when the reset switch 501 is pushed,
Indicates that the alarm tone has been reset.

Here, the detailed operation of address signal detector 450 will be explained.

Synchronization signal detection pulse on line 903 (Fig. 4d)
), the read pulse generator 454 is activated. Read pulse generator 454 is connected to line 9
Read pulses synchronized with the clock signal starting from 00 are sequentially outputted to the output terminals corresponding to the bits #1 to #31 shown at 454 in FIG. 3, and this is repeated cyclically. The programmable read-only memory (PROM) 453 has the address signal assigned to the receiver written in advance, and the PROM
The shape is what is called a cord plug. Read pulse generator 454 is composed of a shift register. The data of the PROM 453 is read by the read pulse from #1 of the read pulse generator 454, and the 2-input exclusive NOR
It is supplied to one input terminal of gate 451. The input signal from the waveform shaping circuit 300 is applied to the other input terminal of the exclusive NOR gate 451, and the exclusive NOR gate 451
“H” if both inputs match, “L” if they do not match
Output. This "H" output is counted by a counter 452. Since counter 452 is being fed the clock signal from line 900, it will now receive the clock signal from #2.
PROM453 output data and waveform shaping circuit 30
0 input signal is also exclusive NOR
If the result of the comparison at the gate 451 matches, the counter 452 counts up the count, and then sequentially #31.
If all 31 bits match, a detection pulse (FIG. 4e) is output to line 904. Then, the counter 452 is reset at the falling edge of the #31 read pulse, and prepares for counting each subsequent word.

Next, with reference to the time chart of FIG. 5, a series of operations when switching the battery saving period will be described.

FIG. 5a shows a modulated carrier wave transmitted from a base station. Now, if four calling number signals from the telephone exchange 2 are not input to the encoding device 3 of the base station within the above-mentioned fixed time (1024 words), the base station will receive a 9-word (9t) prefix signal ( P) in Fig. 5a is sent from the transmitter 5, followed by a 1-word synchronization signal (1 in Fig. 5a), a 1-word battery saving switching signal (2 in Fig. 5a), and 2 words. The end signal (E in Figure 5a) is emitted from the transmitter 5, and then,
The modulated wave emission from the transmitter 5 is stopped until four calling numbers are registered in the storage circuit 35 in the encoding device 3. When four calling numbers are registered, the second
As explained in FIG. 5c, a modulated wave is emitted from the transmitter 5 as shown in FIG. 5a.

Figure 5 shows the battery saving operation of the receiver in Figure 3 corresponding to the modulated wave in Figure 5a.
Figure b. Receiving section 200 and waveform shaping circuit 300
As shown in Fig. 5b, the battery saving is turned OFF (2t) and ON (5t) by the pulser circuit 700.
is repeated. When the prefix signal P is detected by the prefix signal detector 420 while the receiving section 200 and the waveform shaping circuit 300 are in the 2t period of battery saving OFF, it is detected at time c ₁ ' in FIG. 5c. A pulse is generated. At this time, as explained with reference to FIG. 4c, the timer 460 determines that the battery saving OFF time is 9t (the third
time). Then, the synchronization signal
As explained in FIG. d, it is detected at time d ₁ ' in FIG. 5d, and the battery saving OFF time is set to 80t (fourth time) by the timer 470.
Here, the battery saving switching signal shown at 2 in FIG. 5a is detected by the switching signal detector 480, and the detection pulse shown in FIG. The pulse on line 905 is OR gate 4
85 to reset the timer 470, and
The F/F 730 is reset via the OR gate 490, and its Q output is inverted to "L". and,
The switching transistor 750 is turned off via the NOR gate 740.

Here, the detection pulse on line 905 sets a flip-flop (F/F) 760 and outputs Q,
Invert Q. The output and Q of the F/F 760 are connected to AND gates 780 and 770, respectively, and the AND gate 780 is inhibited and the gate 770 is kept connected. A control signal indicated by β ₂ in FIG. 5b is repeatedly input to the other input terminal of the AND gate 770. Further, a control signal indicated by β ₁ in FIG. 5b is repeatedly input to the other input terminal of the AND gate 780. These control signals are provided by a control signal generator 720 which divides the output of oscillator 710 and generates the required control signals β ₁ , β ₂ . The pulse that resets and initializes this control signal generator 720 is
It is obtained by inverting the output Q of F730 using an inverter 790. Therefore, the NAND gate 740 is controlled by the output signal of the AND gate 770, and the switching transistor 750 is controlled with a period of β ₂ .
is repeatedly intermittent.

Here, to explain the effect of changing the cycle of battery saving, the current consumption of the receiving section 200 and the waveform shaping section 300 is 3 mA, and the current consumption of the signal selection circuit 400 is
Since the current consumption of the pulser circuit 700 is 150μA, the average current consumption is 2t×3000+5t×150/7t≒964μA when the battery saving cycle is β ₁ , and 2t× when the battery saving cycle is _β2 . 3000+1021t×150/1023t≒155μA. Therefore, the effect of reducing current consumption is only 16%, which is extremely large compared to not switching from β ₁ to β ₂ .

Next, when the base station sends out a pre-signal having a time length of 1025t as indicated by P' in _FIG . Output to 901. The pulse on line 901 resets F/F 760 and inverts the Q output. Therefore, the AND gate 780 is switched from prohibited to closed, the AND gate 770 is switched from closed to prohibited, and the battery saving cycle is switched from β ₂ to β ₁ . The pulse on line 901 (at time c ₂ ' in Figure 5c) is
Battery saving is canceled for a time of 9t, causing an operation similar to that described at time c ₁ ′. Since no synchronization signal is detected within this time as shown, the timeout signal from timer 460 returns to battery saving mode. Pause time between prefix signals P′ and P on the base station side
9t is the 9t time when the receiver is waiting for the synchronization signal.
This is provided to avoid a situation where battery saving cannot be canceled which occurs when P following P' is sent continuously.

Next, the operation process of detecting the prefix signal P at time c ₃ ' in Figure 5 c and detecting the synchronizing signal at time d ₂ ' in Figure 5 d is the same as in Figures 4 c and d. .

Note that it is unnecessary to send the end signal E (see Figure 2 H) after the address signal when the receiver reaches the battery saving cancellation period of 80t and the address signal sent from the base station is less than 80t. The end signal detector 440 detects the pulse, and the detected pulse is passed through the OR gates 485 and 49 so as not to perform a receiving operation.
This is to reset the F/F 730 via 0 and return to battery saving mode.

In the above embodiment, the second signal is used as the prefix signal.
Although we have described the case where only the code pattern in Figure D is used, it goes without saying that the prefix signal can be replaced with a different code from the synchronization signal, battery saving switching signal, termination signal, and address signal. be.

Also, since the address number capacity is 2 ²¹ = 2097152, for example, group this by 10,000 numbers,
There are 200 groups, and the prefix signal for each group is set separately.Furthermore, in the base station, a calling number to group converter is inserted between the trunk 31 and the register 33, and the register 3 is set for each group.
3 and subsequent encoding device configuration circuits, and each group modulation signal alignment circuit is provided subsequent to the NAND gate 46 for outputting the modulation signal to the transmitter 5.
It is clear that the period in which the battery saving cycle is β ₂ can be increased. In this case, by configuring the circuit configuration of the front signal detector 420 of the receiver in the same manner as the address signal detector 450, the synchronization signal setting can be made into a code plug format, and the PROM for the synchronization signal and address number setting can be set. By accommodating them in the same cord plug, the difficulty of practical handling can be solved.

As explained above, the present invention can significantly improve the power consumption of a receiver, which is a terminal device, by configuring a system that can set multiple types of battery saving cycles, and can also eliminate the power switch of the receiver. , the device can be made smaller and its operability can be improved, and the practical effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a base station according to the present invention, FIG. 2 is a time chart for explaining the operation of the base station in FIG. 1, and FIG. 3 is a receiver according to an embodiment of the present invention. 4 is a time chart for explaining the operation of the receiver in FIG. 3, and FIG. 5 is a time chart for explaining the operation of the receiver in FIG. 3 when switching the battery saving cycle. It is a diagram. DESCRIPTION OF SYMBOLS 1... Subscriber telephone, 2... Telephone exchange, 3... Encoder, 31... Trunk, 32... Call setting switch, 33... Register, 34... Timing circuit, 3
5... Storage circuit, 36... Code converter, 37... Pre-signal generator, 38... Synchronization signal generator, 39... Battery saving switching signal generator, 40... End signal generator, 41... Encoding circuit, 5... Transmitter, 51...
FSK modulator, 52... Frequency converter, 53... Power amplifier, 54... Antenna, 100... Antenna, 20
0... Receiving section, 300... Waveform shaping circuit, 400... Signal selection circuit, 410... Bit synchronization circuit, 420...
Pre-signal detector, 430... Synchronization signal detector, 44
0... End signal detector, 450... Address signal detector, 460 and 470... Timer, 500... Alarm sound generator, 501... Switch, 600... Speaker, 700... Pulser circuit, 710... Oscillator, 7
20... Control signal generator, 750... Switching transistor.

Claims (1)

[Scope of Claims] 1. A personal selection call receiver having a battery saving function that receives radio waves modulated with a battery saving switching signal or an individual selection signal, comprising: a battery; a receiving unit that receives and demodulates the radio waves; a signal selection circuit connected to the receiver output; a pulser circuit having at least two battery saving cycles connected to the output terminal of the signal selection circuit; and a switch means connected to the pulser circuit output and the battery. , a call notification means connected to another output terminal of the signal selection circuit, and the signal selection circuit receives a battery saving cycle switching signal when the pulser circuit is operating in a first battery saving cycle. When a detection signal is received and detected, the switching means outputs a detection signal to the pulser circuit to switch the battery saving cycle of the pulser circuit to a second cycle longer than the first cycle, and the switching means A personal selection call receiver, characterized in that power is supplied to at least the receiving section. 2. In a personal selection calling receiver with a battery saving function that receives radio waves modulated with a serial signal of a prefix signal and a battery saving switching signal or an individual selection signal, a battery and a receiving section that receives and demodulates the radio waves are provided. , a signal selection circuit connected to the receiver output, and a first signal selection circuit of the signal selection circuit.
and a pulser circuit having at least two battery saving cycles connected to a second output terminal, a switch means connected to the output of the pulser circuit and the battery, and a third pulser circuit of the signal selection circuit.
and a call notification means connected to the output terminal of the
The signal selection circuit, when the pulser circuit is operating in a first battery saving cycle,
When the serial signal of the prefix signal and the battery saving switching signal is received and detected, the prefix signal detection signal is outputted to the first output terminal, the battery saving switching signal detection signal is outputted to the second output terminal, and the pulser circuit is activated. The battery saving operation is switched to a second period which is longer than the first period, and further, the signal selection circuit is configured to switch between the prefix signal and the individual selection signal when the pulser circuit is operating in the second battery saving period. When a serial signal is received and detected, a pre-signal detection signal is output to the first output terminal, the battery saving cycle of the pulser circuit is switched from the second cycle to the first cycle, and the individual selection signal detection signal is switched to the first output terminal. 3, to operate the call notification means, and the switch means supplies the battery power interrupted by the output of the pulser circuit to at least the receiving section. Machine.