JPH0129425B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase difference detection circuit for alternating current voltage and current for controlling the power factor of electric power systems and the like.

A conventional AC voltage/current phase difference detection circuit is configured as follows. That is, when the voltage and current to be detected are, for example, in phase, a circuit is configured in advance to guide the voltage and current as shown in Figure 1A, and the rise and fall of the voltage V and current I obtained as the output of this circuit is is captured and input to the flip-flop circuit. If the logic outputs for voltage V and current I of this flip-flop circuit are as shown in FIG. 1B, for example, based on these logic outputs, it is converted into an ON-OFF signal as shown in FIG. 1C, and the second The signal is input to an amplifier circuit having a filter configuration as shown in the figure. In the circuit shown in FIG. 2, a predetermined bias is applied to the ON-OFF signal, and the signal is averaged by a filter capacitor C to obtain a DC voltage as an output voltage. In addition, in Figure 2, R
(1) to R(3) are resistors, and VR is a potentiometer for bias setting. Therefore, the phase difference of the AC voltage and current to be detected can be detected from the level of the DC voltage described above. The characteristics of the phase angle α and the DC output voltage in this case are shown in FIG.

However, the ON-OFF shown in Figure 1C
To average the signal to a DC voltage, for example, the second
It is necessary to increase the capacitance of the filter capacitor C shown in the figure.

Therefore, a time delay occurs in detecting the phase difference between AC voltage and current. There is no problem when used for simple measurements where detection delay can be ignored, but when used for power factor control in electric power systems, etc., it is difficult to respond quickly to various power supply fluctuations and load fluctuations. There were some problems, such as not being able to do it.

The present invention has been made in view of the above points, and is capable of detecting the amount of phase lead and lag with a simple circuit configuration, as well as speeding up the detection. The purpose of the present invention is to provide a phase difference detection circuit for alternating current voltage and current that enables operation. In order to achieve this object, the present invention includes means for detecting each zero-point passing point of voltage and current to generate a predetermined logic condition, and information about the time difference between zero-point passages based on the logic condition output from the means. A pair of sample and hold means on the leading phase side including an integrator or the like whose output state periodically changes with a phase difference of half a cycle from each other, and another pair of sample and hold means having a similar configuration to the sample and hold means. , a means is provided for averaging and synthesizing the added outputs of each pair of sample and hold means in a DC manner, and detecting a phase difference between AC voltages and currents from a DC voltage level proportional to the time difference obtained as an output of the synthesizing means. It is characterized by

Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 4 is a circuit diagram showing an embodiment of the AC voltage and current phase difference detection circuit according to the present invention. In the figure, reference numeral 10 denotes a detection data calculation circuit that detects each zero point passing point of voltage and current and generates a predetermined logic condition. In this detection data calculation circuit 10, CP ₁ and CP ₂ are comparators that detect the point in time when the voltage V and current I pass through the zero point, respectively.

NOT ₁ ~ _{NOT 4} are polarity inverters, NAND ₁ ~
NAND ₄ is a NAND gate. 20I samples information about the time difference between each zero point passage of voltage and current based on the logical condition output from the detection data calculation circuit 10, and outputs a first signal whose output state changes periodically based on this sampled information. This is a sample and hold circuit. Further, 20 is a second sample and hold circuit whose output state changes periodically with a phase difference of half a cycle with respect to the first sample and hold circuit 20. These circuits 20,
20 samples leading phase data. Similarly, data with a delayed phase is sampled by the third and fourth sample-and-hold circuits 20 and 20 whose output states periodically change with a phase difference of half a cycle. These sample and hold circuits 20
, 20, AS ₁₁ , AS ₂₁ , AS ₃₁ , AS ₄₁
are analog switches such as N-channel FETs, and VR ₁₁ , VR ₂₁ , VR ₃₁ and VR ₄₁ are potentiometers. 22, 22, 22, 22
is an integrator, A ₁₁ , A ₂₁ , A ₃₁ , A ₄₁ are operational amplifiers,
R ₁₁ , R ₂₁ , R ₃₁ , R ₄₁ are input resistances C ₁₁ , C ₂₁ , C ₃₁ ,
C ₄₁ is an integrating capacitor, RS ₁₁ , RS ₂₁ , RS ₃₁ , RS ₄₁
is, for example, an analog switch such as an N-channel FET. 24, 24 and 24, 24 are amplifiers that amplify the input corresponding to the phase difference, respectively, and R ₁₂ , R ₂₂ , R ₃₂ , R ₄₂ are input resistors R ₁₃ , R ₂₃ ,
R ₃₃ and R ₄₃ are feedback resistances, D ₁₁ and D ₁₂ ;
_D21 , _D22 ; _D31 , _D32 ; _D41 , _D42 are diodes. 30 is a sample hold circuit 20, 20
This is an amplifier circuit that averages and synthesizes the summed outputs of 20 and 20 in a direct current manner.

In this amplifier circuit 30, R〓, R〓 are input resistors, _R51 is a feedback resistor, and _A51 is an operational amplifier.

One embodiment of the present invention is configured as described above, and its operation will be described next.

Assume that an AC voltage is input to the comparator CP ₁ and an AC current is input to the comparator CP ₂ . As shown in FIG. 5A, the comparators CP ₁ and CP ₂ are constructed so that both the voltage and current are positive and the output is "0". The operations of the sample and hold circuits 20, 20 and 20, 20 when these voltages and currents are viewed from the logic outputs of the polarity inverters NOT ₁ and NOT ₃ (see FIG. 5B) are shown in FIGS. 5E and F, respectively. Shown below.

In addition, Figure 5C shows the logic output of NOT ₂ , and Figure 5D shows the logic output of NOT 2.
indicate the logic output of NOT ₄ , respectively. This fifth
FIGS. 6A to 6I illustrate the state transitions shown in the figures to make it easier to understand. Note that the signal V in FIG. 6B for the voltage and current waveform in FIG. 6A,
I indicates the output signals of the polarity inverters NOT ₁ and NOT ₃ , respectively.

This will be explained below with reference to the logic table shown in FIG. 5E.

First, as shown in Figure 6A, if the polarity of voltage V is positive and the polarity of current I is negative, then the corresponding
The logic levels of NOT ₁ and NOT ₃ are "1" and "0", respectively. Therefore, the logic level of the output of the NAND gate NAND ₁ is "0", and a logic "0" signal is applied to the gate of the analog switch AS ₁₁ of the sample and hold circuit 20. By this,
Analog switch AS ₁₁ becomes conductive and enters the sample state.

At this time, the logic level of the NAND gate NAND ₄ is "1" and a logic "0" signal is input to the gate of the analog switch AS ₂₁ of the sample and hold circuit 20, so the analog switch AS ₂₁ is not conductive and the data is not processed. No samples are taken. In this case, the sample-and-hold circuit 20 is in a state in which sampled data is held, as will be understood from the transition of operating states described later.

As mentioned above, the sample and hold circuit 20
Since the analog switch AS ₁₁ becomes conductive, a predetermined voltage based on the setting of the potentiometer VR ₁₁ is input to the integrator 22 .

In this case, the logic level of the output of NAND ₂ which provides the gate signal of analog switch RS ₁ is "1", but when analog switch RS ₁ is connected to N channel
Since it is a FET, it is not conductive, and a predetermined integral operation based on the time constant C ₁₁ R ₁₁ is performed. As a result, a negative integral output generated at the output terminal of the integrator 22 is input to the amplifier 24. In this case, since the integral output is of negative polarity, the diode D ₁₁ is non-conductive and a positive voltage proportional to the integrator output voltage R ₁₃ /R ₁₂ is obtained as the output of the amplifier 24.

The output of the amplifier 24 obtained in this way,
That is, the output of the sample and hold circuit 20 has a waveform that increases with the integration time as shown in FIG. 6C.

Next, the case where the polarity of the voltage V is positive and the polarity of the current I is also positive as shown in FIG. 6A will be described. In this case, the corresponding logic levels of NOT ₁ and NOT ₃ are "1" and "1", respectively. Therefore, the logic level of NAND gate NAND ₁ is "1", and the analog switch of sample hold circuit 20
A logic level "1" is applied to the gate of AS ₁ .

Therefore, analog switch AS ₁ does not conduct.
At this time, the logic level of NAND ₂ becomes "1",
Applied to the gate of analog switch RS ₁ ,
As mentioned above, since it is an N-channel FET, it does not conduct. Therefore, the output state of the integrator 22 is held at a constant negative voltage. This negative constant voltage is input to the amplifier 24, and a positive hold voltage as shown in FIG. 6C is obtained as an output.

On the other hand, the logic level of the NAND gate NAND ₄ is "1", and this signal "1" is applied to the gate of the analog switch AS ₂₁ of the sample and hold circuit 20. This signal "1" does not cause the analog switch AS ₂₁ to conduct. At this time, the NAND gate NAND ₃ is at the logic level "0", but as mentioned above, since the analog switch RS ₁₁ is an N-channel FET, it conducts and the charge accumulated in the integrating capacitor C ₂₁ is discharged, as shown in Figure 6. It becomes a reset state as shown in D.

Next, a case where the voltage is negative and the current is positive will be explained. In this case, the logic levels of NOT ₁ and NOT ³ are "0" and "1", respectively. Based on the same logical operation, the analog switch AS ₁ of the sample-and-hold circuit 20 becomes non-conductive, and the analog switch RS ₁ also becomes non-conductive, so the output of the sample-and-hold circuit 20 continues to be held as shown in FIG. 6C. do.

On the other hand, at this time, the analog switch AS ₂₁ of the sample-and-hold circuit 20 is conductive, and the analog switch RS ₂₁ is non-conductive, so the integrator 22 performs an integration operation based on the time constant C ₂₁ R ₂₁ and The output shown in FIG. 6D is obtained.

Next, both the voltage and current become negative, and the state becomes NOT ₁ .
The logic level of NOT ₃ is both "0". In this case as well, based on the same logical operation, the analog switch AS ₁₁ of the sample and hold circuit 20 is non-conductive;
The analog switch _RS11 becomes conductive, the charge accumulated in the integrating capacitor _C11 is discharged, and the output of the sample and hold circuit 20 becomes a reset state as shown in FIG. 6C.

On the other hand, at this time, the analog switch AS ₂₁ of the sample and hold circuit 20 is non-conductive, and the analog switch RS ₂₁ is also non-conductive, so that the output state of the integrator 22 is held as shown in FIG. 6D.

Hereinafter, each sample hold circuit 20
, 20 will periodically transition between a sample state, a hold state, and a reset state, as shown in FIGS. 6C and 6D.

The outputs O ₁ and O ₂ of the sample-and-hold circuits 20 and 20 obtained in this way have positive polarity, with priority given to the high level side, and the added DC voltage value O ⁽⁺⁾ as shown in FIG. 6E. ₀₁ is input to the synthesis circuit 30 at the subsequent stage.

The above description of the operation has been about the pair of sample-and-hold circuits 20, 20 on the leading phase side, but the same applies to the other pair of sample-and-hold circuits 20, 20 on the lagging phase side. In this case, the output state of the sample and hold circuit 20 is the sixth
As shown in FIG. F, the output state of the sample-and-hold circuit 20 changes periodically with a phase difference of half a cycle, as shown in FIG. 6G.

The outputs O ₃ and O ₄ of the sample and hold circuits 20 and 20 obtained in this way are given priority to the low level side in negative polarity, and the added DC voltage value O ^(-) as shown in FIG. ₀₂ is input to the synthesis circuit 30 at the subsequent stage.

Therefore, in the synthesis circuit 30, each of these outputs
A DC voltage at a predetermined level is obtained as an inverted output of the combined value of O ⁽⁺⁾ ₀₁ and O ^(-) ₀₂ . The phase difference between AC voltage and current can be determined from this DC level. The relationship between DC voltage and phase in this case is shown in the characteristic diagram of FIG. As can be understood from this characteristic diagram, when the voltage and current to be detected are in the same phase and the phase difference of the same amount of electricity is zero as in this embodiment, each of the outputs described above O ⁽⁺⁾ _01
The ^{difference between} _{_} ^_ _{_} If , O ⁽⁺⁾ ₀₁ increases,
The characteristic is that O ^(-) ₀₂ decreases.

In the above embodiment, an N-channel FET is used as the analog switch, but any type of FET or other analog switch can be used by changing the logic operation of the detected data calculation circuit.

As described above, the present invention makes it possible to detect the advance of the phase difference of voltage and current, including the advance and lag of the phase difference, without requiring a filter as in the conventional case, and to speed up the response without causing a delay in the detection. This can be achieved with a simple circuit configuration. Therefore, it has an excellent feature that it can contribute to stable system operation by applying it to control such as power factor adjustment of an electric power system.

[Brief explanation of drawings]

FIG. 1A is a waveform diagram showing the relationship between voltage and current to explain conventional phase difference detection of AC voltage and current;
Figure 1B is a table showing the logic states corresponding to the voltage and current in Figure 1A, Figure 1C is a waveform diagram showing pulses based on the logic states in Figure 1B, and Figure 2 is the diagram shown in Figure 1. A circuit diagram showing a filter into which the pulse waveform of C is input,
3 is a characteristic diagram showing changes in phase with respect to the voltage obtained as the filter output in FIG. 2; FIG. 4 is a circuit diagram showing an embodiment of the AC voltage and current phase difference detection circuit according to the present invention; Figures A to 5F are the fourth
A table diagram explaining the logical operation of the phase difference detection circuit shown in the figure,
Figure 6 is a time chart showing the operating waveforms of each part of the phase difference detection circuit in Figure 4, and Figure 7 is a characteristic diagram showing the relationship between the DC voltage and phase obtained as the output of the phase difference detection circuit in Figure 4. be. 10...detection data calculation circuit, 20...first
sample hold circuit, 20... second sample hold circuit, 20... third sample hold circuit, 20... fourth sample hold circuit, 22, 22, 22, 22... integrator, 30... Synthesis circuit, AS ₁₁ , AS ₂₁ , AS ₃₁ ,
AS ₄₁ ; RS ₁₁ , RS ₂₁ , RS ₃₁ , RS ₄₁ ... Analog switch, C ₁₁ , C ₂₁ , C ₃₁ , C ₄₁ ... Integrating capacitor.

Claims (1)

[Claims] 1. A circuit for detecting the phase difference of alternating current voltage and current in order to perform power factor control, etc., which includes means for detecting each zero point passing point of voltage and current to generate a predetermined logic condition; Based on the logic condition output from the means, information about the time difference between each zero point passage of the voltage and current is sampled, and the output state based on this sampled information changes periodically with a phase difference of half a cycle from each other, and when the polarity is positive, logic condition outputs from the first and second sample and hold means for sampling advanced phase data with priority given to the high level side, and the means for detecting each zero point passing point of the voltage and current to generate a predetermined logic condition; Based on this, information about the time difference between each zero point passage of the voltage and current is sampled, and the outputs of the first and second sample and hold means are periodically transitioned with a phase difference of half a cycle, and a low level is generated at negative polarity. The third and fourth sample and hold means for sampling the data of the delayed phase that is prioritized by the side, and the added values of the first and second sample and hold means and the third and fourth sample and hold means are DC averaged. The output state of each sample hold means is configured to periodically transition between a sample state, a hold state, and a reset state, and the output state of each sample hold means is proportional to the time difference obtained as an output of the synthesis means. A phase difference detection circuit for AC voltage and current, which detects a phase difference between AC voltage and current from a DC voltage level. 2. The AC voltage and current phase difference detection circuit according to claim 1, wherein each of the sample and hold means includes an integrator that integrates a value corresponding to a time difference between voltage and current.