JPH01292969A - Vertical driving pulse generating circuit - Google Patents

Abstract

PURPOSE:To improve a noise proof characteristic by providing an intrinsic window (gate period) against a vertical synchronizing signal of first and second broadcasting system whose vertical periods are different. CONSTITUTION:A first intrinsic data period is provided against a vertical synchronizing signal of the first and the second broadcasting systems, respectively, and when the vertical synchronizing signal exists in this first gate period, it is switched to a second gate period being narrower than a first gate period. For instance, when it is confirmed that the vertical synchronizing signal has arrived in a period of about 262.5H in a first gate period (224H-296H) of a gate circuit 9, the gate period of the gate circuit 9 is switched to a second gate period (260.5H-264H), and a counter 10 is brought to self-reset in a period of 262.5H. Accordingly, a gate open period of the gate circuit 9 can be nallowed. thus, the noise proof characteristic can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a vertical drive pulse generation circuit for a TV (television) receiver. , relates to a vertical drive pulse generation circuit with improved noise resistance.

(b) Conventional technology An automatic TV broadcast system discrimination device that has a function of opening a gate (window) and taking in vertical synchronization signals of two different broadcast systems (for example, NTSC system and PAL system) during the expected arrival period. However, it has been filed as Japanese Patent Application No. 58-68916 by the same applicant as the present application. 9th
The figure is a circuit diagram showing the gate circuit in the automatic discrimination device for the television broadcasting system, which includes a counter (2) that divides the frequency of the horizontal synchronization signal from the terminal (1), and a vertical synchronization signal from the input terminal (3). and a gate circuit (4) for passing the gate in response to a gate control signal from the counter (2);
A pulse generation circuit (
5).

After the counter (2) is reset, it counts the horizontal synchronization signal from the terminal (1).Then, the gate circuit (4) is cut off until the period when the vertical synchronization signal is expected to arrive. This helps prevent noise etc. from the input terminal (3) from affecting the subsequent circuit.And when the expected count number of NTSC and PAL vertical synchronization signals arrives: n=240, Generates a gate control signal that makes the gate circuit (4) conductive.In this state, if a regular vertical synchronization signal has arrived, n=2.
62.5 for NTSC, and n=312.5 for PAL
The vertical synchronizing signal of the system passes through the gate circuit (4) and is applied to the pulse generating circuit (5).
A reset pulse corresponding to the vertical synchronization signal is generated at the output end of the counter (2) to reset the counter (2). Then, in response to the reset, a vertical drive pulse is generated at the output terminal (6) of the counter (2) and is supplied to a deflection circuit (not shown). After the counter (2) is reset, it counts again and repeats the same operation as described above.

Note that when no vertical synchronization signal is applied to the input terminal (3), a pulse is generated from the counter (2) at n=340, and the pulse is generated from the counter (2) via the pulse generation circuit (5).
2) is applied. Therefore, in this state, the counter (2) is in a self-resetting state (a state in which the television screen is flowing vertically).

Therefore, according to the circuit shown in FIG. 9, by providing a window that allows the vertical synchronization signal to pass only during a specific period, it is possible to prevent malfunctions of the downstream circuit due to noise contained in the video signal.

(c) Problems to be solved by the invention By the way, since the gate circuit (4) in FIG. 9 can be used in both the NTSC system and the PAL system,
The conduction start timing is set to n-240. The reason for n=240 is that the vertical synchronization signal of the NTSC system normally arrives at n=262.5. However, when receiving a PAL vertical synchronization signal, the arrival of the vertical synchronization signal is usually n=312.5, so if the gate circuit (4) is opened from n=240, the noise resistance will be reduced. The problem was that it got worse.

That is, if noise is mixed into the PAL vertical synchronization signal and the noise is present at a position earlier than the generation timing of the vertical synchronization signal, the noise passes through the gate circuit (4) and the counter (2 ) could malfunction.

(d) Means for Solving the Problems The present invention has been achieved in view of the above points, and includes a gate circuit that passes a vertical synchronization signal applied to an input terminal in accordance with a control signal, and a A wide gate signal corresponding to a wide period during which the vertical synchronization signal is expected to arrive is reset by a signal corresponding to a passing vertical synchronization signal, and counts signals having a frequency that is an integral multiple of the horizontal synchronization signal frequency. a counter that generates a gate signal with a narrow width corresponding to a narrow period in which the vertical synchronization signal is expected to arrive;
a phase comparison circuit that performs a phase comparison between a frequency-divided output signal having a period equal to the vertical synchronization signal generated from the counter and the vertical synchronization signal from the gate circuit; and a gate signal selection circuit that applies wide-width and narrow-width gate signals as control signals to the gate circuit.

(f) Effect According to the present invention, a unique first gate period is provided for the vertical synchronization signals of the first and second broadcasting systems, and when the vertical synchronization signal exists within the first gate period, The switching is made to a second gate period which is narrower than the first gate period. Therefore, the influence of noise mixed into the signals of each broadcast system can be significantly reduced.

Further, according to the present invention, when the second gate period is set, the counter is self-reset at the regular vertical period of each broadcasting system, so that the vertical drive pulse with a stable period is transmitted from the counter. You can get it.

(f) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which (7) is an input terminal to which NTSC and PAL video signals are applied, and (8) is the input terminal (7). ), (9) is a gate circuit that passes the vertical synchronization signal from the synchronization separation circuit (8) according to a control signal, and (10) is a clock terminal. (
(12) is the gate circuit (9) that counts the clock signal of frequency 2 rH (fH is the horizontal synchronization signal frequency) from the 11) and generates the first to fifteenth output signals (≠□ to φIs). an input selection circuit that switches and outputs the vertical synchronization signal from the oscilloscope and the first, second, third, and fifth push-in force signals φ1, 4hφ, and φ generated from the counter (10) according to a plurality of control signals; , (13) is a reset pulse generation circuit that generates a set pulse having a predetermined pulse width according to the output signal of the input selection circuit (12);
4) is an output terminal at which an output signal (vertical drive pulse) at the HJ level is generated for a period of 8H (H is one period of the horizontal synchronization signal) after the cariter (10) is reset in response to the reset pulse; 15) starts its operation in response to the sixth output signal φ6 from the counter (10), compares the phase of the reset pulse with the seventh output signal -7 from the counter (10), and compares the phase of the reset pulse with the seventh output signal -7 from the counter (10). Determine whether the vertical synchronization signal is 50Hz or 60Hz5 0
/60 discrimination circuit, (16> is the 3rd, 5th, 6th, 7th and 14th output signals (φ,
,φ,.

φ,,φ? +'16+4), reset pulse, 50/6
The counter (1
0) is synchronized with an external signal. (17) is a synchronization detection circuit that detects whether or not the counter (10) is synchronized with a signal from the outside.
~≠7. ) according to a plurality of control signals and applies the output to the gate circuit (9), (18)
are the first and second output signals φ1 and 4. generated from the counter (10). A first signal selection circuit (19) switches and outputs the output signal of the first signal selection circuit (18) according to the discrimination output of the 50/60 discrimination circuit (15), and a clock signal from the clock terminal (11) The delay circuit (20) delays the output signal of the gate circuit (9) according to the counter (
A holding circuit (21) holds the reset pulse and the output signal of the delay circuit (19) or the output signal of the holding circuit (20) and the counter ( 10) The fourth output signal φ4 generated from
a second signal selection circuit that selectively switches and outputs (
22) is a phase comparison circuit that compares the phases of the two output signals of the second signal selection circuit (21).

The counter (10) is composed of a 10-stage T-FF (T-type flip-flop circuit) and a decoder circuit, and the T-FF divides the 2f9 clock signal applied from the clock terminal (11). It decodes and outputs the frequency-divided output. Then, the first output signal φ, after 261.5H after the counter (10) starts counting, the second output signal φ2, after 311.5H, the third output signal 4.
is after 296H, the fourth output signal φ, is between 2H and 4H, and the fifth output signal φ6 is after 356H, the sixth output signal 4.
is after 224H, the 7th output signal≠, is after 288H, the 8th output signal φ is 26Q, between 5H and 264H, the 9th output signal is
The output signal φ is the 10th signal between 310.5H and 314H.
Output signal φ1. is between 224H and 296H, the 11th output signal≠, l is between 268H and 356H, the 12th output signal 6° is between 224H and 356H, the 13th output signal φl is after 8H, the 14th output signal is 1 After .5H, the fifteenth output signal φ, 6 is a signal generated between 8H and 17H.

Now, in the case of the NTSC system, the period of the vertical synchronization signal from the broadcasting station is 262.5H, and in the case of the PAL system, the period is 3H.
It is 12.5H. Therefore, in the present invention, NTSC
The first wide gate period of the method is taken before and after 224H.
to 296H, and the second narrow gate period is 260H.
．． It is set between 5H and 264H. Further, the first wide gate period of the PAL power type is set before and after that, and is set between 268H and 356H, and the second narrow gate period is set at 310.
It is set between 5H and 314H.

Further, the timing (discrimination limit point) serving as a reference for discrimination between the NTSC system and the PAL system is set to 288H.

Next, the operation will be explained. In the circuit shown in Figure 1, when there is no signal, no video signal is applied to the input terminal (7>), so
The counter (10) is not reset by an external signal, but sequentially counts the clock signal from the clock terminal (11). When the count reaches 356H, a fifth output signal -6 is generated from the counter (10) and applied to the synchronization detection circuit (16).

Then, the synchronization detection circuit (16) is a counter (10).
It generates an output signal of level "rL" indicating that the gate signal is out of synchronization, switches the first switch (23) in the gate signal selection circuit (17) to the contact side, and switches the first switch (23) in the input selection circuit (12) to the contact side. Connect the second switch (24) to contact a.
switch to the side. Therefore, the fifth output signal i from the counter (10) is transmitted to the first OR gate (25) and the second switch (
24) is applied to the reset pulse generation circuit (13) via the third switch (26), and a corresponding reset pulse is applied to the counter (10).

(It is assumed that the third switch (26) is switched to the contact a side.) The reset pulse has a short pulse width according to the 2f'N clock signal from the clock terminal (11). (One period of clock signal of 2f, t)
Therefore, after resetting, the counter (10) is
Resume counting immediately. And again the counter (10)
A fifth output signal φ is generated, and the same operation as described above is repeated.

At this time, since no external signal is applied to the counter (10), the counter (10) is in a self-resetting operation, and the output terminal (10) is self-resetting.
4), a vertical drive pulse with a period of 356H is generated. In the present invention, the counter (10) is 296H or 3
The state in which 56H is self-resetting is called out-of-synchronization.

On the other hand, the first switch (
23) switches to the contact side, the twelfth output signal φ1. is the first switch (2
3) to the gate circuit (9). For that reason,
The gate circuit (9) has a wide gate period of 224H to 356H.

In this state, if an NTSC or PAL video signal is applied to the input terminal (7), the vertical synchronization signal in the video signal is separated by the synchronization separation circuit (8) and passes through the gate circuit (9). is applied to the input selection circuit (12). Here, the second switch (24) in the input selection circuit (12) responds to the switching control signal from the synchronization detection circuit (16) regardless of the switching control signal from the 50/60 discrimination circuit (15). The state shown in the figure (contact a side) is maintained because it is switched preferentially. Therefore, the vertical synchronization signal from the gate circuit (9) is sent to the first OR gate (25).
It passes through the third switch (26) and is applied to the reset pulse generation circuit (13). Then, a reset pulse corresponding to the vertical synchronization signal is generated by the reset pulse generation circuit (
13) to the 50/60 discrimination circuit (15) and the synchronization detection circuit (16).

By the way, the 50/60 discrimination circuit (15) has a counter (1
It becomes possible to take in a reset pulse in response to the sixth output signal φ from 0), and the reset pulse is compared in phase with the seventh output signal -7, and the output of the phase comparison result is set to a predetermined value (e.g. After counting up to 4 times), a determination output is generated. In addition, the synchronization detection circuit (16) receives 60Hz from the 50/60 discrimination circuit (15).
When an output signal of level rH, indicating that It generates an "H" level output signal indicating that. If the reset pulse does not arrive, an output signal of rL'' level indicating that the synchronization is out of synchronization is generated in response to the arrival of the third output signal ≠. Furthermore, the synchronization detection circuit (16)
When the "L" level output signal indicating 50Hz is applied from the /60 discrimination circuit (15), in response to the arrival of the seventh output signal φ, it becomes possible to take in the reset pulse from then on, and the reset is performed. When the pulse is counted a predetermined number of times by the counter, rH indicates a synchronized state.

Generates a level output signal. Further, when the reset pulse does not arrive, the fifth output signal 4. r L indicating that the synchronization is out of synchronization in response to the arrival of r L .

It is configured to generate a level output signal.

Here, if we are currently receiving an NTSC vertical synchronization signal, the phase comparison between the reset pulse corresponding to the vertical synchronization signal and the seventh output signal -1 is determined by the 50/60 discrimination circuit (
15), but since the phase of the reset pulse is earlier than the phase of the seventh output signal≠, when the phase comparison is performed a predetermined number of times, the 50/60 discriminator circuit (15) determines that r H
, the fourth and fifth switches (
27) and (28) are switched to the contact a side. Also, the rH
, the sixth switch (29) is switched to the contact a side according to the output signal of the level. Further, the synchronization detection circuit (16) takes in a reset pulse in accordance with the rH, level output signal of the 50/60 discriminator circuit (15), and when counted a predetermined number of times, generates an rH, level output signal. 2
The switch (24) is switched to the contact side.

A reset pulse from the reset pulse generation circuit (13) is applied to the second signal selection circuit (21).

Further, the first signal selection circuit (18) selects the first output signal φ1 in accordance with the discrimination output of the 50/60 discrimination circuit (15), so that the first output signal φ□ is detected by the delay circuit (19). The signal is delayed by a predetermined amount and applied to the second signal selection circuit (21). (The delay amount of the delay circuit (19) is the first output signal 4
．． The period is set to approximately 262.5H. )
Then, the first output signal -8 and the reset pulse are applied to a phase comparator circuit (22), and their phases are compared. Here, if the period of the vertical synchronization signal being received is slightly deviated from 262.5H due to the influence of a weak electric field, etc., the phase comparator circuit (22) outputs an output signal of rH and level indicating a phase mismatch. occurs. Then, the seventh switch (30) is switched to the contact side in accordance with the output signal of the rH level, so that the tenth output signal φ, generated from the counter (10). are the fifth switch (28) and the seventh switch (3
0), and the gate circuit (
9).

Therefore, the gate opening period of the gate circuit (9) is set to 224H.
It is possible to set an appropriate value for the vertical synchronization signal of the NTSC system, which is between 296H and 296H.

Furthermore, since the third switch (26) maintains the state of the contact a side according to the rH level output signal of the phase comparator circuit (22), the gate is closed regardless of the state of the second switch (24). The vertical synchronization signal passed through the circuit (9) is applied to the reset pulse generation circuit (13). Then, the counter (10) is reset in accordance with the reset pulse synchronized with it, so the carantuff 10) becomes synchronized with the vertical synchronization signal from the outside, and the vertical drive pulse synchronized with it is sent to the output terminal (14). can get.

If the next received vertical synchronization signal has a period of exactly 262.5H, the phase comparator circuit (22) generates an "L" level output signal indicating phase matching. Then,
Since the seventh switch (30) is switched to the contact a side in response to the output signal of the r L '' level, the eighth output signal 4. is generated from the counter (10). is applied to the gate circuit (9).

Therefore, the gate opening period of the gate circuit (9) is set to 260.
It can be made very narrow between 5H and 264H, and the noise resistance can be greatly improved.

On the other hand, the third switch (26) is switched to the contacting side in response to the rL'' level output signal of the phase comparison circuit (22). Therefore, the first output signal φ1 is sent to the sixth switch (29).
and is applied to the reset pulse generation circuit (13) via the third switch (26). Then, the output terminal of the reset pulse generation circuit (13) is synchronized with the clock pulse,
A reset pulse that falls at 262.5H is generated to reset the counter (10).

Then, after the reset is released and the count progresses, the first output signal φ is generated again, and the same operation is repeated.

Therefore, the counter (10) performs a self-resetting operation at 262.5H by itself, regardless of the external vertical synchronization signal. Therefore, a vertical drive pulse with a period of 262.5H is generated at the output terminal (14>) of the counter (10).

In this state, even if the external vertical synchronizing signal fluctuates due to channel switching, the counter (10) cannot synchronize with it.

Therefore, in the present invention, even in this state, the phase comparison circuit (2
2) is observed.

Its operation will be explained. The phase comparator circuit (22)
When an output signal of level L is generated, the second signal selection circuit (21) accordingly selects the output signal of the holding circuit 20> and the fourth output signal φ4 generated from the counter (10).
and both signals are passed through the phase comparator circuit (22
), the phase is compared. Here, when the output signal of the phase comparator circuit (22) is at the r L '' level, the counter (10
) maintains the above state. Also, the output signal is “H”
When flipped to the level, the third switch (26
) is switched to the contact a side, the self-resetting operation of the counter (10) is stopped, and the counter (10) is again synchronized with the external vertical synchronization signal. In addition, the first switch (23) is switched to the contact side in accordance with the rH, level output signal, so the gate period of the gate circuit (9) becomes 2 again.
It will be between 24H and 296H.

That is, in the present invention, the first gate period (224H
When it is confirmed that the vertical synchronization signal arrives at approximately 262.5H period within 296H), the gate period is switched to the second gate period (260,5H to 264H), and the counter (10) is set to 262.5H. It resets itself periodically. By doing so, the noise resistance of the counter (10) is improved, and the stability against instantaneous loss of the incoming vertical synchronization signal is increased.

The above explanation was about the NTSC system, but P
In the case of the AL method, they are basically the same except for the value of the output signal of the counter (10). For example, when an "L" level output signal indicating 50Hz is generated from the 50/60 discrimination circuit (15), the fourth and fifth switches (
27) and (28) are switched to the contact side, so the gate period of the gate circuit (9>) corresponds to the values of the 9th and 11th output signals φ and φ, I generated from the counter (10). In addition, the first signal selection circuit (18) selects the counter (1) according to the output signal of the 50/60 discrimination circuit (15).
The second output signal generated from 0) is selected. When the second output signal φ is applied to the count set pulse generation circuit (13), the counter (10)
is self-reset at a period of 312.5H, which is the period of the PAL system.

Next, a case will be described in which the reception is switched from NTSC broadcasting to PAL broadcasting. Since the gate period of the gate circuit (9) immediately after switching corresponds to the NTSC system, the vertical synchronization signal of the PAL system cannot pass through the gate circuit (9). Therefore, the counter (10) enters a self-resetting state in response to the third output signal φ generated from the counter (10). Then, when the third output signal ≠ is applied to the synchronization detection circuit M (16), an output signal of level r L indicating out of synchronization is generated, and the first switch (23) is brought into contact. switch to the side. Therefore, the first
2- Output signal -1, is applied to the gate circuit (9).

Therefore, the vertical synchronizing signal of the PAL system is immediately passed through, and the counter (10) generates a vertical drive pulse synchronized with it at the output terminal (14>).

Next, the specific circuit example shown in FIG. 1 will be explained. FIG. 2 is a circuit diagram showing a specific circuit example of the input selection circuit (12) and reset/pulse generation circuit (13) in FIG.
D-type flip-flop circuit) (31) indicates a reset pulse generation circuit. Incidentally, when explaining the specific circuit example of FIG. 1, the same reference numerals are given to the same circuit elements as in FIG. 1.

In FIG. 3, the output of the gate circuit (9) is rH.

When the level is reached, the R8-FFCR8 type flip-flop circuit (32) is set, and its Q output becomes rH. Here, if the terminal (33) of the phase comparator (22) is at the rH level, the output of the AND gate (34) is at the rH level, and is passed through the OR gate (35) to the D
- Applied to the D input of FF (31). D-FF (31
) is applied with a clock signal from a clock terminal (11), and in response to the fall of the clock signal, its Q output becomes rH, level, and RS -F
F (32) is reset, and its Q output becomes rL'' level in response to the falling edge of the next clock signal. Therefore, a reset pulse with a constant width is obtained at the output terminal (36).

Also, if RS-FF (32) remains in the reset state,
Terminal (33) is rH, level, synchronization detection circuit (16)
Suppose that the terminal (37) of is generating the rH level.

In this state, the terminal (38) of the 50/60 discrimination circuit (15)
) is generating the “H” level, the terminal (39
) is applied to the D-FF (31) via the AND gate (40) and the OR gate (35). Also, in that state, connect the terminal (
38) is at the level r L , the AND gates (40), (41), <42) are all closed, and the fifth output signal φ from the terminal (43) becomes the OR gate (
35) to D-F F (31).

Also, R8-FF (32) remains in the reset state and the terminal (
33) is at the "L" level. In this state, when the terminal (38) is at the 1H level, the first output signal φ from the terminal (44) is applied to the D-FF (31) via the AND gate (42) and the gate (35). be done. In this state, if the terminal (38) is at the "L" level, the second output signal i from the terminal (45) will be sent to the D-FF (3) via the AND gate (41) and the OR gate (35).
1) can be applied.

Therefore, the output terminal (36) has the first to third output signals φ.
1 to φ and a reset pulse corresponding to the fifth output signal φ6 is generated.

FIG. 3 is a circuit diagram showing a specific circuit example of the 50/60 discrimination circuit (15) of FIG. 1. Assuming that an NTSC vertical synchronization signal is being received now, the first R8-FF (47) is set in response to the sixth output signal φ from the terminal (46), and its Q output becomes 1H'' level. , the first AND gate (48> is opened. Therefore, the reset pulse from the reset pulse generation circuit (13) is applied to the first AND gate (48).
)(48>, T-F F (49) and (50
) is incorrectly applied to the first counter (dan). and,
When four reset pulses are counted, the output of the second AND gate (52) becomes rH'' level, and the second R8-
Set FF (53). Therefore, the output terminal (54)
becomes the 'HJ level, and it is determined that the NTSC system is being received.

Also, if a PAL vertical synchronization signal is being received, the reset pulse is not applied when the first R3-FF (47) is in the set state, so the first AND gate (
The output of 48) maintains the level r L . And the seventh
When the output signal ≠ is applied, the first R3-FF (47) is reset, its G output becomes rH level, and the third AND gate (55) is opened. Therefore, the reset pulse passes through the third AND gate (55) and the T-FF (56
) and (57). Then, as in the previous case, the fourth AND gate (5
9) becomes rH, level and the second R5-FF (53
), and the output terminal (54) is inverted to "L" level.

FIG. 4 is a circuit diagram showing the synchronization detection circuit (16) of FIG. 1. If we are currently receiving a regular vertical synchronization signal of the NTSC system, the output signal of the 50/60 discrimination port (15) will be at the 1H level, so the first and third AND gates (60) and ( 61) is in the open state, the second and fourth AND gates (62) and (63) are in the closed state, and the output of the first AND gate (60) is in response to the sixth output signal φ from the terminal (64). “H, level and or gate (
65) to the first R3-FF (66).

Then, the Q output of the first R3-FF (66) becomes 1H'' level, and the reset pulse from the reset pulse generation circuit (13) is sent to the quaternary counter (required) consisting of T-FF (67) and (68). applied. When four reset pulses are counted, the output of the AND gate (70) becomes rH" level, and the second R3-FF (71) is set, and its Q output is set to rH, level. In addition, 1st R5
-FF (66) is the seventh output signal φ or the 14th output signal φ14 because the third AND gate (61) is open.
will be reset accordingly. Therefore, the AND gate (72
) is between 224H and 288H, or between 224H and 1.5
A reset pulse can be passed during H.

If the vertical synchronization signal is lost in this state, the third output signal φ8 from the terminal (73) will be
) is applied to Since the other two inputs of the AND gate (c) are both at the rH level, the third output signal φ passes through the OR gate (75) and is output to the quaternary counter (
2) and the second R3-FF (71) are reset. Therefore, the Q output of the second R8-FF (71) is immediately reversed.
L, level.

Next, if a regular PAL vertical synchronization signal is received, the output of the 50/60 discrimination circuit (15) is r L
, the level, so the first and third AND gates (60)
and (61) are in an open state, and the second and fourth AND gates (62) and (63) are in an open state. For that reason,
7th output signal from terminal (76) ≠, 1st R3
-FF (66) is set, and its Q output becomes 1H'' level. Therefore, the reset pulse is
72), and in the same manner as above, the 2nd R3
-Q output of FF (71) becomes "H" level.

Note that the first R5-FF (66) is the third AND gate (61
) is in the closed state, so the fifth output signal≠ or the fourteenth output signal
It is reset in response to the output signal d14.

Therefore, the AND gate (72) is from 288H to 356H.
The reset pulse can be passed between 288H and 1.5H.

In this state, if the vertical synchronization signal is missing, the fifth output signal φ from the terminal (77) will be changed to the OR gate (75
) through the quaternary counter (normal) and the second R8-FF (7
1) to reset each of them. Therefore, the second
The Q output of R3-FF (71) is immediately inverted to rL'' level. Note that since the output signal of the 50/60 discrimination circuit (15) at the rL level is applied to the AND gate (74), its output is at the rL level.

FIG. 5 is a circuit diagram showing a specific circuit example of the gate signal selection circuit (17) of FIG. 1. Now, the synchronization detection circuit (16)
Terminal (78) "RH" level, 50/60 discrimination circuit (
Assume that the terminal (79) of 15) is at rH level.

In this state, the terminal (80) of the phase comparison circuit (22) is
When the level is H, the 10th output signal φ111 from the terminal (81) is connected to the AND gate (82) and the NOR gate (83).
) and gate circuit (9) via AND gate (84)
It can be applied to the awn. Also, in that state, the terminal (80) is r L
, the eighth output signal from the terminal (85) is -1.
is similarly connected to the gate circuit (9) via the AND gate (86).
) is applied to

Also, the terminal (78) is rH, level, and the terminal (79) is "
If the terminal (80) is at the "L" level and the terminal (80) is at the "H" level, the eleventh output signal φII from the terminal (87) is similarly applied to the gate circuit (9) via the AND gate (88). In addition, if the terminal (80) is at the r L level in that state, the ninth output signal from the terminal (89)≠
, is similarly connected to the gate circuit (
9).

Furthermore, when the terminal (78) becomes "L" level, the AND gate (84) is closed, and the 12th output signal φ1□ from the terminal (91) is sent to the gate circuit (9) via the AND gate (92).
) is applied to

FIG. 5 is a circuit diagram showing a specific circuit example of the first signal selection circuit (18) and delay circuit (19) in FIG.
3) shows the delay circuit (19). When the discrimination terminal (94) of the 50/60 discrimination circuit (15) is at the rH" level, the first output signal φ1 from the terminal (95) passes through the AND gate (96> and the OR gate (97) and becomes D-. FF
(93) is applied to the D input. Also, conversely, the discrimination terminal (9
4) is at the level r L , the second output signal φ from the terminal (98) is applied to the D input of the D-FF (93) via the AND gate (99) and the OR gate (97). And D-F F (93) is a clock terminal (1
The D input is delayed by 0.5H according to the clock signal from 1).

FIG. 7 is a circuit diagram showing a specific circuit example of the holding circuit (20)-1 second signal selection circuit (21) and phase comparator circuit (22) in FIG. circuit(
20), the first to fourth AND gates (101) to (104), the OR gate (105) and the NOAH gate (
106) indicates the second signal selection circuit (21), D -F
F (107), 5th and 6th AND gate (108
) and (109), the first and second counters (110) and (111), and the second R3-FF (112) indicate a phase comparison circuit (22). Now, 2nd RS-F
When the output terminal (113) of F (112) is at rH level, the first and third AND gates (101) and (
103) is developed. Then, the output signal of the delay circuit (19) is transmitted to the first AND gate (101) and the NOR gate (1
06) to the D input of D −F F (107). Further, the reset pulse from the reset pulse generation circuit (13) is applied to the C input of D-FF (107) via the third AND gate (103) and NOR gate (106), and the phases of both signals are compared. It will be done. Conversely, when the output terminal (113) is at the r L level, the second and fourth AND gates (102) and (104)
will be developed. Then, the Q output of the first RS-FF (100) reset according to the gate circuit (9>) becomes the D input of the D-FF (107) via the second AND gate (102) and the OR gate (105). Also, the fourth output signal -4 from the terminal (114) is applied to D via the fourth AND gate (104) and NOR gate (106).
-F F (to7) is applied to the C input, and the phases of both signals are compared. FIG. 8 is a waveform diagram showing an example of the phase comparison operation.

For example, assume that the output terminal (113) is at rH level. In this state, if the phase of the clock signal is as shown in FIG. 8 (a), the gate circuit (9) in FIG.
If a vertical synchronizing signal as shown in FIG. 8(c) is generated and applied to the reset pulse generating circuit (13), a reset pulse as shown in FIG. . And the reset pulse is a third AND gate (103) and a NOR gate (106).
D-F F (107
) is applied to the C input of On the other hand, the counter (1
0) to a first output signal φ1 as shown in FIG.
The signal is delayed by 0.5H and applied to the D input of D-FF (107) via the first AND gate (101) and OR gate (105) as shown in FIG. D
-F F (107) is a falling operation, so timing 1. It can be seen that the Q output becomes rH level, indicating that the phases match. Then, when the fifth AND gate (108) is opened according to the Q output, the terminal (
115) from the 15th output signal φ1. passes through it,
applied to the first counter (110). Then, the fifteenth output signal φ1. When is counted four times, the first count,
(110) sets the second R3-F F (112) and brings its Q output to the level r L . Also, D-F
If the phases of the two signals do not match in F (107), the sixth AND gate (109) opens,
Counting is performed by the second counter (111), and the second RS
-F F (112) is reset and its Q output is r
Set to H level.

In the explanation of FIG. 1, the case of the NTSC system and the PAL system was explained, but the present invention is not limited to this, and the present invention is not limited to this.
It is applicable to any system (TSC system and SECAM system).

(G) Effects of the Invention As described above, according to the present invention, it is possible to provide a unique window (gate period) for the vertical synchronization signals of the first and second broadcasting systems with different vertical periods, so that the influence of external noise It is possible to generate vertical drive pulses in accordance with different broadcasting systems without being affected by the noise.

In particular, according to the present invention, two windows are provided for the vertical synchronization signal of each broadcasting system, and when it is confirmed that the vertical synchronization signal exists in the first wide window, the vertical synchronization signal is displayed in the second narrow window. Switching. Even when a narrow window is applied, the period of the vertical synchronization signal arriving from the outside is observed, and if there is a fluctuation in the period, the counter is synchronized with the external vertical synchronization signal, so the vertical synchronization signal is stable. Drive pulses can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIGS. 2, 3, 4, 5, 6, and 7 are circuit diagrams showing specific circuit examples of FIG. 1. 8 is a waveform diagram for explaining FIG. 7, and FIG. 9 is a circuit diagram showing a gate circuit of a conventional automatic discrimination device for television broadcasting. (9)...Gate circuit, (10)...Counter,
(11)...Clock terminal, (12)...Input selection circuit, (13)...Reset pulse generation circuit,
(14)...Output terminal, (15)...50/60
Discrimination circuit, (16)...Synchronization detection circuit, (17)
...Gate signal selection circuit, (18)...First signal selection circuit, (19)...Delay circuit, (20)...
-Holding circuit, (21)...second signal selection circuit, (
22)...Phase comparison circuit.

Claims (7)

[Claims] (1) A gate circuit that passes the vertical synchronization signal applied to the input terminal in accordance with the control signal, and a gate circuit that is reset by a signal corresponding to the vertical synchronization signal that passes through the gate circuit, and a signal that is an integer multiple of the horizontal synchronization signal frequency. Count the frequency signals,
a counter that generates a wide gate signal corresponding to a wide period in which the vertical synchronization signal is expected to arrive and a narrow gate signal corresponding to a narrow period in which the vertical synchronization signal is expected to arrive; a phase comparison circuit that performs a phase comparison between a frequency-divided output signal having a period equal to the generated vertical synchronization signal and the vertical synchronization signal from the gate circuit; A vertical drive pulse generation circuit comprising a gate signal selection circuit that applies a narrow width gate signal as a control signal to the gate circuit, and characterized in that two types of wide and narrow gate periods are provided for the vertical synchronization signal. (2) A gate circuit that passes vertical synchronization signals of the first and second broadcasting systems applied to the input terminal according to a control signal, and is reset by a signal corresponding to the vertical synchronization signal that passes through the gate circuit. A first frequency-divided output signal corresponding to a wide period in which the vertical synchronizing signal of the first broadcasting method is expected to arrive, by counting signals having a frequency that is an integral multiple of the horizontal synchronizing signal frequency; a second frequency-divided output signal corresponding to an expected narrow period; and a third frequency-divided output signal corresponding to a wide period during which the vertical synchronization signal of the second broadcasting method is expected to arrive.
a fourth frequency-divided output signal corresponding to a narrow period in which the vertical synchronization signal is expected to arrive, a fifth frequency-divided output signal corresponding to the vertical period of the first broadcasting method, a second frequency-divided output signal corresponding to the vertical period of the first broadcasting method; a counter that generates a sixth frequency-divided output signal corresponding to the vertical period of the broadcasting system; a broadcasting system determining circuit that determines whether the incoming vertical synchronization signal is the first broadcasting system or the second broadcasting system; a first signal selection circuit that selects and outputs one of the fifth and sixth frequency-divided output signals according to the discrimination output of the broadcast system discrimination circuit; and a signal corresponding to the vertical synchronization signal generated from the gate circuit and the first signal a phase comparison circuit that performs phase comparison with the output signal of the 1-signal selection circuit, and controls the first to fourth frequency-divided output signals according to the output signal of the phase comparison circuit and the discrimination output of the broadcasting system discrimination circuit. A vertical drive pulse generation circuit comprising a gate signal selection circuit that applies a signal to the gate circuit, and characterized in that two types of wide and narrow gate periods are provided for vertical synchronizing signals of first and second broadcasting systems. (3) The counter has a seventh frequency-divided output signal corresponding to a wide period in which the vertical synchronization signals of the first and second broadcasting systems are expected to arrive, and the counter A synchronization detection circuit is provided for detecting that the gate circuit is not reset and is in a self-resetting state, and the seventh frequency-divided output signal is applied as a control signal to the gate circuit in accordance with the output signal of the synchronization detection circuit. 3. The vertical drive pulse generation circuit according to claim 2, wherein the vertical drive pulse generation circuit is configured as follows. (4) Claim 2 or 3, further comprising a reset pulse generation circuit that generates a reset pulse for resetting the counter in accordance with the output signal of the gate circuit.
Vertical drive pulse generation circuit described in . (5) The vertical drive pulse generation circuit according to claim 2 or 3, characterized in that a delay circuit is provided between the first signal selection circuit and the phase comparison circuit. (6) An input selection circuit to which the vertical synchronization signal generated from the gate circuit and the fifth and sixth divided output signals generated from the counter are applied, and selects and outputs one of the signals according to the output signal of the phase comparison circuit. 3. The vertical drive pulse generation circuit according to claim 2, further comprising: a counter configured to be reset in accordance with an output signal of said input selection circuit. (7) Selectively select the reset pulse from the reset pulse generation circuit and the output signal of the first signal selection circuit, or the signal corresponding to the vertical synchronization signal from the gate circuit and the eighth frequency-divided output signal of the counter. Claim 4, characterized in that a second signal selection circuit is provided which switches and applies the signal to the phase comparison circuit, and the state of the second signal selection circuit is switched in accordance with the output signal of the phase comparison circuit. Vertical drive pulse generation circuit.