JPH01292863A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce cell area and deterioration of write by forming a side wall only on a gate sidewall of a periphery transistor section execpting the cell transistor section of a nonvolatile memory to make an LDD structure. CONSTITUTION:A side wall 18 is formed only on a polysilicon gate side wall of a peripheral transistor section 14, and not formed on a cell transistor section 13. Therefore, only the peripheral transistor section 14 can be formed in an LDD structure. Since the side wall 18 does not extend crosswise at the cell transistor 13, the interval between the cell transistor and an electrode window 21 can be made small, thus allowing a small cell area. Moreover, write function does not deteriorate because the cell transistor section 13 is not of LDD structure.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, particularly a nonvolatile semiconductor memory device suitable for high integration as an LDD structure, in which a sidewall is formed only on the gate sidewall of peripheral transistors excluding cell transistors. Regarding the manufacturing method, the purpose of the present invention is to provide a method for manufacturing a semiconductor device in which a sidewall is provided only for peripheral transistors and no sidewall is provided for cell transistors, and the present invention aims to provide a method for manufacturing a semiconductor device in which a sidewall is provided only for peripheral transistors, and no sidewall is provided for cell transistors. The method of manufacturing a semiconductor device includes patterning the gate of the cell transistor and the gate of the peripheral transistor separately, and forming a sidewall on the side wall of the gate of only the peripheral transistor. do.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a nonvolatile semiconductor memory device that is suitable for high integration as an LDD structure, in which sidewalls are formed only on the gate sidewalls of peripheral transistors, excluding cell transistors.

[Conventional technology]

In recent years, as semiconductor devices have become highly integrated and miniaturized, junctions have become shallower and channel lengths have become shorter. On the other hand, hot carriers are generated due to the high electric field, and these hot carriers are injected into the gate oxide film of the MOS device, causing a problem of deterioration of characteristics.

In contrast, conventionally, a sidewall is provided on the sidewall of the polysilicon gate on the gate oxide film, and a region with low carrier concentration is formed at the end of the diffusion layer near the drain at the bottom of the sidewall, and by relaxing the electric field near the drain, LDD (Light) prevents deterioration of characteristics due to hot carriers.
ly Doped Drain (a structure with a lightly doped drain) is known.

By the way, as a semiconductor memory, EFROM (E
rasable Programmable Read
0nly Memory).

FIG. 3 is a cross-sectional view showing the memory cell structure of a conventional HFROM.
A polysilicon floating gate 4 and a control gate 5 are formed on the gate oxide film 3 on the channel between the two.
and are covered with an oxide film 6. Further, on the n0 layer 2, an electrode window 7 is formed in an insulating film 9, and an aluminum wiring layer 8, which is partially illustrated, is provided. This EFRO
In M, writing is performed by applying a high electric field to the drain junction and injecting charges into the floating gate 4 through the gate oxide film 3, and erasing is performed by irradiating ultraviolet rays with high energy to inject the charges in the floating gate 4. This is done by applying energy and letting it escape beyond the barrier of the gate oxide film 3.

Even in non-volatile semiconductor memory devices such as EFROM, specifications for peripheral transistors have become stricter as the integration becomes higher, finer, and smaller.
It has become necessary to manufacture the structure.

[Problems to be Solved by the Invention] However, if a conventional non-volatile semiconductor memory device such as an EPROM is made into an LDD structure as it is, as shown in FIG.
A side wall 6a is attached to the side wall portion of the control gate 5.
is formed, and a portion of the n- layer 10 having a low carrier concentration at the end of the n+ layer near the drain is formed below the sidewall 6a. However, unlike other semiconductor memories, writing in EFROM is performed by injecting hot electrons generated by avalanche collapse into the floating gate 4. Therefore, when the cell transistor part shown in FIG. 4 has an LDD structure, avalanche collapse There was a problem that hot electrons were less likely to be generated due to this, resulting in poor writing. Further, the distance between the cell transistor and the electrode window 7 becomes stricter than before due to the side wall 68 of the cell transistor extending sideways. If the n+ layer 10 is provided under the sidewall 6a of the cell transistor section, the problem of writing can be avoided, but the problem of the spacing between the cell transistor and the electrode window 7 will not be solved. Additionally, an increase in the number of steps is also considered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which sidewalls are provided only for peripheral transistors and no sidewalls are provided for cell transistors.

[Means to solve problems]

The above problem is solved in a method of manufacturing a nonvolatile semiconductor memory device including a cell transistor section and a peripheral transistor section, in which the gate of the peripheral transistor and the gate of the cell transistor are patterned separately, and only the peripheral transistor is patterned on its gate sidewall. The problem is solved by a method for manufacturing a semiconductor device, which is characterized in that a sidewall is formed in the semiconductor device.

[Effect]

In the present invention, a sidewall is formed on the sidewall of the gate of the peripheral transistor of a nonvolatile semiconductor memory device, no sidewall is formed on the gate of the memory region, and only the peripheral transistor has an LDD structure, so that the cell area can be reduced. Also, writing will not deteriorate.

〔Example〕

Hereinafter, the present invention will be specifically explained with reference to an illustrated embodiment.

FIGS. 1(a) to 1(a) are cross-sectional views of the manufacturing process of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

First, as shown in FIG. 1(a), a field oxide film 12 is formed on a P-type silicon substrate 11 by a conventional method, and gate oxidation is performed on a cell transistor section 13 and a peripheral transistor section 14 corresponding to an element formation region. Film thickness is 300~
Approximately 400 gate oxide films 15 are formed. and,
Boron ions (B) are implanted to form a channel (acceleration voltage 50-70 keV).

Dose amount IXl0-"cm-").

Next, as shown in FIG. 1(b), 20% of polysilicon A was
The film is deposited to a thickness of approximately 0.00 to 3,000 nm, and patterned so as to remain on the gate oxide film 15 of the cell transistor section 13 as a floating gate.

Next, as shown in FIG. 1(C), polysilicon A is thermally oxidized to form an oxide film (St(h film) 1
After forming 6, polysilicon B is coated with 2000 to 3
The film is deposited to a thickness of about 1,000 ml.

Next, as shown in FIG. 1(d), after patterning the polysilicon B only in the peripheral transistor region to form a polysilicon gate, phosphorus ions were injected at an acceleration voltage of 5 (1 to 70Ke).
Ions are implanted at a dose of IXIO"co+-!, and a low concentration n- layer 17 is formed in the peripheral transistor section 14 using the gate of polysilicon B as a mask. At this time, the cell transistor section Since 13 is covered with polysilicon B, n- layer 17 is not formed.

Next, as shown in FIG. 1(e), when silicon oxide (SiOz) is deposited by vapor phase growth and etched back by ζ anisotropic etching, the Sing on the flat surface of polysilicon B is Although it is etched, the peripheral transistor 1
Sidewalls 18 are formed only on the gate sidewalls of polysilicon B of No. 4.

Next, as shown in FIG. 1(f), the cell transistor section 1
3, polysilicon A and polysilicon B are simultaneously patterned to form a floating gate and a control gate.

Next, as shown in Figure 1 (powder), in order to prevent damage caused by ion implantation, through oxidation was performed to form an oxide film on the surface of polysilicon B, and then arsenic ions were injected at an accelerating voltage of 50 to 70 KeV. degree, dose amount I XIO”cm-
A high concentration N9 layer 19 is formed in the cell transistor section 13 and the peripheral transistor section 14. At this time, the lower part of the side wall 18 of the peripheral transistor is masked by this side wall 18 and is not implanted with ions. .

Thereafter, it is formed by a normal manufacturing process of a nonvolatile semiconductor memory device.

FIG. 2 is a cross-sectional view of a nonvolatile semiconductor memory device formed by the above manufacturing process. Note that parts corresponding to those in FIG. 1 are denoted by the same reference numerals. In the figure, after the barrel process shown in Figure 1 above, silicon oxide (
SiO□) film 20, electrode window 21, aluminum wiring N
22, 23, etc. are formed.

According to the above manufacturing method, since the sidewall 18 is formed only on the sidewall of the polysilicon gate of the peripheral transistor section 14 and not on the cell transistor section 13, only the peripheral transistor section 14 can have an LDD structure. Therefore, in the cell transistor section 13, the sidewall 18 does not protrude laterally, and the interval between the cell transistor and the electrode window 21 can be narrowed, making it possible to reduce the cell area. Since the transistor section 13 does not have an LDD structure, the write function will not deteriorate.Furthermore, in this embodiment, when ion implantation is performed in the n- layer 17, the cell transistor section 13 side is masked or the n+ layer 19 is ion-implanted. During ion implantation, the peripheral transistor section 14 is not specially masked, the number of masks used does not increase compared to the conventional method, and the process is shortened.

Note that in the present invention, only the peripheral transistors of the nonvolatile semiconductor memory device need only have a sidewall formed on their gate sidewalls to have an LDD structure (the types of diffusion regions, implanted ions, etc. are not limited to the embodiments).

〔Effect of the invention〕

As explained above, according to the present invention, in a nonvolatile memory, a sidewall is formed only on the gate side wall of the peripheral transistor section excluding the cell transistor section, resulting in an LDD structure, so that the cell area can be reduced, and
Writing also does not deteriorate. Further, the number of masks used does not increase, and the process can be shortened.

[Brief explanation of the drawing]

1(a) to (6) are sectional views of the manufacturing process of the embodiment of the present invention, FIG. 2 is a sectional view of the EFROM of the embodiment of the present invention, FIG. 3 is a sectional diagram of the conventional Er'ROM, and FIG. The figure shows a conventional LDD
FIG. 2 is a cross-sectional view of an EPROM structure. In the figure, 11 is a p-type silicon substrate, 12 is a field oxide film, 13 is a cell transistor section, 14 is a peripheral transistor section, 15 is a gate oxide film, 16 is a SiO□ film, 17 is an n-layer, and 18 is a sidewall. , 19 is the n layer, 20 is the SiO2 film, 21 is the electrode window, and 22 and 23 are the aluminum wiring layers. Patent Applicant: Fujitsu Ltd. Agent, Patent Attorney: Gen Kukimoto, Akido Otsuwa Yoshiyuki” (Telegraph 8H) 1.1, 1 EPROM d1. L D D ah E PROM Jrillll
nFigure 4

Claims (1)

[Claims] Cell transistor section (13) and peripheral transistor section (1
4) In the method for manufacturing a nonvolatile semiconductor memory device, the gate of the cell transistor (13) and the gate of the peripheral transistor (14) are patterned separately, and only the peripheral transistor (14) has its gate sidewall patterned. 1. A method of manufacturing a semiconductor device, comprising forming a sidewall (18) on the surface of the semiconductor device.