JPH01289320A - Delta modulator - Google Patents

Abstract

PURPOSE:To reduce the distortion caused due to the delay characteristic of a component by providing a bias circuit controlling a DC bias of an analog input signal between an analog signal input terminal and a comparator. CONSTITUTION:A capacitor 207 eliminating the DC component of an analog input signal, a resistor 101 controlling the DC bias of the analog input signal, a DC voltage source 102 and a bias circuit 103 are provided to the modulator. Then the DC bias is controlled to differentiate the absolute value of the slope of the increasing potential of the input signal to the comparator from the absolute value of the slope of the decreasing potential. When the potential of the input signal of the comparator is decreasing, the absolute value of the slope of is small and the input signal to the comparator gets a higher potential with respect to the comparator reference potential consecutively for some times. When the potential of the input signal to the comparator is increasing, the absolute value of the slope is increased and the probability of the higher potential than the reference potential of the comparator is increased between the sampling period and the retarded period. Thus, the delta modulator with high performance while reducing the production of distortion is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a delta modulator that reduces distortion among analog-to-digital converters.

A conventional delta modulator is a type of analog-to-digital converter that focuses on the difference between each sample when sampling at regular intervals, encodes this information, and converts the information generated due to this encoding. The quantization error is corrected for subsequent samples.

Hereinafter, a conventional delta modulator as described above will be explained with reference to the drawings. FIG. 3 is a block diagram showing the configuration of a conventional delta modulator. In general, a delta modulator has an analog signal input terminal 20 as shown in FIG.
1. Subtractor 202. Comparator 2o31 local demodulator 2o4.
The delta modulation signal output terminal 205 outputs information as to whether the analog input signal has increased or decreased compared to the potential sampled one sampling period before in the form of a 1-pit sign. It is.

The analog signal input to the analog signal input terminal 201 is input to the subtracter 202. The subtracter 202 takes the difference between the analog signal and the output of the local demodulator 204, which is a potential sampled one sampling period before, and outputs the difference to the comparator 203. If the signal input to the comparator 203 is larger than a certain reference potential, the analog input signal is increasing, and the comparator 203 outputs "1" to the modulation signal output terminal 20.
Output to 15. If the signal input to the comparator 203 is smaller than the reference potential, the analog input signal is decreasing, and the comparator 203 outputs 0'' to the delta modulation signal output terminal 20.
Output to 5. This 1”.

0" becomes the delta modulation signal. On the other hand, the local demodulator 204 demodulates the delta modulation signal that is the output of the ratio 1 modulator 203 and outputs an analog signal to the subtracter 202.

FIG. 4 is a circuit diagram showing an example of the conventional delta modulator mentioned above. The analog signal input from the analog signal input terminal 206 has its DC component removed through a capacitor 207, is added to the signal passed through a resistor 209 from the output of the local demodulator 215 through a resistor 208, and is input to the D terminal of the D flip-frog 213. be done. However, since the inverted output (NO terminal) of the D flip-flop 213 is used as the input to the local demodulator 215, the resistor 20B and the resistor 209 have the same effect as a subtracter.

Next, the D flip-flop 213 uses the input potential to compare the analog input signal with the potential sampled one sampling period before. If the potential of the D terminal is higher than the threshold level, ``1'' is output to the Q terminal and 0'' is output to the NO terminal. If the potential of the D terminal is lower than the threshold level, 0'' is output to the Q terminal and 1' is output to the NQ terminal.

The signal output from the Q terminal of the D flip 70 tube 213 is a delta modulation signal, and the delta modulation signal output terminal 21
4 is output. On the other hand, 1″ output from the NO terminal,
The delta modulated signal with the "○" inverted is input to the local demodulator 215. The local demodulator 216 is composed of a resistor 211 and a capacitor 210, and when the potentials corresponding to '1'' and Q'' are input, the voltage is applied to the capacitor 210 through the resistor 211.
Charge and discharge. When the time constant τ of the resistor 211 and capacitor 210 is much larger than the sampling period T, the local demodulator 215 becomes an integrating circuit, and the integrated result is the inverted potential of the analog input signal sampled one sampling period ago. Become.

Problems to be Solved by the Invention However, the above-mentioned conventional delta modulator has the problem of generating characteristic 1 distortion of a D flip-flop. The generation of distortion will be explained below.

Figure 6 shows (a) clock signal when the analog input signal is zero, (b) D terminal input signal of the D flip-flop of an ideal delta modulator, (0) D flip-flop of the ideal delta modulator. (d) D terminal input signal of the D flip-flop in the conventional delta modulator (point B in Figure 4); (e) Output of the Q terminal of the D flip-flop in the conventional delta modulator. 5 is a waveform diagram showing an example of a signal (0 point in FIG. 4); FIG. When the analog input signal is zero, ideally the output delta modulation signal changes from 1'' to 0' at each rising edge of the clock signal supplied to the D flip-flop, as shown in Figure 5(C). It becomes a repeating signal.If the input signal at the D terminal of the D flip-flop is at a higher potential than the threshold level /L'VTH at the rising edge of a certain clock, "1" is output from the Q terminal. '0' is output from the NQ terminal. When no II is output from the NQ terminal, the local modulator is discharged with a time constant determined by the resistor and capacitor of the local demodulator, and the input signal at the D terminal of the D flip-frog begins to fall and reaches a potential lower than vTH. Become. Then, at the next rising edge of the clock, the potential at the D terminal of the D flip-flop is lower than vTH, so 0' is output from the Q terminal and 1'' is output from the NO terminal.

When '1' is output from the NO terminal, charging is performed in the local demodulator, and the input potential of the D terminal of the D flip-flop begins to rise and becomes higher than vTH.

Due to such repetition, in an ideal operation, 1'' and 0'' are repeatedly output from the Q terminal of the D flip-flop.

However, in the conventional delta modulator, in the actual D flip-flop, there is a delay Δt from the rising edge of the clock signal until it is output to the Q terminal or NQ terminal, so the delta modulation signal from the D terminal of the D71J flip-flop is 1" , 0'' are not output alternately. As shown in FIG. 6(d), if the input signal at the D terminal of the D flip-flop is at a higher potential than the threshold level vTH at the rising edge of a certain clock, there is a delay Δt, so the input signal from the NQ terminal is Δt. 0" is output after a delay of
The potential of the input signal at the terminal begins to fall after a delay of Δt. At this time, a state occurs in which the input signal at the D terminal is still at a higher potential than vTH even at the rising edge of the next clock. When the input signal at the D terminal has a higher potential than vTH, "o" is output from the NQ terminal again, and the potential at the D terminal continues to fall. At the next rising edge of the clock, the input signal of the D terminal becomes a lower potential than vTH, and 1" is output from the NO terminal with a delay of Δt. Furthermore, at the rising edge of the next clock, 1" is output again due to the delay Δt. It is output from the NQ terminal. In other words, since there is a delay from the rising edge of the clock to the output to the NO terminal in the D flip-flop, the Q signal is a delta modulated signal.
The output of the terminal is not ``1'' and ``0'' alternately,
It repeats like 1”, 1”, ’o”, ”O”,
It will no longer be ideal movement.

In the above example, we talked about the case where the analog input signal is zero, but if the input signal is not zero, the 1", 1", 0
The repetition of ", '0" occurs as distortion. In the circuit diagram of the conventional delta modulator shown in FIG. 4, the potential at point A is the threshold rep/L' of the D flip-flop 213.
1”, ’1”, ’ when near V TH
0”.

0" repetitions are likely to occur, and the power supply voltage esV.

v'rI (2.5V, 5 when NO terminal output is 1")
V.

When a sine wave is input to the analog signal input terminal using a D flip-flop whose voltage is 0", the point where the absolute value of the slope of the sine wave is the largest is the potential of 2.5V, so this Distortion occurs at this point, and second harmonic distortion occurs in the delta modulated signal.

The present invention solves these conventional problems and provides a high-performance delta modulator that reduces distortion.

Means for Solving the Problems To achieve this object, the delta modulator of the present invention is characterized in that a bias circuit for controlling the DC bias of the analog input signal is provided between the analog signal input terminal and the comparator. There is.

Effect of the present invention With the above-described configuration, by controlling the DC bias, the absolute value of the slope when the potential of the input signal of the comparator increases is different from the absolute value of the slope when the potential of the input signal of the comparator decreases. When the potential is falling, the absolute value of the slope is small and the comparator input signal becomes high potential several times in succession relative to the comparator reference potential. Therefore, even if the comparator outputs 1" continuously due to the delay, the delta modulation signal has originally been 1" several times in a row, so the relative error due to one successive output will be small. Distortion generation becomes smaller.

In addition, when the potential of the input signal of the comparator is rising, the absolute value of the slope becomes large, and the probability that the potential becomes higher than the reference potential of the comparator between the sampling period and the delay increases. The probability of outputting "o" decreases. Therefore, the occurrence of distortion can be reduced, and a high-performance delta modulator can be realized.

Embodiment A delta modulator according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a delta modulator in one embodiment of the present invention. The delta modulator of this embodiment shown in FIG. 1 basically has the same configuration as the conventional delta modulator, so the same components are given the same numbers and detailed explanations will be omitted.

In FIG. 1, 207 is a capacitor that removes the DC component of the analog input signal, 1o1 is a resistor that controls the DC bias of the analog input signal, 102 is a DC voltage source, and 103 is a bias circuit.

Like the conventional delta modulator shown in FIG. 4, the embodiment of the present invention also adds the output of the local demodulator 216 and the analog input signal.
Because of the presence of the resistors 208 and 209, current flows through the resistors 208 and 209, and the absolute value of the slope of the time change when the output potential of the local demodulator 215 increases or decreases due to charging and discharging of the capacitor 210 of the local demodulator 216 is different. It's coming. In other words, D
Regarding the input potential of the D terminal of the flip-flop 213, the absolute value of the slope when rising is large, and the absolute value of the slope when falling is small.

FIG. 2 shows an example of (a) the sampling clock signal of the comparator, (b) the comparator input signal, and (C) the output delta modulation signal when the analog input signal in the delta modulator of this embodiment is zero. FIG. As can be seen from FIG. 2(b), by controlling the DC bias, the absolute value of the slope when the potential of the comparator input signal rises is different from the absolute value of the slope when the potential falls.

When the potential of the comparator input signal is falling, the absolute value of the slope is small and the comparator input signal becomes high potential several times in succession with respect to the comparator reference potential. Therefore, even if the comparator outputs 1" continuously due to the delay, the delta modulation signal is originally 1" several times in a row, so it is 1".
The relative error caused by successive times becomes smaller, and the occurrence of distortion becomes smaller. In addition, when the potential of the comparator input signal is rising, the absolute value of the slope increases, and the probability that the potential becomes higher than the comparator reference potential during the sampling period T and the delay Δt (T - Δt) increases. , the probability of outputting "0" continuously decreases.

Therefore, the occurrence of distortion due to the delay of the D flip-flop 213 can be reduced, and a high-performance delta modulator can be realized.

As described above, by controlling the DC bias of the analog input signal, a high-performance delta modulator with reduced distortion generation can be achieved.

In this embodiment, the bias of the analog input signal is controlled by connecting it to a constant voltage source via the resistor 1o1 immediately after the capacitor 207 that removes the DC component of the analog input signal. A similar effect can be obtained by connecting the capacitor to a constant voltage source via a resistor to perform bias control.

As described in detail, the delta modulator of the present invention makes it possible to reduce distortion caused by the delay characteristics of the element using a bias circuit that controls the DC bias of an analog input signal. 0

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a delta modulator according to an embodiment of the present invention, and FIG. 2 shows (a) a sampling clock signal when the analog input signal is zero, and (b) a D flip-flop of the delta modulator of the present invention. (C) D terminal input signal of the present invention
Figure 3 is a block diagram showing a conventional delta modulator, Figure 4 is a circuit diagram of a conventional delta modulator, and Figure 5 is an analog input signal. (a) Sampling clock signal when the signal is zero; (b) D terminal input signal of the D flip-flop of an ideal delta modulator; (CI) Q terminal output of the D flip-flop of the ideal delta modulator. (d) D terminal input signal of the D flip-flop of the delta modulator in the conventional example; and (e) waveform diagram of the Q terminal output signal of the D flip-flop of the delta modulator in the conventional example. 101...Resistance for bias circuit, 102...
...DC voltage source, 206...analog signal input terminal, 212...sampling clock input terminal,
213...D flip-flop, 214...
... Delta modulation signal output terminal, 215 ... Local demodulator, 201 ... Analog signal input terminal,
202...Subtractor, 203...Comparator, 204...Local demodulator, 206...
Delta modulation signal output terminal, T...period of sampling clock, vTH...threshold level of D flip-flop, Δt...clock 2NQ delay time of D flip-flop . Name of agent: Patent attorney Toshio Nakao and 1 other person10
j-... Bias circuit 206-° A6 log signal input Naruko, 212-... Sampling clock input j%chi 213-D Fushi Tsubu flop F! +4- Jiruri Modulation Den Yo Shichiriki Sadakuko Figure 1 Z+5
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Claims (1)

[Claims] a subtracter that takes the difference between an input signal input from an analog signal input terminal and a local demodulation signal; a comparator that samples the output of the subtracter and converts it into a delta modulation signal; and a comparator that converts the output of the comparator into an analog signal. A delta modulator, comprising a local demodulator for demodulating and outputting a local demodulated signal, and further comprising a bias circuit for controlling a DC bias of the analog input signal between the analog signal input terminal and the comparator.