JPH01289301A - High frequency integrated circuit - Google Patents
High frequency integrated circuitInfo
- Publication number
- JPH01289301A JPH01289301A JP63119669A JP11966988A JPH01289301A JP H01289301 A JPH01289301 A JP H01289301A JP 63119669 A JP63119669 A JP 63119669A JP 11966988 A JP11966988 A JP 11966988A JP H01289301 A JPH01289301 A JP H01289301A
- Authority
- JP
- Japan
- Prior art keywords
- characteristic impedance
- substrate
- line
- strip line
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 230000005540 biological transmission Effects 0.000 claims abstract description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 8
- 230000005855 radiation Effects 0.000 abstract description 5
- 230000003247 decreasing effect Effects 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 239000000126 substance Substances 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 239000003989 dielectric material Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Waveguides (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、セラミック基板やGaAs等の半導体基板上
にストリップ線路等の伝送線路が形成された高周波集積
回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a high frequency integrated circuit in which a transmission line such as a strip line is formed on a semiconductor substrate such as a ceramic substrate or GaAs.
〈従来の技術〉
一般に高周波集積回路には、トランジスタ、抵抗やそれ
らを接続するストリップ線路等が同一基板上に集積され
ているため、それらの素子間のインピーダンスを整合す
る回路が必要である。このインピーダンス整合回路の一
つに4分の1波長変成器があり、従来からよく用いられ
ている。<Prior Art> Generally, high-frequency integrated circuits have transistors, resistors, strip lines connecting them, etc. integrated on the same substrate, so a circuit is required to match the impedance between these elements. One of these impedance matching circuits is a quarter wavelength transformer, which has been commonly used in the past.
第3図は、4分の1波長変成器を表わす回路図でZLは
負荷で、点AB間は特性インピーダンスZo1線路長4
分の1波長の線路31である。ここで、点Aから負荷側
をみた入力インピーダンスは、Z in= Zo”/Z
t、となる。例えば、ZL=200ΩでZQ=100
Ωの時、Zin=50Ωとなシ、高インピーダンスを低
インピーダンスに変換できる。Figure 3 is a circuit diagram showing a quarter-wavelength transformer, where ZL is the load, and between points AB is the characteristic impedance Zo1, line length 4.
This is a line 31 of 1/1 wavelength. Here, the input impedance seen from point A to the load side is Z in = Zo''/Z
t. For example, ZL=200Ω and ZQ=100
When Ω, Zin=50Ω, high impedance can be converted to low impedance.
一般的には、負荷zLと入力インピーダンスZinが定
まっており、それらから必要なzoが求まる。Generally, the load zL and input impedance Zin are determined, and the necessary zo can be found from them.
この4分の1波長変成器をストリップ線路で構成する場
合、従来ストリップ線路の線路巾を変えることにより所
望の特性インピーダンスを得ていた。When this quarter-wavelength transformer is constructed using a strip line, a desired characteristic impedance has conventionally been obtained by changing the line width of the strip line.
また、バイアス回路等で高特性インピーダンスの伝送線
路が必要な時も、同様な理由により線路巾を細くしてい
た。Also, when a transmission line with high characteristic impedance is required for a bias circuit or the like, the line width is made narrower for the same reason.
〈発明が解決しようとする問題点〉
しかし、従来の方法では、線路幅を変えなければ、伝送
線路の特性インピーダンスを変えることができないため
、所望の特性インピーダンスが高くなるにつれて、線路
幅がせまくなり、抵抗損が増大するので伝送線路内の伝
送ロスが増大する欠点があった。例えば、基板として、
100μm厚のGaAsf考えると、l0GH2におい
て特性インピーダンス50Ωでは線路幅は約75μmで
あるのに対し、100Ωでは約81tmまで細くなって
しまう。<Problems to be solved by the invention> However, in the conventional method, the characteristic impedance of the transmission line cannot be changed without changing the line width, so as the desired characteristic impedance increases, the line width becomes narrower. However, since the resistance loss increases, the transmission loss within the transmission line increases. For example, as a substrate,
Considering GaAsf with a thickness of 100 μm, the line width is about 75 μm at a characteristic impedance of 50Ω at 10GH2, whereas it becomes narrow to about 81 tm at a characteristic impedance of 100Ω.
また、特性インピーダンスを小さくするために、線路幅
を太くした場合には、放射損が増大するという問題点が
あった。Furthermore, when the line width is increased in order to reduce the characteristic impedance, there is a problem in that radiation loss increases.
本発明は上記の点に鑑みて創案されたものであり、上記
従来の問題点を除去した新規な高周波集積回路を提供す
ることを目的としている。The present invention has been devised in view of the above points, and an object of the present invention is to provide a novel high-frequency integrated circuit that eliminates the above-mentioned conventional problems.
く問題点を解決するための手段〉
上記の目的を達成するため、本発明の高周波集積回路は
、基板と、この基板の一部分を除去した除去部分に埋め
込まれた上記の基板の誘電率と異なる誘電率を持つ誘電
体と、上記の誘電体上に低抵抗率金属等により形成され
た伝送線路とを有してなるように構成している。Means for Solving the Problems In order to achieve the above object, the high frequency integrated circuit of the present invention includes a substrate and a substrate having a dielectric constant different from that of the substrate embedded in the removed portion obtained by removing a portion of the substrate. It is configured to include a dielectric material having a dielectric constant, and a transmission line formed of a low resistivity metal or the like on the dielectric material.
即ち、本発明は基板の一部を、例えば基板の一部分を主
面側より底面まで除去し、その除去部分に、上記の基板
の誘電率と異なる誘′Pt率をもつ誘電体を埋め込み、
上記の基板と上記の誘電体の主面側の高さを略等しくし
、上記の誘電体上に上記の基板上の伝送線路の特性イン
ピーダンスと異なる特性インピーダンスをもつ伝送線路
を形成するように構成している。That is, the present invention removes a part of the substrate, for example, from the main surface side to the bottom surface, embeds a dielectric material having a dielectric constant different from the dielectric constant of the substrate in the removed part, and
The heights of the main surfaces of the substrate and the dielectric are approximately equal, and a transmission line having a characteristic impedance different from the characteristic impedance of the transmission line on the substrate is formed on the dielectric. are doing.
く作 用〉
本発明では、高周波集積回路を構成する基板が部分的に
異なる誘電率を持つことになる。上記の基板の誘電率よ
りも誘電体のそれが小さい時は、ストリップ線路の線路
幅を細くすることなく、特性インピーダンスを大きくで
きる。逆に、基板の誘電率よりも誘電体のそれが大きい
時は、ストリップ線路の線路幅を太くすることなく、特
性インピーダンスを小さくできる0従って、線路幅を変
えることなく特性インピーダンスを変化させることがで
きる。このことにより、特性インピーダンスを大きくし
た時、線路幅を細くしなくても良いため、線路の抵抗に
よる新たな損失を招くことなくまた、特性インピーダン
スを小さくした時、線路幅を太くしなくても良いため、
放射による新たな損失を招くことがない。Effects> In the present invention, the substrates constituting the high frequency integrated circuit have partially different dielectric constants. When the dielectric constant of the dielectric is smaller than the above-described dielectric constant of the substrate, the characteristic impedance can be increased without narrowing the line width of the strip line. Conversely, when the permittivity of the dielectric is larger than that of the substrate, the characteristic impedance can be reduced without increasing the line width of the strip line. Therefore, it is possible to change the characteristic impedance without changing the line width. can. As a result, when the characteristic impedance is increased, there is no need to make the line width thinner, so new losses due to line resistance are not caused, and when the characteristic impedance is decreased, there is no need to make the line width thicker. Because it's good,
No new losses due to radiation are caused.
〈実施例〉
以下、図面を参照して本発明の一実施例を詳細に説明す
る。<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第1図は、本発明の一実施例を示す斜視図である0
第1図において、1は回路基板又はGaAsやSt等の
半導体基板、2はこの基板1及び後述する誘′電体4上
に形成された銅、金、アルミニウム等の低抵抗率金属よ
りなるストリップ線路の伝送線路、3は基板1の裏面に
形成されたストリップ線路の接地電極、4は基板lの誘
電率と異なる誘電率tもつ誘電体で5i02等が利用で
き、第1図のAA’線での断面を第2図に示すように、
基板1の一部分を主面側より底面まで除去した除去部分
に埋め込み形成され、基板1と誘電体4の主面側の高さ
が略等しくされている。FIG. 1 is a perspective view showing one embodiment of the present invention. In FIG. 3 is a ground electrode of the strip line formed on the back surface of the substrate 1, and 4 is a dielectric constant different from that of the substrate 1. 5i02 etc. can be used as a dielectric material with t, and the cross section taken along line AA' in Fig. 1 is shown in Fig. 2.
It is embedded in the removed portion where a part of the substrate 1 is removed from the main surface side to the bottom surface, and the heights of the substrate 1 and the dielectric body 4 on the main surface side are made substantially equal.
更に詳細に説明すると、−例として、基板lとして10
0 Am厚のQ a A S %誘電体4として5iO
zを用いる。5t(hの誘電率は3程度であるので、G
aAsのそれの約1/4である。このため、QaAs基
板1上に形成された75μm巾のストリップ線路の特性
インピーダンスは10 GHzで約500であるのに対
して、Sigh上に形成された同じ巾のストリップ線路
の特性インビーダンスは約1000になる。従って、本
発明によればストリップ線路の線路幅を変化させること
なく特性インピーダンスを変化させることができる。i
た、同じ特性インピーダンスを得るための線路幅は、G
aAsに比べてS i(hの方が太いため、特性インピ
ーダンスが大きくなるほど線路の抵抗による損失を小さ
くできる。In more detail: - By way of example, the substrate l is 10
0 Am thick Q a A S % dielectric 4 as 5iO
Use z. 5t (The dielectric constant of h is about 3, so G
It is about 1/4 of that of aAs. Therefore, the characteristic impedance of a 75 μm wide strip line formed on the QaAs substrate 1 is approximately 500 at 10 GHz, while the characteristic impedance of a strip line of the same width formed on Sigh is approximately It becomes 1000. Therefore, according to the present invention, the characteristic impedance can be changed without changing the line width of the strip line. i
In addition, the line width to obtain the same characteristic impedance is G
Since S i (h is thicker than aAs, the loss due to line resistance can be reduced as the characteristic impedance increases.
本実施例におけるS i(hのGaAs基板へのうめこ
みの製造方法例全次に述べる。An example of the manufacturing method of embedding Si(h into a GaAs substrate in this embodiment) will be described below.
(i)まず5iChのうめこみ部分以外にAtを蒸着し
、GaA s基板裏面にAuを蒸着する。(i) First, At is vapor-deposited in areas other than the recessed portion of the 5iCh, and Au is vapor-deposited on the back surface of the GaAs substrate.
(if)Reactive Ion Etching
(RI E )装置と、BCIa+C12+02混合ガ
スによりGaAsをエツチングする。(if) Reactive Ion Etching
GaAs is etched using a (RI E ) device and a BCIa+C12+02 mixed gas.
(iii) G aA sをエツチングした部分に5i
02を塗布し、GaAs基板上に残った5i(hをRI
EによりエッチバックすることでSighを除去する。(iii) 5i on the etched part of G aA s
02 was applied, and the remaining 5i (h was RI
Sigh is removed by etching back with E.
なお、上記の実施例にあっては基板に埋め込む誘電体と
して5i(hを用いた例を説明したが、本発明はこれに
限定されるものではない。また基板の除去部分に誘電体
を埋め込む場合も、上記した実施例のように基板の主面
側より底面まで除去して誘電体を埋め込む例に限定され
るものではなく、調整すべきストリップ線路の特性イン
ピーダンスの値に応じて、埋め込む誘電体の厚みを調整
すれば良いことは言うまでもない。In addition, in the above embodiment, an example was explained in which 5i (h) was used as the dielectric material to be embedded in the substrate, but the present invention is not limited to this. In this case, the method is not limited to the example of removing the dielectric material from the main surface side of the board to the bottom surface and embedding the dielectric material, as in the above-mentioned embodiment. Needless to say, you can adjust the thickness of your body.
〈発明の効果〉
以上述べたように、本発明によれば、ストリップ線路の
特性インピーダンスを大きくした時、従来の線路幅が細
くなることによる抵抗損の増大を抑え、また、特性イン
ピーダンスを小さくした時、従来の線路幅が太くなるこ
とによる放射損の増大を抑えることができる。<Effects of the Invention> As described above, according to the present invention, when the characteristic impedance of the strip line is increased, the increase in resistance loss caused by the narrowing of the conventional line width can be suppressed, and the characteristic impedance can be reduced. At the same time, it is possible to suppress the increase in radiation loss caused by the conventional line width becoming thicker.
第1図は、本発明の高周波集積回路の一実施例を示す図
、第2図は、第1図のAA’線の断面図、第3図は、4
分の1波長変成器の回路図である。
1・・・GaAs基板、2・・・ストリップ線路の上層
線路、3・・・ストリップ線路の接地線路、4・・・S
i02層0FIG. 1 is a diagram showing an embodiment of the high frequency integrated circuit of the present invention, FIG. 2 is a cross-sectional view taken along line AA' in FIG. 1, and FIG.
FIG. 2 is a circuit diagram of a 1/2 wavelength transformer. 1... GaAs substrate, 2... Upper layer line of strip line, 3... Ground line of strip line, 4... S
i02 layer 0
Claims (1)
基板の誘電率と異なる誘電率を持つ誘電体と、 上記誘電体上に形成された伝送線路と を有してなることを特徴とする高周波集積回路。1. It is characterized by comprising a substrate, a dielectric having a dielectric constant different from that of the substrate embedded in a removed portion obtained by removing a part of the substrate, and a transmission line formed on the dielectric. High frequency integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63119669A JPH01289301A (en) | 1988-05-17 | 1988-05-17 | High frequency integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63119669A JPH01289301A (en) | 1988-05-17 | 1988-05-17 | High frequency integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01289301A true JPH01289301A (en) | 1989-11-21 |
Family
ID=14767125
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63119669A Pending JPH01289301A (en) | 1988-05-17 | 1988-05-17 | High frequency integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01289301A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017098926A (en) * | 2015-11-13 | 2017-06-01 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
1988
- 1988-05-17 JP JP63119669A patent/JPH01289301A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017098926A (en) * | 2015-11-13 | 2017-06-01 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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