JPH01289170A - Non-volatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To contrive a reduction in the writing/erase repetition resistance of the title device and the improvement of the electrification hold characteristics of the device by a method wherein a first gate insulating film having a thin film part is formed continuously on a channel region and extending over the upper part of a drain region and a second gate insulating film is formed on a first electrode conductor which is laminated on this first gate insulating film and is set in a floating state in a potential manner. CONSTITUTION:The surface of a D type Si substrate 11 of a memory cell of a non-volatile semiconductor storage device is element-isolated by a field insulating film 12 in every cell region and source and drain regions 13 and 14 consisting of an n<+> diffused region are formed in the substrate surface at each cell region. Moreover, a gate oxide film 16 is continuously formed on part of a channel region 15 between the source and drain regions and extending over the upper part of the region 14, a tunnel insulating film 17 is formed on a part, which corresponds to the region 14, of the film 16, these films 16 and 17 are formed by thermally oxidizing the substrate 11 to contrive a stabilization and a floating gate 18 is formed on the film 16.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) This invention relates to a nonvolatile semiconductor memory device using nonvolatile transistors as memory cells, and particularly relates to a nonvolatile semiconductor memory device that uses nonvolatile transistors as memory cells, and particularly relates to a nonvolatile semiconductor memory device that uses nonvolatile transistors as memory cells. The present invention relates to a nonvolatile semiconductor memory device.

(Prior art) Figure 4 shows the ``IEE Journal of Solid State Circuits''.
Journal or 3olid 3tate
Circuits) vol. 5C-22No. 5
Oct.

1987), which shows the structure of a memory cell of a conventional non-volatile semiconductor memory device, and FIG.
) is a plan view, and FIG. 4(b) is a sectional view taken along line AA' in FIG. 4(a). In the figure, an n-type source region 42 and a drain region 43 are provided on the surface of a p-type substrate 41, and a part of the channel region 44 between the source and drain regions is formed by oxidizing the substrate. The end portion is connected to the drain region 1 through a gate insulating film 45 having a thickness of about 200.
A floating gate electrode 46 made of polycrystalline silicon is provided which overlaps i143. Furthermore, channel region 4
A control gate N-pole 47 made of polycrystalline silicon is provided on the substrate 41 and the floating gate electrode 46 through a gate insulating film obtained by oxidizing the surfaces of the substrate 41 and the floating gate electrode 46, respectively. In this way, a gate electrode structure in which a part of the ill Ill gate electrode covers the channel region is generally called an offset gate structure, and by adopting this structure, data is overerased during data erasing, resulting in depletion type. It is known that it is possible to prevent a plurality of cells from being simultaneously selected during data reading due to the existence of memory cells that have been selected.

Erasing data in a memory cell with such a structure requires l
1II III By biasing the gate electrode 47 to OV and the drain region 43 to a high voltage, electrons are extracted from the floating gate electrode 46 to the drain region 43 via the gate insulator 1I45 by a tunnel effect. At this time, since a tunnel current flows through the thick gate insulating film, the part where the current flows is weak 5po.
t, resulting in deterioration of charge (electron in this case) retention characteristic <retention> of the floating gate electrode 46 and deterioration of write/erase repetition endurance. Specifically, the memory cell shown in FIG. 4 has the following structural problems. One of them is that the electric field applied to the gate insulating film under the floating gate electrode during erasing largely depends on the shape of the floating gate electrode and the thickness of the gate insulating film.

When viewed at the LSI level, this means that the amount of charge handled from the floating gate 1-NI varies, and there is a margin in the structure itself that extracts electrons from the lower end of the floating gate N pole through the gate insulating film. There is no such thing. Second, since the shape of the gate insulating film under the floating gate electrode is flat, it is essential to reduce the illumination thickness of the gate insulating film in order to reduce the erase voltage in the future due to scaling, etc. However, on the one hand, this promotes deterioration of retention characteristics, and it can be said that the cell structure is unsuitable for high integration.

FIG. 5 shows the structure of a memory cell of a conventional non-volatile semiconductor memory, which is different from the above described in "Nikkei Microdevices, March 1986 issue, page 67. Figure (a) is a plan view, and Figure 5 (b) is the same figure (
A-A' cross-sectional view of a), Figure 5 (C) is a cross-sectional view of
-8' sectional view.

In this memory cell, in addition to the floating gate electrode 46 and control gate electrode 47, an erase gate electrode 48 made of polycrystalline silicon is newly provided, and a gate insulation 149 obtained by oxidizing the surface of the erase gate electrode 48 is provided. Erasing is performed by extracting electrons from the floating gate electrode 46 to the erase gate electrode 48 via the floating gate electrode 46.

However, in this case as well, due to the shape effect (edge effect) of the floating gate electrode 46 or the surface protrusion effect (asperity effect) on the upper surface of the erase gate electrode 48, the gate insulating film between the erase gate electrode 48 and the floating gate electrode 4G is 49
It is inevitable that variations will occur in the electric field applied to the This variation is worse than that of the memory cell shown in FIG. 4 above.

As a result, variations in threshold voltage occur during data erasing. If the degree of this variation becomes large, electrons will not be sufficiently extracted from the floating gate electrode during erasing, resulting in erroneous reading or destruction of the gate insulating film. Particularly in the latter case, electrons cannot be stored in the floating gate electrode, and the memory cell becomes a defective cell that is constantly in a conductive state. It goes without saying that even if this is not a fatal defect, the write/erase repeat durability and charge retention characteristics are easily deteriorated. Also, in the case of this memory cell, *ti
It is necessary to use a 3m polycrystalline silicon process,
There is a problem that the controllability of the process is very poor.

(Problem to be solved by the invention) In this way, in the conventional nonvolatile semiconductor memory device, writing/
There are problems such as a decrease in repeated erasing durability and a deterioration in charge retention characteristics, and it is an object of the present invention to provide a nonvolatile semiconductor memory device that can eliminate all of these problems and also allows for high integration of memory cells. With the goal.

[Structure of the Invention] (Means for Solving the Problems) A nonvolatile semiconductor memory device of the present invention includes source and drain regions provided on the surface of a semiconductor region, and the source and drain regions provided on the surface of a semiconductor region.
The layer is continuously laminated over the channel region provided between the drain regions, the channel region, and the drain m-ring, and is formed to have a film thickness thinner in a part corresponding to the drain region than in other parts. A first gate insulating film having an N film portion, a first electrode conductor stacked on the first gate insulating film and set in a potential floating state, and a first 2! It is characterized by comprising a second gate insulating film made of FaM on the polar conductor, and a second electrode conductor laminated on the second gate insulating film.

Further, the nonvolatile semiconductor memory device of the present invention has a second
The electrode conductor is provided so as to extend over the channel region through the second gate insulating film.

(Function) When erasing data, electrons are extracted from the first N-pole conductor to the drain region through the thin film portion of the first gate insulating film.

Furthermore, since the second electrode conductor is provided so as to extend over the channel region via the second gate insulating film,
Even if over-erasing occurs during data erasing, simultaneous selection of a plurality of cells can be prevented from occurring during data reading.

(Example) Hereinafter, the present invention will be described by way of an example with reference to the drawings.

FIG. 1 shows the configuration of a memory cell of a nonvolatile semiconductor memory device according to an embodiment of the present invention, and FIG.
) is a plan view of the pattern, FIG. 1(b) is a sectional view taken along line AA' in FIG. 1(a), and FIG.
'This is a cross-sectional view. In the figure, a p-type silicon substrate 11
The surface of the cell is isolated by a field insulating film 12 for each cell region. In each cell region, a source region 13 and a drain region 14 made of n-type diffusion regions are formed on the substrate surface. Furthermore, a gate oxide 1116 is continuously formed over a portion of the channel region 15 between the source and drain regions and over the drain 1l14.

Most of this gate oxide 11116 has a thickness of about 300 layers, but a portion corresponding to the drain region 14 has a tunnel insulation layer of about 90 layers.
It is set to l117. Note that this gate oxide film 16 and a part of the tunnel insulating film 17 are formed by thermally oxidizing the substrate 11, and are compared to an absolute n film obtained by oxidizing polycrystalline silicon or the like. The film quality is sufficiently stable.

A floating gate electrode 18 made of polycrystalline silicon is formed on the gate oxide 1!116. Furthermore, an i+IJ control gate electrode 20 made of polycrystalline silicon is formed in the remaining region of the channel region fi15 and on the floating gate electrode 18 with a gate insulating film 19 interposed therebetween. The gate insulator 1!119 is formed on the channel region so that its thickness is approximately 250 mm. Further, an interlayer insulation Il! is provided on the entire surface of the substrate including the control gate electrode 2o! I21 is deposited. A contact hole 22 communicating with the surface of the drain region 14 is opened in this interlayer RWA 21, and a wiring 23 made of aluminum is formed by patterning so as to fill this contact hole 22.

In the memory cell having such a configuration, the control electrode 20 is used as a word line, and the wiring 123 is used as a bit. Then, data writing is performed by setting the source region 13 to Ov, for example, and setting the tiIJIll gate electrode 19 to Ov, for example.
This is done by biasing the drain region 14 to, for example, 8V, respectively. At this time, hot electrons traveling through the channel region 15 are injected into the floating gate electrode 18 due to the channel hot electron effect. As a result, the @ value voltage of the memory cell in which the filling has been performed increases. The threshold (direct voltage) of a memory cell that is not subjected to this gate-on operation remains as low as before.

Therefore, when reading data, the source region 13 is, for example, OV
When the flJ lit gate N pole 19 is biased to, for example, 3V and the drain region 14 is biased to, for example, 3V, a memory cell that is not being written and has a low threshold voltage becomes conductive, and a current flows between its source and drain regions. flows. On the other hand, a memory cell in which writing has been performed and the IBl value voltage has increased becomes non-conductive, and no current flows between the source and drain regions. Therefore, when reading data, data is determined based on whether or not current flows between the source and drain regions.

Erasing data is carried out by placing the source region 13 in a potential floating state, biasing the control gate electrode 19 to, for example, OV, and biasing the drain region 14 to, for example, 20V. At this time, the capacitance between the control gate electrode 19 and the floating gate electrode 18, the capacitance between the floating gate electrode 18 and the drain region 14, and the floating gate 1! The potential of floating gate electrode 18 is set depending on the capacitive coupling state between pole 18 and channel region 15 due to '8ffi. and,
This potential becomes sufficiently lower than 20V, and the electric field between floating gate electrode 18 and drain region 14 becomes strong. As a result, electrons previously stored in the floating gate electrode 18 pass through the tunnel insulating film 17 of the gate oxide m16 to the drain fRbl.

Extracted at 14. As a result, the 11111 pressure of the memory cell in which data has been erased returns to its original low state.

By the way, the variation in electron extraction due to the shape of the floating gate electrode, which was a problem when erasing data in conventional memory cells, is due to the tunneling of the gate insulator M1G obtained by oxidizing a substrate with very good Ma property. Insulation I! 111
1, it can be significantly improved compared to the conventional method.

Furthermore, in the above embodiment, since the tunnel insulator 117 exists independently from the gate insulating film 16, the structure is advantageous for future reductions in erase voltage. That is, by keeping the thickness of the insulating film 16 constant, it can have a predetermined withstand voltage as a gate insulating film, and by changing the thickness of the tunnel insulating film 917, it can be made to correspond to various erase voltages. . Moreover, according to the above embodiment, by using the oxide film of the silicon substrate, which has high breakdown voltage and high controllability, the tunnel insulation 11 is
Variations in the electric field applied to the memory matrix 17 are extremely reduced within the memory matrix or within the wafer, and can be significantly improved compared to the conventional method. Furthermore, when erasing data, the electrons in the floating gate electrode 18 are extracted to the drain region 14 through the tunnel insulating film 17, so there is no need for an erase gate electrode as in the conventional memory cell shown in FIG. As a result, high integration of memory cells and simplification of processes can be achieved.

Next, a method for manufacturing a memory cell having the above structure is shown in FIG.
) to (f).

First, an impurity of the same conductivity type as the substrate for preventing field reversal is ion-implanted into a region M where a field oxide film is to be formed on a p-type silicon semiconductor substrate 11, and then a field insulating film is formed using the usual LOCO8 technique using selective oxidation. 12 is formed to separate the elements for each cell region (FIG. 2(a)).

Next, after forming an oxide film (not shown) on the surface of the substrate 11, an n-type diffusion region 31 is formed on the substrate surface by ordinary photolithography and ion implantation techniques, and a threshold layer is formed in the portion that will become the channel region. li1'I
An ion implantation region 32 for l pressure IIItl is formed. Thereafter, the previously formed oxide film is completely removed, and the substrate surface is oxidized again using an oxidation method to form an insulating film 33 with a thickness of about 300 on the entire surface (FIG. 2(b)).

Next, only the area where the tunnel insulating film is to be formed is covered with the above insulation wA.
33 is selectively removed to expose the substrate 11 in that area, and then a tunnel insulation vA17 with a thickness of 90 mm is formed on the substrate surface by low-temperature dilute oxidation.

Subsequently, a polycrystalline silicon film 34 is formed on the entire surface by low-temperature CVD (CVD).
After depositing on the entire surface by chemical vapor deposition method (D-Chemical vapor deposition method), impurities are diffused to lower the resistance (FIG. 2(C)).

Next, the polycrystalline silicon @34 is patterned using normal photolithography technology, and the floating gate electrode 1 is formed.
8 (Fig. 2(d)).

Subsequently, by selective etching using the floating gate electrode 18 as a mask, the insulating film 33 other than the floating gate electrode is removed.
After forming the gate insulating film 16 by removing the gate insulating film 16, heat treatment is performed in an oxidizing atmosphere to oxidize the surface of the substrate and the surface of the floating gate electrode, thereby forming a gate insulating film 11119. Thereafter, polycrystalline silicon is deposited on the entire surface by low-temperature CVD, impurities are diffused to lower the resistance, and then patterning is performed using photolithography to form the control gate electrode 20. Next, using the control gate electrode 20 as a mask, n-type impurity ions are implanted into the substrate in a self-aligned manner, and then diffused to form a source region 13 and a drain region 14 (see FIG. 2(e)).
)).

Subsequently, a glabellar insulating film 21 is deposited on the entire surface by CVD method,
This interlayer 1111 is created using photolithography technology.
A contact hole 22 is opened in 21, and then aluminum is deposited on the entire surface by, for example, sputtering, and this is patterned to form a contact hole 23 (see FIG. 2(f)).
)).

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above embodiment, the tunnel insulating film 17 is formed at a position other than the end of the floating gate electrode 18, but as shown in the cross-sectional view of another embodiment in FIG. The insulating film 11 may be formed at the end of the floating gate electrode 18.

In addition, we have explained the case where tunnel insulation 1i1117 is an oxide film obtained by thermally oxidizing a silicon substrate. The film may be composed of a so-called 0NOII film consisting of an oxide film/nitride film/il film.

Furthermore, in the above embodiment, the case where each of the floating gate electrode 18 and the control gate electrode 20 is made of polycrystalline silicon has been described, but this may be made of other wiring materials, such as ^^
Of course, a silicide such as MOS i or WSi made of a melting point metal and silicon, or a polycide film made of these silicides and polycrystalline silicon may be used.

[Effects of the Invention] As explained above, according to the present invention, a non-volatile semiconductor memory device is provided in which it is possible to lower the program/erase repetition resistance and improve the charge retention characteristics, and in which the memory cells can be highly integrated. can be provided.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a memory cell used in a device according to an embodiment of the present invention. FIG. 1(a) is a pattern plan view, and FIG. 1(b) and FIG. 1(C) are a pattern plan view. 2 is a sectional view showing the manufacturing process of the memory cell of the above embodiment, FIG. 3 is a sectional view of a memory cell according to another embodiment of the present invention, and FIG. 4 is a sectional view of a memory cell of a conventional device. FIG. 5 is a diagram showing the structure of a memory cell of a conventional device different from the above. DESCRIPTION OF SYMBOLS 11... P-type silicon substrate, 12... Field insulation layer, 13... Source region, 14... Drain f
IAy1.15...Channel area, IG, 19...
・Gate oxide film, 17... Tunnel insulating film, 18...
・Floating gate electrode, 20... Control gate electrode, 21.
...Interlayer insulating film, 22...Contact hole, 23.
··wiring. Applicant's agent Patent attorney Takehiko Suzue B' (a) (C) Figure 2 Figure 2 Figure jI3 Figure 4471

Claims (2)

[Claims] (1) A source and drain region provided on the surface of a semiconductor region, a channel region provided between the source and drain regions, and a layer continuously stacked over the channel region and the drain region, and A first gate insulating film having a thin film portion formed thinner in a part corresponding to the region than in other parts, and a first gate insulating film stacked on the first gate insulating film and set in a potential floating state. A first electrode conductor, a second gate insulating film laminated on the first electrode conductor, and a second electrode conductor laminated on the second gate insulating film. Non-volatile semiconductor memory device. (2) The nonvolatile semiconductor memory device according to claim 1, wherein the second electrode conductor is provided to extend above the channel region via the second gate insulating film.