JPH01287761A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make ID data nonvolatile and normally rewritable, and to prevent the ID data from being destroyed owing to malfunction by making a static RAM nonvolatile and adapting memory protection to a fixed data storage data area. CONSTITUTION:This device is equipped with the static RAM (SRAM) 4, a power source backup means 5 which backs up a power source when the normal power line to the SRAM is disconnected, an address decoder 3, and a write protection control circuit 7. Then the SRAM 4 is made nonvolatile by the backup means 5 and used while classified into a fixed data storage area 41 and a normal data storage area 42. Fixed data such as ID data which are made nonvolatile and memory-protected are stored in this fixed data in the fixed data storage area 42, normal data are read out and written in the normal data storage area 42. The need for a dedicated memory for fixed data storage is therefore eliminated. Consequently, the fixed data are held and normal writing is enabled.

Description

[Detailed Description of the Invention] [Summary] Regarding storage devices, while it is possible to make IDs used in car phones etc. non-volatile and to enable normal rewriting,
A static RAM that is divided into a fixed data storage area and a normal data storage area for the purpose of preventing D from being destroyed, and the static RAM.
a power supply backup means for backing up the power supply of M;
an address decoder that outputs a fixed address decode signal indicating writing to the fixed data storage area and a write control signal based on the write address to the static RAM; and a normal fixed address decode signal from the address decoder. and a write protection control circuit that stores the write data at a predetermined address of the fixed data storage area only when a normal write control signal is output, and makes the static RAM non-volatile and the fixed data Configure to perform memory protection of storage data area.

[Industrial application field]

The present invention relates to a semiconductor memory device, and in particular, it makes fixed data nonvolatile so that it does not disappear even when the power is cut off, and makes it rewritable as necessary.
The present invention relates to a semiconductor memory device that protects fixed data from being destroyed due to program runaway on the CPU side.

[Conventional technology]

For example, so-called ID (Tdenti-f
cation) The data is stored in memory as fixed data and used. These ID data need to be maintained even if the power is turned off. -On the other hand, once the ID data is set, it is not changed every day.
It may be changed as necessary. In this way, the ID data is preferably nonvolatile and stored in a rewritable memory.

Conventionally, ID data is stored in PROM, E” (Elect
Non-volatile memory such as ROM or static RAM (SRAM)
SRA that has been made non-volatile by providing power backup
I have M memorize it.

[Problem to be solved by the invention] When FROM is used, there is no problem in terms of non-volatility, but
10 When changing data, P) Remove the IOM from the car phone, etc., and change the data on the PRO? There is a problem in that the ID data cannot be easily changed while the device is being worn.

f! ``ROM is excellent in its non-volatility and ease of changing data, but it has the problem of being expensive.

When a non-volatile SRAM is used, the ease of changing non-volatile data is satisfied, but the ID data may be destroyed due to malfunction of the CPU due to external disturbances or the like. In other words, protection against malfunctions and the like is not provided.

Various types of memory protection are already known. In magnetic disks, magnetic drums, etc., writing is disabled by setting a switch or pin for each cylinder (for each track). However, this type of memory protection cannot be applied to semiconductor memories. A memory block in a semiconductor memory is a write-protected area in a certain area by a combination of a program and hardware. However, this method has a problem in that the memory protection function does not work if the program itself goes out of control.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention that solves the above problem.

The semiconductor memory device of the present invention is a static RAM (SR).
AM) 4. Consists of power backup means 5 for backing up the power when the normal power supply to the SRAM is cut off, an address decoder 3, and a write protection control circuit 7.

The SRAM 4 is made non-volatile by the power backup means 5.

The SRAM 4 is divided into a fixed data storage area 41 and a normal data storage area 42 for use. The fixed data storage area 41 stores fixed data such as ID data that should be made nonvolatile and memory protected. Normal data is successively written to the normal data storage area. Sharing SRAM 4 in this manner eliminates the need for dedicated memory for fixed data storage.

(Function) The address decoder 3 does not impose any restrictions on data succession commands from the CPU, etc. (not shown), and even when writing data, the address decoder 3 normally sets the write address WR to the data storage area. -An, the normal data address decode signal NDADD and the write control signal WRCNT are output.The write protection control circuit 7 outputs the normal data address decode signal NDADD and the write control signal WRCNT.
Write data R to write address WR-AD to RAM 4
-Enable DAT to be stored. - On the other hand, when writing data to a fixed data storage area, the CP
From U etc., data MP for canceling memory protection
r is output to the address decoder 3. The address decoder 3 decodes the memory protection release data MPr and outputs a signal for resetting the protect register in the write protection control circuit 7. The protect register is thereby reset and data writing to the fixed data storage area 41 is permitted. Next, this write address -R is used to write data from the CPU etc. to the fixed data storage area 41.
-AD is input to the address decoder 3, and the address decoder 3 outputs a fixed address decode signal FDADD. Write protection control circuit 7 receives fixed address decode signal F.
Depending on the reset state of DADD and protect register,
Data is written to the fixed data storage area 41 of the SRAM 4. When one data write is completed, the protect register is reset and the fixed data storage area 4
Prohibits writing data to 1.

Therefore, in order to further write data to the fixed data storage area 41, the CPU etc. outputs the memory protection release data MPr and then writes data to the fixed data storage area 41.
In this way, a data write request is made for each data item.
Data writing to the fixed data storage area 41 is a two-step operation, and memory protection is automatically restored once data writing is completed, so even if a program runaway occurs in the CPU, etc. Mere writing of data to the fixed data storage area 41 is prohibited, so the data within the fixed data area 41 is protected.

〔Example〕

FIG. 2 shows a control device used in a car telephone as an embodiment of the present invention.

In the figure, the control device includes a CPU 1, a program storage ROM 2, an address decoder 3, an SRAM 4,
The semiconductor memory device of the present invention is comprised of a power supply backup means 5, an I10 unit 6, and a write protection control circuit 7.

FIG. 3 shows a circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

In the figure, the address decoder 3 is the control decoder 3.
1 and an address decoder 32.

The address decoder 3 outputs a chip select (C3) signal for the ROM 2, an output enable (OE) signal, and a CS signal for the SRAM 4, but these circuits are omitted. The control decoder 31 has CP[
A write clock CKwm and a write control pulse CNTwm are output based on the clock CKCFO from I1 and the write control signal 5CNT. In addition, the control decoder 3
1 indicates that address 5ADR from CPU 1 indicates a fixed data storage area, and data 5DATA requests permission to write to the fixed data storage area;
Outputs protection release pulse RPRT. The address decoder 32 outputs a normal data address decode pulse NDADDP when the address 5ADR from the CPU 1 is within the normal data storage area, and outputs a fixed data address decode pulse FDAD when it is within the fixed data storage area.
In this embodiment, the SRAM d has the first
As shown in the figure, addresses are assigned in the order of normal data storage area 42 and fixed data storage area 42. Therefore, the address decoder 32 decodes only the normal data address decode pulse NDADDP in the case of an address in the normal data storage area 42, and the normal data address decode pulse NDADDP in the case of an address in the fixed data storage area 41. Fixed data address decode pulse FD
Outputs both ADDP pulses.

The write protection control circuit 7 is a D-type flip-flop (hereinafter referred to as
D-FF) 71, 72, NAND gate 73, AN
D gate 74, NANO gate 75 and inverter 7
6 are connected as shown. D-FF 71 is a memory protection control register, and D-FF 72 is its reset register. NAND gate 75 is SRAM
The chip enable terminal WE of No. 4 and the inverter 76 are connected to the chip enable terminal CE. SRAM 4
is CPU 1 to AT L, S5 ADR and data 5
Enter DATA.

The SRAM 4 is normally supplied with power via a power supply 10 and a diode 53. Further, when the power supply 10 is cut off, the SRAM 4 is supplied with power from the power supply backup means 5 consisting of a capacitor 51 and backflow prevention diodes 52 to 53, and is rendered non-volatile. When power is supplied from the power supply 10 and the diode 53, the capacitor 51 is charged via the diode 54.

Therefore, when the power supply 10 is cut off, the capacitor 51,
Power is backed up from the diode 52. S.R.A.
If M4 is used as CMO3 type SRAM, capacitor 5
1 can provide long-term power backup.

In addition to the illustrated example, the power supply backup means 5 may include replacing the capacitor 51 with a battery, omitting the diode 54,
Various measures can be taken, such as using a battery backup type.

The memory protect operation of the circuit shown in FIG. 3 will be described below.

FIGS. 4(a) to 4(i) show timing diagrams of normal data writing operations to the normal data storage area.

Writing to the normal data storage area 42 is performed at write address 5A.
Since only DR and write data 5DATA are output from the CPU 1, the output INH of the D-FF 71, which functions as a memory protect register, is at a high level, that is,
Data writing to the fixed data area 41 is prohibited (FIG. 4(a)). However, the address decoder 3 outputs a write control pulse CNT□ (FIG. 4(g)) and a normal data address decode pulse NDADDP (FIG. 4(b)). Fixed data address decode pulse FDA
Since DDP (Fig. 4(C)) is at low level and memory write inhibit pulse INH is at high level, NAND
Fixed data write enable pulse FDWR of gate 73
, are high level (FIG. 4(e)), so the NAND gate 75 outputs the write control pulse CNTw* (FIG. 4(g)).
), the write enable signal SWE (Fig. 4 (
h))) is low enabled. In addition, the inverter 76
Normal data address decode pulse NDADD via
The inverted pulse of P is used as the chip enable signal SCE.
Applied to RAM 4. As a result, data is written into the normal data storage area 42 of the SRAM 4.

After writing data, D-FF 71 via D-PF 72
is cleared, but in this case, there is no change since the D-FF 71 remains reset.

FIGS. 5(a) to 5(i) show timing diagrams of normal data writing operations to the fixed data storage area 41. FIG.

The CPU 1 outputs data for canceling write inhibition to the fixed data storage area 41 to the control decoder 31 of the address decoder 3 as write data 5DATA.

This causes the merotect release pulse RPRT to become D-PF.
71, and the memory write inhibit pulse INH of D-FF 71 becomes low level, that is, the write enable state (
5(d)), the CPU 1 then outputs a write address 5ADR and write data 5DATA with the fixed data storage area 41 as the address. Address decoder 3
2 outputs a normal data address decode pulse NDADDP and a fixed data address decode pulse FDADDP (FIGS. 5(b) and 5(c)). NANO gate 73
Since the output FDWR, remains at high level, AN
A write enable pulse WR is output from the D gate 74 (FIGS. 5(e) and 5(f)). As a result, the write enable signal SWE and the chip enable signal SCE become low enabled, and the fixed data area 4 of the SRAM 4 is enabled.
Data is written to 1.

After writing the above, clear pulse 5CLR from D-FF 72
is output, the D-FF 71 is reset, and the write inhibit pulse INH becomes high level (Fig. 5(i)(d))
.

When the write inhibit pulse INH becomes high level,
Next, the fixed data storage area 41 is written to the fixed data storage area 41 without outputting data for canceling write protection to the fixed data storage area 41.
Even if data is written to the file, the data will not be written.

The abnormal write operation will be described with reference to FIGS. 6(a) to (i). Normal data address decode pulse NDADDP
and fixed data address decode pulse FDADDP
At the time when is output, the write inhibit pulse INH should be at a low level as shown by the broken line in FIG. 6(d) under normal operation, but it is at a high level. Therefore, the output FDWRt of the NAND gate 73 becomes low level as shown by the solid line in FIG. 6(e). As a result, the write enable pulse W R
Since t is at a low level as shown by the solid line in Fig. 6(f), even if the write control pulse CNT□ is output (Fig. 6(f)
g)), the write enable signal SWE does not become low enable (FIG. 6(h)). Therefore, no data is written to the fixed data storage area 41.

In this way, since data cannot be written to the fixed data storage area 41 until after the write protection to the fixed data storage area 41 has been lifted, it is possible to write data to the normal data storage area 41 by mistake. If the fixed data storage area 41 should be written to, an address within the fixed data storage area 41 is specified, or a program runaway causes a write address to the fixed data storage area 41, the fixed data storage area 41 No data is written to.

7(a) to (i), when writing data to the normal data storage area 42, the fixed data storage area 42
The figure shows an operation timing diagram when data is output to release the write prohibition to Although the data address decode pulse NDADDP is output, (Fig. 7(b)
)), fixed data address decode pulse FDADDP
is not output (FIG. 7(C)). Therefore, the output FDWRE of the NAND gate 73 remains at high level (
FIG. 7(e)), and a write enable pulse WR is output (FIG. 7(f)). Therefore, even if the write enable signal swE becomes low enable (FIG. 7(h)) and the write prohibition is canceled, data is written to the normal data storage area 42. - On the other hand, the D-FF 71 is reset after data writing. Therefore, even if there is a subsequent request to write data to the fixed data storage area 41 without releasing the write protection, it will not be executed.

〔Effect of the invention〕

As described above, according to the present invention, with a simple circuit configuration, fixed data can be retained (non-volatility) even when the power is turned off, and while memory protection is applied against abnormal operation, the fixed data can be maintained during normal operation. enable change.

In addition, in the present invention, since SRAM is shared for fixed data storage and normal data storage, the cost is low and space can be saved, and fixed data can be written at the same speed as normal data. can.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a semiconductor memory device of the present invention, FIG. 2 is a control circuit diagram of an embodiment of the present invention, FIG. 3 is a circuit diagram of a semiconductor memory device of an embodiment of the present invention, and FIG. a)-(i)--FIGS. 7(a)-(i) are operation timing diagrams of the circuit of FIG. 3. (Explanation of symbols) l...CPU. 2...Program ROM. 3... Address decoder, 4... Static RAM. 5... Power backup means, 6... I10 unit, 7... Write protection control circuit.

Claims (1)

[Claims] 1. Static RAM (41) and regular data storage area (42) that are used separately.
4), a power backup means (5) for backing up the power of the static RAM, and a write address (WR-AD) for the static RAM.
), an address decoder (3) outputs a fixed address decode signal (FDADD) indicating writing to the fixed data storage area and a write control signal (WRCNT).
), and write protection that stores write data (WR-DAT) at a predetermined address in the fixed data storage area only when a normal fixed address decode signal and a normal write control signal are output from the address decoder. a control circuit (7) to make the static RAM non-volatile;
A storage device, characterized in that the storage device is configured to perform memory protection of the fixed data storage data area.