JPH01286063A - Data transmitting system - Google Patents

Abstract

PURPOSE:To enhance data transmitting efficiency between a processor and a prescribed device by including the bank designating information of an address in an address setting instruction. CONSTITUTION:Data from a CPU 10 are serially transmitted through a serial interface circuit 20 to plural devices 11, 12, 13.... At the time of a transmission, after the sending of an address setting instruction, by sending the address data, the address is set, and the data corresponding to the set address are transmitted. The information to designate the plural banks are included in the address setting instruction, and by the address setting instruction attached with the bank designating information and the address data to be next sent, the address in the designated bank is designated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transmission method for transmitting data from a data processing processor (CPU) to various devices.
In particular, the present invention relates to a data transmission method that can improve data transmission efficiency from a processor to a device.

[Summary of the invention]

When transmitting data from a data processing processor to various devices, the present invention sets a real address by sending address data after sending an address setting command, and transmits data corresponding to the set address. In the data transmission method, by including address bank specification information in the address setting command, data transmission by specifying the bank and address can be realized with a small number of transmissions,
This improves the efficiency of data transmission between the processor and a predetermined device.

[Conventional technology]

In recent years, so-called microprocessors have come to be used for various purposes, and there is a need for data transmission between various devices. Data transmission methods between the microprocessor and various devices can be roughly divided into parallel transmission and serial transmission. Among these, serial transmission has the advantage of requiring less wiring, and is used for data transmission to multiple controlled devices, for example, in system control of various electronic devices. There is.

FIG. 3 is a block circuit diagram for explaining a conventional example of serial data transmission between a CPU (processor) and various devices. In FIG. 3, for example, an 8-bit microprocessor is used as the CPU 51, and the data and data of this CPU 51 are
The bus DB, address bus AB and control bus CB contain so-called ROM (read only memory) 52, RAM (Random Access Memo January 5
3. A PIO (parallel interface) circuit 54 and a 310 (serial interface) circuit 55 are connected. The data input/output terminal of this SIO circuit 55 is connected to a plurality of serially controlled devices, such as AD/
DA converter 61, DSP (digital signal processor)
62, . . . are commonly connected. In order to alternatively specify these various devices 61, 62, . . . , for example, the address bus AB and the control bus
An address decoder 56 connected to bus CB is used. This is a so-called memory Matsubuto ■0 configuration, and each ■0 device can be specified from the CPU 51 in a form similar to normal memory access, and the commands can be unified or simplified, and the software can It's advantageous.

Here, in addition to the addresses set for each device described above, addresses corresponding to several functions within one device may be set0. For example, AD / When assuming the volume value adjustment function of the DA converter, as the address increases by 1 from the predetermined address ADO, the left channel recording volume adjustment, right channel recording volume adjustment, left channel playback volume adjustment, right channel playback volume It is conceivable that functions such as adjustment, etc. are set, and the respective adjustment data etc. can be transmitted by specifying these function addresses. In this case, it is necessary to send address data to the device in order to specify the functional address, but it is necessary to send an address setting command prior to transmitting this address data. This address setting command is a command to import the next data to be sent into the device as the above functional address data, but if the bit length of this functional address is longer than the word length of the transmission data,
It is necessary to send m*address data divided into, for example, an upper part and a lower part, and an address setting command must be sent for each of these parts. That is, for example, first, an upper address setting command is sent, and then the upper part of the address is It is necessary to send data, then send a lower address setting command to send lower address data, and then send data corresponding to the functional address consisting of upper and lower data of these addresses. Sending address setting commands for each part of the address in this way is troublesome and results in a reduction in data transmission speed.

For example, even if the word length of the transmission data is 8 bits and the word length of the address is 10 bits, the data must be sent separately into an 8-bit upper address and a lower address, and the 8 bits of the upper address must be sent separately. As for the bits, only the lower two bits are valid, resulting in poor data efficiency.

The present invention has been made in view of the above circumstances, and enables high-speed serial data transmission with a simple configuration, especially when the read address length is longer than the data length that can be serially transmitted at one time. An object of the present invention is to provide a data transmission method that can improve transmission efficiency when transmitting data by specifying such an address.

[Means to solve the problem]

In order to solve the above problems, a data transmission method according to the present invention sends an address setting command when transmitting data corresponding to a predetermined address from a data processing processor to at least one device. address later
In a data transmission method in which a rear address is set by sending data and data corresponding to the set address is transmitted, the address space is divided into a plurality of banks, and the address space is divided into a plurality of banks during the address setting command. The address setting command with this bank specification information and the next address/
This method is characterized by specifying an address within a specified bank using data.

[For production]

Since the information for specifying the multiple banks is included in the above address setting command, address specification can be performed by specifying a bank by simply sending the next address data. For example, specifying the upper address data It saves you the trouble of sending it.

〔Example〕

FIG. 1 is a block circuit diagram schematically showing a circuit configuration used in an embodiment of the data transmission method according to the present invention.

In FIG. 1, for example, a CPU10 consisting of a so-called 8-bit microprocessor has a write control signal WR1, a successive control signal RD, and a memory access request signal M.
REQ, data/command instruction signal D/C116-bit address AO-A15 output terminal, and 8-bit address
At least input/output terminals for data DO to D7 are provided. The data (including address data) from this CPU10 is sent to multiple devices 11, 12, 13, . . . via the serial interface (SIO) circuit 2o.
Serial transmission to...

This SIO (serial interface) circuit 20 mainly includes a shift register 21 for converting parallel input data from the CPυ 10 into serial data, and the plurality of devices 11, 12,
An address decoder 22 for detecting the address assigned to . and the above 3-state buffer 2
3 and a serial control circuit 24 that controls the operation of the shift register 21. Such a serial interface circuit 20 is connected to the CPU10.
The 16-bit addresses ^0 to ^15 and 8-bit data DO to 07 from A bit R/W, a data/command status bit D/C, and a start bit ST for serial transmission are added, and serial transmission is performed under the format shown in FIG.

That is, in the serial transmission data format shown in FIG. 2A, starting from the beginning of the serial data string,
Start bit ST, data/command status bit D/C1 successive/write status bit R/W
and margin bits MG for read/write switching are arranged, and further 8-bit data to be transmitted (8-bit data DOND7 from CPUIO, etc.) is arranged. This serial data string is serially transmitted in order from the start bit ST in accordance with the serial transmission lock.

Here, the successive/write status bit R/W in the format of FIG. The above data/command status bit D/C is obtained by
Obtained from 0.

Further, the start bit ST is constantly supplied from the terminal 26.

The content of the part in the above format where 8-bit data is arranged can be either normal data or address as information to be processed, or command data as control information to control the information. However, the status bit D/C differs depending on the contents of this part. This status bit D/C is similar to the binary signal S indicating a transmission request from a terminal disclosed in, for example, Japanese Patent Laid-Open No. 60-187157, and in the technology described in this publication, the signal S In this embodiment, when the status bit D/C indicates data D,
In the 8-bit data portion to be transmitted in the above format, 8-bit data or an 8-bit address to be processed is placed. Also the status
When bit D/C indicates command C, the device code is placed in the upper 4 bits of the 8-bit data part in the above format, and the lower 4 bits are placed in the lower 4 bits, as shown in FIG. 2B, for example. Instruction code is placed.

Here, the above 4-bit device code can be considered as a type of address for specifying any of the above devices 11, 12, etc., and for example, the correspondence shown in Table 1 is used. It can be a relationship.

Table 1 This Table 1 shows an example in which the correspondence between device codes and devices is one-to-one. However, by making each code of multiple devices common, one device code can It may also be possible to specify a device.

Next, the above 4-bit instruction code is C
This represents commands sent from PUI O to devices 11, 12, . . . , and specific examples thereof are shown in Table 2.

Table 2 In this Table 2, address H or address L indicates an instruction for setting, for example, the upper 8 bits or lower 8 bits of a 16-bit address.
After this instruction code is transmitted, the contents of the 8-bit data portion in the serial data transmitted from CPU10 to devices 11112, . . . become the upper 8-bit address or the lower 8-bit address. Note that depending on the purpose, type of device, etc., only the lower 8-bit address may be sufficient.

Also, increment and decrement in Table 2 are as follows:
This indicates an instruction for automatically increasing or decreasing an address by 1, and "hold" is an instruction for stopping the increase or decrease of an address due to the above-mentioned increment or decrement instruction.

Furthermore, as a main part of the present invention, banks A to D in Table 2 refer to banks A to D corresponding to four memory areas distinguished by the upper two bits in the memory space of a 10-bit address, for example. This shows an instruction to specify one of D and to set a rear address using lower address data (8 bits) sent next. In other words, the 10-bit address space is expressed in hexadecimal numbers from 000H to 3.
When expressed as FFH, bank A is 000H to 0FFH.

Bank B is 100H to IFF) (, Bank C is 200H
~2FFH and bank D correspond to 300H to 3FFH, respectively. For example, in order to specify the address of 270H, it is sufficient to send 70H as an 8-bit address after sending the bank C command.

Next, the address decoder 22 in the serial interface circuit 20 of FIG. 1 receives the write control signal WR and memory request signal MR from the CPU10.
EQ, successive control signal RD and 16-bit address AO
~A15 are supplied, and based on these signals,
Access requests (memory requests) to addresses assigned to each of the above devices 11, 12,...
When this is done, a predetermined serial transmission start signal or trigger signal is sent to the serial control circuit 24. The serial control circuit 24 is supplied with a mask clock synchronized with, for example, a reference operating clock of the CPU I O through a terminal 27. The serial control circuit 24 outputs a predetermined number of pulses of this mask clock as a serial transmission lock in response to the input of the trigger signal, and supplies the mask clock to the shift register 21 and, if necessary, to the clock supply line ICE. Each of the above devices 11.
12, . . . are respectively supplied to clock input terminals.

This serial transmission lock can also be omitted.

Serial transmission data from shift register 21 is 3
Serial transmission line X via state buffer 23
St, each of the above devices 11, I2,...
serial data input terminal. In the example shown in FIG. 1, bidirectional serial transmission lines l and i are assumed, and serial data from each device 11, 12, . . . is also transmitted through the transmission line! 8. However, separate serial transmission lines may be provided for data transmission and data reception.

Next, the so-called DSP (digital signal processor)
and devices such as AD/DA converters 11.12,...
The internal structure of is explained.

A shift register 31 for converting the serial transmission data from the 310 circuit 20 into parallel data is provided in an arbitrary device, for example, the device 11 in FIG. The 8-bit data portion of the data is supplied to a command decoder 32, an address counter 33, and a data buffer 34, respectively. The functional address for this device 11 has a total of 10 bits, and the address counter 33 is divided into upper 2 bits and lower 8 bits. The upper two bits of the address in this case are information specifying one of the four banks A to D.

Here, the command decoder 32 inputs the shift register 3
The above status bit D in the data string supplied to
/C interprets the command for data (command data) indicating C (command) and controls the operation of each part according to the interpreted command. For example, the status bit D/C C (command) and the instruction code indicates the above "0001" (address L), the command decoder 32 will determine when the data is sent in the next serial transfer, that is, when the status bit D/C is When D (data) is indicated, an address load signal is output.

This address load signal is sent to the address counter 33.
The 8-bit data inputted to the load terminal LD of the address counter 33, serially transferred, and converted into parallel data by the shift register 8 is loaded into the lower side of the address counter 33 as address lower data.

Then, when the original data is sent, that is, when the status bit D/C indicates D (data), the command decoder 32 sends a load signal to the load terminal LD of the data buffer 34, The sent data (8 bits) is taken into this data buffer 34 as the data at the address.

Further, if the instruction code in the command is an address setting instruction with the bank specification information (for example, the bank C), the command decoder 32 sends a load signal to the load terminal LD of the upper address register 39. The upper address (equivalent to 2 bits) obtained by encoding, for example, the lower 2 bits of the instruction code with the upper address encoder 38 is taken in. This upper address encoder 38 is for obtaining an upper address (equivalent to 2 bits) for specifying each bank based on the instruction code of banks A to D in Table 2 above. In the specific example shown in Table 2, attention is paid to the fact that the lower two bits of the instruction codes of banks A to D are different from each other, and the conversion as shown in Table 3 is performed.

After the address setting command with bank specification information is sent, 8-bit address data for specifying an 8-bit address within the specified bank is sent (the status bit D/C becomes D). is serially transmitted, the command decoder 32 sends an address load signal to the address counter 33, and for the upper address, the 2-bit load signal from the upper address register 39 is sent.
data to shift register 3 for lower addresses.
It is controlled so that 8-bit data from 1 to 1 is taken into each address counter 33. In addition, each code of the address setting command of the above bank specification information material is "1000" for bank A, "1001" for bank B, and "1001" for bank C.
By setting in advance so that "1010" is "1010" and "1011" is "1011" for bank D, the lower two bits can be used as is as the upper address for specifying the bank, and the above upper address encoder can be omitted. I can do it.

Next, the upper 4 bits (corresponding to the above device code) from the command decoder 32 are sent to a 4-bit comparator 35, where they are compared with the 4-bit device code setting data from the terminal 36, and the comparison output is is sent to the command decoder 32. Here, the 4-bit device code data supplied to the terminal 36 can be transmitted, for example, by operating a so-called DIP switch or by other C.
It can be set arbitrarily under control from the PU. The terminal 36 of the device 11 has, for example, “0”.
000" setting data is supplied. Therefore, only when the device code in the 8-bit command from the CPU10 is "000", this device 11
A match signal is outputted from the comparator 35 in the controller and sent to the command decoder 32, etc., so that the content interpretation operation of the instruction code, etc., is executed. During the content interpretation operation of this instruction code, in the case of an instruction that controls address change, such as increment, decrement, etc. in Table 2, a signal is sent from the command decoder 32 to the address change control circuit 37, The address change control circuit 37 controls the counting operation of the address counter 33 to increment and decrement the address value flI.

Next, the output from the address counter 33 is sent to the address bus in the device 11, where various function selection operations such as setting the left and right channel volume values are performed, and the output from the data buffer 34 The value for the selected function is set.

In the above configuration, when transmitting 8-bit data to the device 11 by specifying a desired 10-bit address (an 8-bit address from any of the four banks mentioned above) from the CPUIO side, for example, , address 27
Data 04H in 0H (H indicates hexadecimal number)
The operation when transmitting is explained.

In this case, since the value of the upper 2 bits is 2, it is necessary to specify bank C (200H to 2FFH), so the bank C setting command in the infrastructure run code in Table 2 above is used. ).In other words, ■Bank C (address setting command with bank specification) ■Addressed data (701() ■Data (04H) By performing three serial transmissions, specify address 270H and set the data. 04H can be sent.

On the other hand, there is also a method of specifying the rear address using Address H and Address L, which are address setting commands in Table 2, and transmitting data, but in this method, ■Address H (address setting command) ■Address Five serial transmissions are required: setting command (02H) ■address L (address setting command) ■addressed data (70H) ■data (04H).

Therefore, according to the method of the embodiment of the present invention, the number of serial transmissions is reduced by two times compared to the conventional data transmission method using an address setting command, and data transmission can be made faster or more efficient.

In addition, the control information (so-called commands) uses, for example, an arrangement of device codes and infrastructure code of 4 bits each.
There is no need to send them separately, making it possible to increase speed by serially transmitting them, and since the device code and instruction code are separated, the same instruction code can be sent to many devices at high speed by changing the device code. becomes possible. In this case, by sharing the device code on the slave side, commands can be sent to many devices at the same time.

Furthermore, by setting the above automatic address change IIJm mode such as incrementing and decrementing, it is possible to easily perform so-called block transfer of data corresponding to consecutive addresses without incrementing or decrementing each time by software. .

Note that the present invention is not limited to the above-described example, and, for example, the number of bits of the data and address of the CPU, the number of banks, etc. can be set arbitrarily. In addition, by combining the address setting command in the bank specification line with the address change control command such as the increment/decrement command described above, after specifying the bank and sending the lower address data and the data corresponding to the address, data can be sent one after another. It is also easily possible to have the data stored in the device as data corresponding to an incremented address each time the data is sent. In addition, various modifications can be made without departing from the gist of the present invention.

〔Effect of the invention〕

According to the data transmission method of the present invention, after sending out an address setting command with bank designation information, the processor continuously transmits address lower data and original data, thereby changing these banks and lower addresses. Specified data transmission can be achieved with fewer transmissions than before, and data transmission efficiency can be improved. Moreover, since the sequence processing that was conventionally performed by software on the processor side is processed by hardware on the device side, the burden on the software can be reduced and the processing speed can be increased.

Next, according to the embodiment of the present invention, when the data string to be serially transmitted is code data indicating the control information (command information), it includes a device code and an instruction code. , it is possible to send the same command at high speed with one serial transmission without having to send it separately, and the same command can be sent to many devices at high speed by changing the device code without changing the instruction. By sharing the device code, instructions can be sent to many devices at the same time.

Furthermore, by using the address 1M control information (instructional codes such as increment and decrement mentioned above) that automatically changes the address, the address can be changed on the slave device side by simply sending a group of data corresponding to a series of addresses in sequence. Changes are automatically controlled (incrementing, decrementing, etc.), and so-called block transfer of data can be realized without incrementing or decrementing each time by software, thereby increasing the speed of data transmission.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram schematically showing a circuit configuration used in an embodiment of the data transmission method according to the present invention, FIG. 2 is a diagram showing a serial data transmission format in the embodiment, and FIG. 1 is a block circuit diagram for explaining a conventional example. lO...CPU (processor) 11.12,... Controlled device 20...
Serial interface circuit 21...Shift register 22...Address decoder 24...Serial control circuit 31...Shift register 32...Command decoder 33...Address counter 34... Data buffer 38... Upper address encoder 39... Upper address register

Claims (1)

[Claims] When transmitting data corresponding to a predetermined address from a data processing processor to at least one device, a real address is set by sending address data after sending an address setting command. In a data transmission method that transmits data corresponding to the set address, the address space is divided into a plurality of banks, and bank specification information specifying one of the plurality of banks is included in the address setting command. and specifying an address within a specified bank by the address setting command with the bank specification information and the address data sent next.