JPH01286033A - Information processor - Google Patents

Abstract

PURPOSE:To arithmetic performance by properly using the computing element of a pipeline constitution to operate while an arithmetic intermediate result is held at a special time interval and the computing element of the non-pipeline constitution of the same function as it, by an instruction. CONSTITUTION:Computing elements 4 and 5 are of the non-pipeline constitution and the pipeline constitution of the same function respectively, operated data registers 41a and 41b and an arithmetic result register 42 are provided at a computing element 4 and operated data registers 51a and 51b, an arithmetic result register 52 and a pipeline register 53 are provided at a computing element 5. The computing element 5 holds an intermediate result at a fundamental machine cycle or a plural-fold time interval, the instruction of a main storing part 1 is supplied to an instruction control part 2, the operated data are supplied to a general-purpose register 3 respectively, and by the signal from the control part 2, a selector 6 selects either one of the results of the computing elements 4 and 5 and sends it to the register 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention provides an instruction control section that decodes instructions and controls the activation of instructions while managing the state of resources, and a method for executing instructions using control signals from the instruction control section. The present invention relates to an information processing device including an instruction execution unit that executes instructions.

[Conventional technology]

Conventionally, in this type of information processing device, an arithmetic unit of an instruction execution unit includes an operand data register that holds operand data;
It consisted of an arithmetic logic section that realized arithmetic functions and an arithmetic result register that held the arithmetic results.

In the case of this arithmetic unit, the same arithmetic unit cannot be used after the operand data is set in the operand data register for operation until the operation result is set in the operation result register (this time is called a computation cycle)
.

Therefore, in other information processing arithmetic units, multiple stages of registers that hold the intermediate results of calculations are inserted in the middle of the arithmetic logic section, and the intermediate results of the calculations are stored in the intermediate result holding registers of the next stage of the operand data register. The calculation cycle is shortened by using a so-called pipeline configuration so that the next calculation can be activated for the calculation unit at the timing when the result is held.

(Problem to be Solved by the Invention) In the former of the above-mentioned conventional information processing devices, the arithmetic units do not have a pipeline configuration, so when instructions that use the same arithmetic unit are consecutive, the processor There is a drawback that the instruction processing efficiency is reduced due to the usage limit of nN. This tendency becomes more noticeable when the instruction processing section is pipelined to shorten the machine cycle in order to improve the processing efficiency of the device.

In order to solve the above problems, the latter information processing i! I! On the other hand, the device has the following drawbacks.

In general, the flip 70 blocks constituting a register have a delay as a circuit. Therefore, if a register is inserted in the middle of the circuit in order to pipe or line the arithmetic unit, the pipelined arithmetic unit will be able to set the operand data and then display the operation result. It will take longer to confirm. Furthermore, when inserting a register to pipeline arithmetic units, it is efficient to insert the register at a position that is an integral multiple of the machine cycle in terms of circuit delay time, but this is not always possible due to the circuit configuration. However, it may not always be possible to place it at the optimal position, and this also increases the calculation time.

(Means for Solving the Problems) In the information processing device of the present invention, the instruction execution unit is a pipeline system that advances arithmetic processing while holding intermediate results of arithmetic operations at intervals of a basic machine cycle or multiple times the cycle. It has an arithmetic unit with the same configuration as the arithmetic unit, and an arithmetic unit with a non-pipelined configuration that realizes the same l111 as the arithmetic unit, and has an instruction for specifying and using the arithmetic unit for each arithmetic unit, and an instruction control unit. Control is performed to selectively use the arithmetic units according to instructions.

[Effect]

An arithmetic unit with a pipelined structure that has two types of arithmetic units in the instruction execution section, one with a pipelined configuration and one without a pipelined configuration, that perform the same function, and which can be used depending on the instruction.The arithmetic unit has a shorter operation cycle. It becomes possible to flexibly select the characteristics of the non-pipelined operation *i such as short calculation time, and the calculation performance of the fruiting device can be improved.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing essential parts of an embodiment of an information processing apparatus of the present invention.

A main memory section 1 in which instructions and data are stored supplies instructions to an instruction control section 2 and operand data to a general-purpose register 3. The instruction control unit 2 receives an instruction from the main storage unit 1, decodes it, and creates control signals necessary for executing the instruction. The general-purpose register 3 stores operand data from the main memory 1 and the arithmetic unit 4.5.
Temporarily stores the calculation results from. The arithmetic units 4 and 5 have the same functions, but the arithmetic unit 4 is a non-pipelined arithmetic unit, and the arithmetic unit 5 is a pipelined arithmetic unit. The arithmetic unit 4 has operand data registers 41a and 41b.
, an operation result register 42, and the operation unit 5 is an operation data register 518.51b.

Pipeline register 53 that temporarily holds calculation intermediate results
, an operation result register 52, and the operation unit 5 holds the operated data until the operation result is determined in operation 14, and until the operation intermediate result reaches the register at the next stage. The two-manpower selector 6 selects either one of the calculation results of the calculation unit 4.5 based on the control signal from the instruction control unit 2, and sends it to the general-purpose register 3.

Next, the operation of this embodiment will be explained.

The instruction 11tl11 section 2 takes out an instruction from the main storage section 1 and decodes it. If the instruction is a type of instruction that uses pipeline operation 85, the instruction control unit 2 reads necessary operand data (the data is read from the main storage unit 1 and stored in the general-purpose register 3 prior to the instruction). ) is issued to the general-purpose register 3 via the control line 21, and the arithmetic unit 5 is instructed via the control line 23 to set the data in the operand data registers 51a, 51b and start the operation. Send. After the instruction control unit 2 circulates the calculation start signal corresponding to the number of pipeline stages of the calculation units, it instructs the selection B 6 from the 1lJIj line 24 to select the calculation result from the calculation unit 5 and send it to the general-purpose register 3.

Furthermore, if the instruction decoded by the instruction liI control unit 2 is an instruction that uses the non-pipelined arithmetic unit 4, the necessary operand data is read from the general-purpose register 3 as described above, and the data is stored in the operand data register 418. Set it to 41b,
The control line 22 controls the start of the calculation, and after the time required for the calculation has elapsed, the selector 6 is controlled to select the performance result of the W performer 4 using the control line 24 and send it to the general-purpose register 3.

Note that in this embodiment, only pipeline and non-pipeline configuration arithmetic units for arithmetic operations of one function are illustrated;
It goes without saying that similar structures are used for multiple arithmetic functions.

〔Effect of the invention〕

As explained above, the present invention has two types of arithmetic units in the instruction execution unit, one with a pipeline configuration and the other with a non-pipeline configuration, each of which performs the same function, and allows both types to be used depending on the instruction. It is possible to flexibly select the characteristics of a pipeline-configured arithmetic unit such as high cycle length and the characteristic of a non-pipeline-configured arithmetic unit such as short calculation time, and improve the crushing performance of the condensed foot. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of essential parts of an embodiment of an information processing apparatus of the present invention. DESCRIPTION OF SYMBOLS 1...Main storage unit, 2...Instruction control unit, 3...General-purpose register, 4...Non-pipelined arithmetic unit, 5...Pipeline arithmetic unit, 6...Selector.

Claims (1)

[Scope of Claims] An information processing device that includes an instruction control unit that decodes instructions and controls activation of instructions while managing the state of resources, and an instruction execution unit that executes instructions in accordance with control signals from the instruction control unit. In the above, the instruction execution unit is a pipeline-configured arithmetic unit that carries out arithmetic processing while holding arithmetic intermediate results at time intervals of a basic machine cycle or multiple times the cycle, and realizes the same function as the arithmetic unit. an arithmetic unit with a non-pipelined configuration, each arithmetic unit having an instruction to specify and use the arithmetic unit, and an instruction control unit controlling the use of the arithmetic unit according to the instruction. Information processing device.