JPH01281752A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent initial failure due to deterioration of gate breakdown strength by forming an opening with a resist pattern, thereby forming a metallic silicide film after introducing N<+>-type impurities. CONSTITUTION:A resist pattern 12 is formed so as to remove a connecting part between a substrate 1 and a gate metal. Polycrystalline silicon 4 and a gate oxide film 2 are etched continuously by using the resist pattern 12 as a mask. Then, the resist pattern is removed and N<+>-type impurities are introduced by diffusing thermally or by driving As, P, and the like with ions into polycrystalline silicon 4. In such a case, an N-type impurity layer 6 is formed on the substrate surface of an opening 9. Then, a metallic silicide film 5 is formed and a wiring layer consisting of only the metallic silicide layer 5 is constructed in the opening 9 and its layer is connected to the first wiring layer. And then, its layer is connected to a diffusion layer 6 which is formed directly on the substrate 1. Thus, initial failure due to deterioration of gate breakdown strength is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and particularly to a method for manufacturing a semiconductor device characterized by having a gate metal having a two-layer structure of polycrystalline silicon and metal or metal silicide.

[Conventional technology]

The structure and manufacturing process of a conventional semiconductor device will be explained using figures.

In Figure 3, which shows a conventional structure, l is a semiconductor substrate;
2 is a gate insulating film, 3 is an element isolation insulating film, 4 is polycrystalline silicon forming the first wiring layer, 5 is the same (metal or metal silicide film forming the first wiring layer, 6 is the first wiring layer) A diffusion layer under the connection portion between the wiring and the substrate, 7 a sidewall of the LDD structure, and 8 a source or drain diffusion layer.

FIG. 4 shows a plan view of a conventional structure. In FIG. 4, 9 is an opening for connection between the gate electrode and the substrate, IO is an active region, and 11 is a first wiring layer. In the conventional structure, the gate electrode made of the first wiring layer and the substrate are in direct contact with each other. The degree of freedom is increased compared to the type connected by , and the area of this part can be reduced, making it suitable for miniaturization and high integration.

Furthermore, FIGS. 5(a) to 5(e) are diagrams showing a method of manufacturing a conventional structure. Figure 5(a) shows that the element is 1J in the conventional method.
111i3 and gate insulating film 2 have been formed.
In FIG. 5(b), a resist pattern 12 is formed and the required portion 9 of the gate insulating film is removed.

Furthermore, in FIG. 5(C), polycrystalline silicon 4 of the first wiring layer which also serves as the gate electrode has been formed. At this time, inside the opening 9, the substrate surface is oxidized due to chemical treatment for resist peeling, and unless this is removed, contact between the polycrystalline silicon and the substrate cannot be established. After introducing impurities, a metal or metal silicide film is formed, and FIG. 5(e) shows that the first wiring layer is etched, leaving only the necessary portion. The sidewalls were formed using the conventional method and the source/drain diffusion layers were formed as shown in FIG.

[Problems to be Solved by the Invention] Problems with the semiconductor device having the conventional structure as described above include the following points.

As mentioned in the description of the prior art, before forming polycrystalline silicon as shown in FIG.
Wet or dry etching must be performed to remove the thin oxide film formed on the surface by chemical treatment or water washing.

This etching process also etched the G a T e Ba 2 portion, which not only increased the number of initial failures due to deterioration of dielectric strength voltage, but also caused problems such as dielectric breakdown over time, so-called TDDB, and poor reliability.

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned problems.

[Means for Solving the Problems 1] The present invention includes a step of forming a first insulating film serving as an element isolation insulating film on a semiconductor substrate, and a second step! ! a step of forming a film, a step of forming a polycrystalline silicon layer, a step of forming a first resist pattern for opening a predetermined portion, a step of removing the polycrystalline silicon, and a step of the second insulating film. a step of removing the first resist pattern; a step of introducing impurities; a step of forming a metal or metal silicide film; and a step of forming a gate electrode or wiring pattern. This is a method of manufacturing a semiconductor device, further comprising a step of introducing the impurity after forming the polycrystalline silicon layer.

[Example] An example in which an example of the present invention is applied to an N-channel region will be described.

FIG. 1(a) to FIG. 1(f) are explanatory diagrams of the manufacturing method of the present invention.

In the plan views, the same reference numerals as those in FIGS. 2 and 3 indicate the same or corresponding parts.

(1) Figure 1 (a) shows the state in which an element isolation insulating film 3 and a gate oxide film 2 are formed on a P-region l formed on a P-type plate or substrate using a conventional technique. In this example, the element isolation insulating film 3 is formed using the LOCO3 method, but the manufacturing method of the present invention can also be applied to a trench method in which a recess is formed in the substrate 1 and filled with an insulator.

(2) Next, as shown in Figure 1 (b), polycrystalline silicon 4
form. At this time, unlike the conventional method, there is no need for pretreatment such as etching the gate film, which reduces the risk of deterioration of gate breakdown voltage and TDD.
No deterioration of the B characteristics occurred.6 However, the problem was how to connect the substrate and the gate metal, and this was achieved through the following steps.

(3) Next, as shown in FIG. 4(c), a resist pattern 12 is formed to open the connecting portion between the substrate l and the gate metal, and using this as a mask, the polycrystalline silicon 4 and the gate oxidation IE are formed. 2 is etched continuously.

At this time, the etching method is the same as conventional methods such as plasma etching or RIE using fluorocarbon gas, or RIE using carbon chloride gas, etc. For the oxide film, wet etching using HF or hydrogen fluoride gas is used. Conventional methods such as dry etching may also be used.

(4) Next, as shown in FIG. 1(d), the resist pattern is removed, and N° type impurities are introduced into the polycrystalline silicon 4 by thermal diffusion or ion implantation of As, P, etc. At this time, an N-type impurity layer 6 is formed on the surface of the substrate in the opening 9.

(5) Next, as shown in FIG. 1(e), a metal such as Mo, Ti, W, etc. or metal silicide 115 is formed, so that wiring is formed in the opening 9 only by the metal or metal silicide layer 5. and connected to the first wiring layer. Moreover, this made it possible to connect directly to the diffusion layer 6 formed on the substrate l.

(6) Next, as shown in FIG. 1(f), a gate electrode or wiring layer is formed in a predetermined portion.

(7) Next, as shown in FIG. 1(g), sidewalls 7 and diffusion layers 8 to serve as sources and trains are formed by a conventional method.

As described above, by the manufacturing method of the present invention, deterioration of gate breakdown voltage and TD
We were able to eliminate reliability defects such as DB characteristics.

In the embodiments of the present invention, an example of an N channel region on a P- region formed on a P-type substrate or an N-type substrate has been described. N-
It goes without saying that this can also be applied to the P channel area on the area.

[Effect of the invention 1] By using the manufacturing method of the present invention, in a semiconductor device having a connection portion between a gate wiring layer and a substrate, initial defects due to deterioration of gate breakdown voltage are eliminated, yield is improved,
In addition, breakdown of the insulation film over time has been reduced, improving reliability.

[Brief explanation of the drawing]

FIGS. 1(a) to (g) are explanatory diagrams of the method for manufacturing a semiconductor device of the present invention, FIGS. 2 and 3 are explanatory diagrams of the conventional structure and connection parts, and FIGS. 4(a) to (e) ) is an explanatory diagram of a conventional manufacturing method. In the figure, 1...substrate 2...gate insulating film 3...element isolation insulating film 4...polycrystalline silicon 5...metal or metal silicide film 6...diffusion layer 7... ...Side wall 8...Diffusion layer 9 serving as source or drain...Opening 10...Active region 11...First wiring layer 12...Resist pattern and above Applicant: Seiko Epson Corporation

Claims (2)

[Claims] (1) A step of forming a first insulating film to serve as an element isolation insulating film on a semiconductor substrate, and a step of forming a second insulating film,
a step of forming a polycrystalline silicon layer, a step of forming a first resist pattern for opening a predetermined portion, a step of removing the polycrystalline silicon, a step of removing the second insulating film, and a step of removing the second insulating film. A method for manufacturing a semiconductor device, comprising the steps of removing one resist pattern, introducing impurities, forming a metal or metal silicide film, and forming a gate electrode or wiring pattern. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the step of introducing the impurity is performed after forming the polycrystalline silicon layer.