JPH01280984A - Satellite data broadcast signal receiver - Google Patents

Abstract

PURPOSE:To simplify the extraction and reproduction of independent data by reading a received digital multiplex signal in the transmitting direction and in the orthogonal direction of each frame so as to apply de-interleaving, rearranging the data in the multiplex signal after the de-interleaving by one packet each and storing the result in a data storage memory. CONSTITUTION:After the received digital multiplex signal is stored once in a buffer memory, the data is read laterally and de-interleaved by a de- interleaver 5 and the independent data in the multiplex signal is stored in a data storage memory 10 so as to be consecutive by one packet each. Thus, the independent data is arranged in the order of packet comparatively simply and efficiently and written in the data storage memory 10 required for the processing and a so-called byte memory able to readout in the unit of bytes is used. Moreover, the way of address designation is devised, then the method is realized inexpensively.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a satellite data broadcasting signal receiver that receives a data signal multiplexed with a PCM audio signal of satellite broadcasting, that is, a satellite data broadcasting signal.

(B) Prior art The audio signals in the television satellite broadcasting currently being carried out in Japan are transmitted in a phase-modulated PCM signal format, multiplexed with the video signal, and the PCM audio signal is Several channels are multiplexed together with data signals in a so-called interleave multiplex to form a frame.

FIGS. 2 and 3 show the respective frame structures of the A mode (FIG. 2) and the B mode (FIG. 3) employed in the transmission of the PCNi audio signal. That is, for example, regarding A mode, 10 bits of PCM data at each sample point of the PCM audio signal for 4 channels of audio 1 to audio 4 are horizontally processed along with 15 bits of independent data and a 7 bit BCH code for error correction. (horizontal) direction to form one line, and this one line is arranged in the vertical (vertical) direction for 32 lines, i.e. 32
Samples are arranged, and at the beginning of each row, a 1-bit frame synchronization signal (the first 16 rows) and a control code (
The latter 16 lines) and range bits are added, and these constitute one frame. Then, as shown in the figure, this one frame is phase-modulated in the vertical direction one bit at a time from the upper left corner and transmitted, and when the transmission of that one frame is completed, the first frame is transmitted in the same way. The transmission time per frame is 1m se
It is c. Therefore, the bit rate of the transmission signal is 64
X 32 = 2.048 Mbit/sec.

In addition, in B mode, two channels of PCM audio signals are incremented so that they are positioned alternately in the horizontal and vertical directions, and each PCM audio signal consists of 16 bits of data per sample point. There are some differences between the two modes, but the rest is basically the same as the A mode.
Further explanation will be omitted. Note that the range bit described above represents the compression rate etc. when quantizing the PCM audio signal.

Now, in both modes A and B, an area for transmitting the aforementioned independent data, that is, data signals completely unrelated to the PCM audio signal, such as facsimile signals and character signals, is provided in each frame as shown in the figure. However, the above-mentioned independent data is not only such an independent data area provided in advance, but also 2
In April 1986, the Telecommunications Technology Council wrote an interim report of the Satellite Broadcasting Data Transmission System Committee that PCM audio signals can be transmitted even in areas where PCM audio signals are not actually transmitted among the audio areas for four channels. (dated March 25). Therefore, herein, the area within one frame where no PCM audio signal is transmitted and where independent data is transmitted, including the aforementioned independent data channel, will be referred to as a data multiplex area.

For the transmission of such independent data (hereinafter sometimes referred to simply as data signals), the so-called packet method is used, as is the case with normal data transmission, so one packet of data is The interim report also proposes three methods for interleaving (interpolating) multiplexing the data into the data multiplexing area in each frame. For the sake of simplicity, the vertical multiplexing method, which is one of the three methods, will be described assuming that independent data is multiplexed only in the A mode independent data area. That is, one packet of independent data consists of 288 bits of data,
In the case of vertical multiplexing, the 288
Bit data is inserted one pint at a time in the vertical direction of the independent data area, so 288÷32=9 (32 is the number of vertical bits per frame, see Figure 2), Nine frames are required to complete the transmission of data for a packet. In other words, data for 1 packet is divided and inserted into 5 frames between 9 frames. However, in A mode, the independent data area has a capacity of 15 bits in the horizontal direction, so in the end, 15 packets of independent data can be transmitted in 9 frames (one frame of 9 frames is called 1 super frame). It will be done. The same thing can be said in the case of B mode.

(c) Problems to be Solved by the Invention As mentioned above, the independent data that is multiplexed with the PCM audio signal of satellite broadcasting and transmitted as a digital multiplexed signal is divided into parts and inserted between several frames. Therefore, in order to reproduce and use the independent data on the receiving side, the independent data must be extracted from the digital multiplexed signal and arranged in packets.

Therefore, an object of the present invention is to provide a satellite data broadcasting signal receiver that can realize extraction and reproduction of such independent data relatively easily and at low cost.

(d) Means for Solving the Problems In the receiver of the present invention, the received digital multiplexed signal is temporarily stored in a buffer memory and then laterally (as shown in FIGS. 2 and 3)
After reading out and deinterleaving (see figure), the independent data in the multiplexed signal is stored in a data storage memory so as to be continuous one packet at a time.

Further, a memory in which writing and reading are performed in byte units is used as the data storage memory, and writing of the data to this memory is performed by writing the data into the memory in which each bit of input data is to be stored. Data in a 1-byte area in the memory is read, 1 bit in the read 1-byte data is replaced with 1 bit of the input data, and the data is written in the 1-byte area again.

Further, a first addressing means for specifying an address corresponding to each packet by counting tallocks in each horizontal row of the data multiplexed area in each readout period in the digital multiplexed signal after deinterleaving; The address of the data storage memory is designated by second addressing means that designates an address corresponding to each bit within one packet by counting pulses generated for each horizontal readout. .

In particular, when independent data is interpolated vertically within the data multiplex area, the first addressing means is configured to perform the same operation during the readout period of each horizontal row, so that the independent data When interpolation is performed in the diagonal direction within the data multiplexing area, the first addressing means is configured such that its count output value is decreased by one every readout period of each horizontal row.

(e) Effects According to the present invention as described above, independent data can be arranged relatively easily and efficiently in the order of packets, and moreover, the data can be written to the data storage memory necessary for this processing.
Since it is possible to use a so-called byte memory in which reading is performed in byte units, and the method of addressing is devised, it can be realized at low cost.

(f) Embodiment FIG. 1 shows an embodiment of the receiver according to the present invention.
Hereinafter, in this receiver, the model shown in FIG. 4(a), that is, A.
A case will be described in which a satellite broadcasting signal in which independent data is vertically interpolated only in the independent data area of a mode is received. In the figure, (1) is an input terminal for a subcarrier channel signal separated from a satellite broadcasting signal after FM demodulation. The subcarrier channel signal is demodulated by a 4-phase DPSK demodulation circuit (2) to become the aforementioned digital multiplexed signal containing a PCM audio signal and an independent data signal. Since this multiplexed signal is derived one bit at a time in the transmission order shown in FIG.
FT) is output.

On the other hand, the multiplexed signal is sent to a descrambling circuit (4) in the order of reception.
) is also input to tt, where the synchronization signal detection circuit (3)
A frame detection pulse (FT) given from is obtained to descramble the PC-1 audio signal, independent data signal, etc. within each frame of the multiplexed signal. That is, the above P
Since CM audio signals, independent data signals, etc. are scrambled to reduce the error rate during DPSK modulation, this scrambling is performed.

This descrambled digital multiplexed signal is then input to the deinterleaving circuit (5). The digital multiplexed signal input to this deinterleaving circuit (5) is once stored in the buffer memory in the circuit in frame units in the order of input, and then read out in the horizontal direction (reading direction in Figure 2) as described later. It is input to the write control circuit (11).

Note that the descrambling circuit (4), deinterleaving circuit (5), etc. are supplied with a clock (CK) of 2,048 MHz reproduced by the DPSK demodulating circuit (2).

The superframe detection circuit (6) also detects one of the digital multiplexed signals output from the descrambler circuit (4).
9 Constructs a superframe by detecting the flag set in the 6-bit control code and the flag set in the node.
The first frame in the frames is detected, and a super frame detection pulse (ST) is output every time the first frame is detected.

On the other hand, the counter control circuit (7) is specifically, as shown in FIG. 3, a 6-bit counter that is cleared by the frame detection pulse (FT) and receives the aforementioned 2.0t8MHz clock (CK) as its clock input. (71) and AND gate (72) (73) (74) and NOAH gate (75) (7
6) and an inverter (77), and the first, second, and third control pulses (C5,) (C5,) ( shown in FIG.
C3,) is output. The high level period of the first control pulse (CS, ) corresponds to the read period of one row of WL in the independent data area, and one period of the second control pulse (C3t) corresponds to one cycle of the second control pulse (C3t).
The third control pulse (C5s) is generated every 64th tarokk (CK), corresponding to a period of one line of the multiplexed signal product of the frame.

The first control pulse (C5,) is the third control pulse (C5,).
C3, ) is given as a count enable signal for the 4-bit first counter (8), and during its high level period, this counter (8) receives the clock (CK).
is counted. FIG. 7 shows the operation of this first counter (8), and (Qa, ) to (Qa, ) are the outputs of its respective bits. °Also, the second control channel (C
5t) is given as the clock of the 9-bit second counter (9) which is cleared by the superframe detection pulse (ST). FIG. 8 shows the operation of this second counter (9), and (Qb,) to (Qbs) are the outputs of each bit thereof.

FIG. 11 shows independent data areas within one superframe of a digital multiplexed signal, with A1°Ay, . . . , A
ol, B, , B, . . . +BI$8, etc. schematically represent the data of each bit in each one packet in this area. Each of these data is processed by the deinterleaving circuit shown in Figure 1 (
5) in the horizontal direction of FIG. 11 by the clock (CK). Therefore, the 4-bit output (Qa, ) to (Qa, ) of the first counter (8) represents the number (1 to 15) of each packet of the above data! The outputs (Qbo) to (Qbl) of the second counter (9) represent the number (1 to 288) of the bit position within each packet. Further, when the above-mentioned bit position is expressed using a byte number, the upper 6 bits (Qb, ) to (Qbl) of the second counter output are
) represents the byte number (1 to 36), and the lower 3 bits (
Qb, ) to (Qb, ) represent the number of the bit position within each byte.

I will do it.

Returning to FIG. 1 again, (10) is a RAM as a data storage memory, to which writing and reading can only be done in byte units. The output of the first counter (8) (
Qa= )-(Qa, ) and the upper outputs (Qbl) to (Qbl) of the second counter (9) are given, and the structure of the address signal is as shown in FIG. Then, writing to the RAM (10) is performed by the write control circuit (
11) and its RAM (10)
1 byte of data read from (D0+) ~ (Dol
) are latched by a latch circuit (12), and a timing pulse generation circuit (13) generates a write control signal (WR) and a read control signal (R) necessary for these operations.
D), output enable signal (EN), etc. (see Figure 10)
give.

Specifically, as shown in FIG. 9, the write control circuit (11) outputs the lower three bits of the second counter (9) (Qb6
) to (Qb,) as inputs, and 1-bit input data ( Di) latched by the latch circuit (12)
Eight selector circuits (111) that switch and derive one pin out of the data (Do+) to (Dos) of the byte.
- (118), and a tristate buffer circuit (119) that outputs each output to the RAM (IQ) only during the high level period of the output enable signal (EN).

Therefore, now the leftmost data (A
I) is input as input data Di (t in Figure 10), this data is the 42nd bit (column N) counting horizontally from the range bit next to the synchronization signal bit.
α is 43 (see Figure 2), and as can be seen from Figure 7, the output of the first counter (8) at this time is Q = o =
Q −+ = Q, −= Q −* = O.

On the other hand, at this time, the second counter (9) receives the second control pulse (
C5,) (see Figure 6), the output is Ql)0=l, Qbl=Q1), =
. . .=Ql),=O, and the address code of the RAM (10) becomes as shown in FIG. 13 (a). Now, assuming that all the data in RAM (10) is O before this t1, the R specified by the address signal and read out during the high period of the read control signal (RD)
1st byte data (D, l) of A M (10) ~
(D, , ) are all 0, that is, this data is latched by the latch circuit (12) during the low period of the latch control signal (LT) and is output.

On the other hand, the decoder (110) in the write control circuit (11)
As mentioned above, the input of
Only 1 becomes l, and all others become 0. Accordingly, the aforementioned input data (A,) is output only from the first selector circuit (111), and the other second to eighth selector circuits (112) to (
118) outputs the output data 0 of the latch circuit (12), so the tri-state buffer circuit (119)
The 1-byte data input to A is either 0 or 1). This data is output to the RAM (10) at the timing of the high period of the output enable signal (EN), and is outputted to the first memory area (Fig. 13) of the RAM (10) during the high period of the write control signal (WR). It is stored in the row (1 byte capacity).

Next, the second data from the left end of the first row in Figure 11 (B
, ) is input, the output of the first counter (8) is Qa
, =1, Qa+ = Qa* = Qa+ = O1 Since the output of the second counter (9) is exactly the same as in the previous case, the address signal becomes (c) in FIG.

Therefore, 1 byte of data is stored in the 64th row of the memory area of RAM (10).

Thereafter, when the leftmost data (A7.6) of the 286th line (30th line in the 9th frame) of FIG. Since the output of the counter (9) is 286=100011110, the address signal of the RAM (10) becomes as shown in FIG. =6. Therefore, RAM
The 6th bit of the 1-byte data of 100 yen on the 36th line in (10) is rewritten with the input data (Awes), so the data on the 36th line is valid.

In this way, the contents of RAM (10) are rewritten in 1-byte units for each bit of input data, and when all 15 packets of data in one superframe have been stored, the data will be rewritten as shown in Figure 13. 288 of 1 packet each
Bit data is arranged and stored in consecutive addresses in the memory area in bit order. However, there is a blank space of 64-36 = 28 bytes between each of the 9 packets stored in RAM (10), so the capacity of RAM (10) must be at least 64 x 9 = 576 bytes. becomes.

In addition, in FIG. 1, the first counter (8) is cleared by the third control pulse (C53), but
It may be cleared by a frame detection pulse (FT). However, in that case, the AND gate (73) in FIG. 5 may be configured to output a high level at the output value 57 of the counter (71). Further, at this time, the AND gate (74) is of course unnecessary.

The above has described an embodiment in which an independent data signal interpolated and multiplexed vertically in a satellite broadcasting signal is received, but as mentioned above, there is a diagonal multiplexing method as another multiplexing method for independent data. Hereinafter, this diagonal multiplexing method will be explained, and then an embodiment will be described in which independent data signals interpolated and multiplexed using this method are received.

That is, in the diagonal multiplexing method, 288 bits of independent data in one packet are interpolated diagonally within the data multiplexing area so that they are shifted one bit at a time in both the vertical and horizontal directions. Therefore, in a model in which independent data is multiplexed only in the independent data area of mode A using this multiplexing method, 288 bits of data for one packet is
It is inserted into one superframe by diagonally repeating 5 bits at a time. In this case as well, as can be seen from FIG. 17, which shows the details of the independent data area in FIG. 4(b) in the same way as FIG. 11, a total of 15 packets of data are transmitted in one superframe. It is.

Now, even for independent data multiplexed in a diagonal direction as shown in FIG. 17, the receiver of the present invention stores it in the memory consecutively, one packet at a time, as shown in FIG. 13. However, the overall configuration of the receiver in this case is the first one.
It is the same as the one shown in the figure, with the configuration around the first counter (8) being slightly changed.

That is, first, assuming that the diagonally multiplexed data in FIG. 17 is processed using the configuration shown in FIG.
The output of the first counter (8) that counts K) (Qa=
) to (Qa, ) indicate packet numbers to which data corresponding to each output value belongs, as in the case of FIG. That is,
For example, when reading data C1, the output value of the first counter (8) is 2, indicating packet number 2 to which this data C1 belongs. Next, in the read state of the data in the second row of FIG. 17, the output (Qa,
) to (Qa, ) indicate numbers that are 1 larger than the above packet number. That is, when reading data C1, the output value of the first counter (8) is 3, which is 61 larger than packet number 2 to which this data C1 belongs. Below, the first
In the third and fourth lines of FIG. 7, the output value of the first counter (8) becomes a value that is sequentially incremented by one from the packet number.

Therefore, conversely, the output (Qa.) of the first counter (8)
If ~(Qa,) is configured so that it is carried down by 1 for each row in FIG. 17, each output value becomes the packet number to which the data currently being read belongs, as in the case of vertical multiplexing in FIG. 11. will always be shown. That is, in the previous example, the output value of the first counter (8) becomes 2 when data C1 is read in the first line of FIG. 17, and becomes 2 when data C1 is read in the second line.
, and when data C1 is read in the third row, both are set to 2.

On the other hand, the outputs (Qb, ) to (Qba) of the second counter (9) in FIG. 1, which counts the second control pulse (C5*) generated every time one row of data in FIG. 17 is read, are ,
In the case of this figure 17, each 1 is exactly the same as the case of figure 11.
It represents the byte number and bit number within the packet.

Therefore, if the first counter (8) is changed to operate as described above, the output of the first counter (8) (Qa=) - (Qa=) and the output of the second counter (9) ( Vertical multiplexing (first
The RAM (10) can be addressed in exactly the same way as in the embodiment shown in Figure 1), and the second counter (
By adjusting the outputs (Qbo) to (Qb) of 9), the write control circuit (11) in Figure 1 (see Figure 9 for details) can be controlled in exactly the same way, and the data in Figure 17 can be controlled without changing anything else. As shown in FIG. 13, it can be stored in the RAM (10).

Therefore, FIG. 14 shows the configuration around the first counter (8) used in the receiver in the case of diagonal multiplexing as described above. That is, the first counter (8) in the same figure is operated by two people and the output of the AND gate (81) corresponding to the output value 14 of this counter and the first control pulse (C5,) (see FIG. 16 for both). The output of (82) or the inverted output of the inverter (83) of the super frame detection pulse (ST) (see Figure 15) is the or game)
(84) as a clear signal, and when the clear signal is at a low level, it is cleared (synchronously cleared) by a clock (CK).

Therefore, the output (Qa.) of the first counter (8)
~(Qa, ) and its count output value change as shown in FIGS. 15 and 16, respectively. That is, the first
During the pulse period (high level period) of the first control pulse (C5,) at the left end of FIGS. 15 and 16, which corresponds to the read period of the data in the first row of FIG. 7, the output of the first counter (8) The value is determined by the clock (CK) as shown in the figure <0. 1. 2. ...14, and during the pulse period of the first control pulse (C5,) corresponding to the next second row, the output value of the first counter (8) is 14, 0, 1... ...
, 13, and similarly in the next third line 13. 1
4. 0. It changes like 1°..., 12. That is,
The output value of the first counter (8) is decremented by 1 for each row of data in FIG. 17, and thus the above-described operation is achieved.

In addition, the fact that the first control pulse (C3,) is slightly out of phase with the clock (CK) in Figure 16 indicates a time delay in the counter control circuit (7) (see Figure 5 for details). ,
Also, at time t1 and time t in the figure, the first counter (8
) is cleared, but this counter is not cleared at time t because synchronous clearing is used.

Note that in the case of the vertical multiplexing method and the diagonal multiplexing method, examples have been described so far in which independent data is inserted only in the independent data area, but in the case of B mode or when a PCM audio signal is not transmitted. Even in the case of satellite broadcasting in which the above-mentioned data is multiplexed in an area, the same implementation is possible. That is, in that case, the first control pulse (C5+) having a pulse period corresponding to the area where the independent data is inserted should be generated, and the clearing timing of the first counter (8) should be changed as appropriate according to the above pulse period. That's a good translation.

(g) Effects of the Invention According to the receiver of the present invention, several packets of independent data are interpolated and multiplexed between several frames of a digital multiplex signal of satellite broadcasting using a vertical multiplexing method or a diagonal multiplexing method. Even if the data is stored in a packet-by-packet format, the data can be easily read out and used as needed.

Moreover, since an inexpensive memory that writes and reads data in byte units can be used as the memory, and the circuit for writing can be easily configured, it can be realized at a low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of main parts of an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing frame Ill configuration of a digital multiplex signal of satellite broadcasting, and FIGS. ) are diagrams showing the multiplexing positions of independent data within a frame by different multiplexing methods, FIG. 5 is a block diagram showing details of the counter control circuit of the above embodiment, and FIGS. 6, 7, and 8.
9 is a block diagram showing details of the write control circuit, FIG. 10 is a diagram showing its operation time chart, and FIG. 12 is a schematic diagram showing the independent data multiplexed by the vertical multiplexing method, FIG. 12 is a diagram showing the structure of the address signal of the data storage memory, FIG. 13 is a memory map diagram of the above memory, and FIG. A block diagram showing the main parts of another embodiment, FIGS. 15 and 16 are diagrams showing its operation time chart, and FIG. 17 shows independent data multiplexed by the diagonal multiplexing method in the same way as FIG. 11. It is a diagram. (7): Counter control circuit, (8) (9): 1st 2nd
Counter, (10): Data storage memory, (11) Write control circuit.

Claims (4)

[Claims] (1) A satellite data broadcast signal receiver that receives a satellite data broadcast signal transmitted as a digital multiplex signal in which several packets of data are divided and inserted into the data multiplex area in each frame of an interleaf-multiplexed PCM audio signal. In this method, the received digital multiplexed signal is deinterleaved by reading it out in a direction orthogonal to the transmission direction of each frame, and the data in the multiplexed signal after deinterleaving is arranged so that it is continuous for one packet at a time. A satellite data broadcasting signal receiver characterized in that data is stored in a data storage memory. (2) The data storage memory is a memory in which writing and reading are performed in byte units, and when writing the data to this memory, one bit should be stored for each bit of input data. Read the data in a 1-byte area in the memory, replace 1 bit in the read 1-byte data with 1 bit in the input data, and perform the above step 1.
The satellite data broadcasting signal receiver according to claim 1, wherein the data is written in the byte area again. (3) The data is transmitted as a digital multiplexed signal that is interpolated vertically within the multiplexed area so that one packet is completed in several frames, and one horizontal row of the data multiplexed area within one frame of this digital multiplexed signal. a first addressing means for specifying an address corresponding to each packet by counting clocks in each readout period; by second addressing means specifying an address corresponding to each bit in the packet;
3. A satellite data broadcasting signal receiver according to claim 2, wherein an address of said data storage memory is specified. (4) The data is transmitted as a digital multiplexed signal that is diagonally interpolated within the multiplexed area so that one packet is completed in several frames, and one row horizontally of the data multiplexed area within one frame of this digital multiplexed signal. A first controller that specifies an address corresponding to each packet of data by counting clocks for each read period of the data and operating so that the count output value is decreased by 1 for each read period of each horizontal row. by an addressing means and a second addressing means for designating an address corresponding to each bit in one packet by counting pulses generated each time one horizontal row of the multiplexed area is read;
3. A satellite data broadcasting signal receiver according to claim 2, wherein an address of said data storage memory is designated.